tree 8b68eceaf7a1935ab9a07247e242494c9f1c4605
parent 2985c02f798ba8248a9168a9f33a74d90c0c5445
author Sanjay Patel <spatel@rotateright.com> 1597192070 -0400
committer Sanjay Patel <spatel@rotateright.com> 1597192202 -0400

[VectorCombine] add safety check for 0-width register

Based on post-commit discussion in D81766, Hexagon sets this to "0".
I'll see if I can come up with a test, but making the obvious
code fix first to unblock that target.