| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s |
| --- | |
| define dso_local void @legal_vaddv_s32(i16* nocapture readonly %a, i32* %c, i32 %N) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* |
| %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 4 |
| %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) |
| %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> |
| %tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp10) |
| store i32 %tmp11, i32* %store.addr |
| %store.next = getelementptr i32, i32* %store.addr, i32 1 |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| ret void |
| } |
| |
| define dso_local void @legal_vaddv_s16(i16* nocapture readonly %a, i32* %c, i32 %N) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <8 x i16>* |
| %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 8 |
| %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) |
| %sext = sext <8 x i16> %wide.masked.load to <8 x i32> |
| %tmp11 = call i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32> %sext) |
| store i32 %tmp11, i32* %store.addr |
| %store.next = getelementptr i32, i32* %store.addr, i32 1 |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 8 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| ret void |
| } |
| |
| define dso_local void @legal_vaddv_s8(i8* nocapture readonly %a, i32* %c, i32 %N) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 7 |
| %tmp1 = lshr i32 %tmp, 3 |
| %tmp2 = shl nuw i32 %tmp1, 3 |
| %tmp3 = add i32 %tmp2, -7 |
| %tmp4 = lshr i32 %tmp3, 3 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* |
| %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 16 |
| %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) |
| %sext = sext <16 x i8> %wide.masked.load to <16 x i32> |
| %tmp11 = call i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32> %sext) |
| store i32 %tmp11, i32* %store.addr |
| %store.next = getelementptr i32, i32* %store.addr, i32 1 |
| %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| ret void |
| } |
| |
| define dso_local i32 @legal_vaddva_s32(i16* nocapture readonly %a, i32 %N) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* |
| %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 4 |
| %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) |
| %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> |
| %tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %tmp10) |
| %acc.next = add i32 %tmp11, %acc |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] |
| ret i32 %res |
| } |
| |
| define dso_local void @illegal_vaddv_s32(i16* nocapture readonly %a, i32* %c, i32 %N) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* |
| %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 4 |
| %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) |
| %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> |
| %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> |
| %tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %not) |
| store i32 %tmp11, i32* %store.addr |
| %store.next = getelementptr i32, i32* %store.addr, i32 1 |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| ret void |
| } |
| |
| define dso_local i32 @illegal_vaddva_s32(i16* nocapture readonly %a, i32 %N) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* |
| %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 4 |
| %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) |
| %tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32> |
| %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> |
| %tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %not) |
| %acc.next = add i32 %tmp11, %acc |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] |
| ret i32 %res |
| } |
| |
| define dso_local void @illegal_vaddv_u32(i16* nocapture readonly %a, i32* %c, i32 %N) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* |
| %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 4 |
| %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) |
| %tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32> |
| %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> |
| %tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %not) |
| store i32 %tmp11, i32* %store.addr |
| %store.next = getelementptr i32, i32* %store.addr, i32 1 |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| ret void |
| } |
| |
| define dso_local i32 @illegal_vaddva_u32(i16* nocapture readonly %a, i32 %N) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>* |
| %tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 4 |
| %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef) |
| %tmp10 = zext <4 x i16> %wide.masked.load to <4 x i32> |
| %not = xor <4 x i32> %tmp10, <i32 -1, i32 -1, i32 -1, i32 -1> |
| %tmp11 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %not) |
| %acc.next = add i32 %tmp11, %acc |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 4 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] |
| ret i32 %res |
| } |
| |
| define dso_local void @illegal_vaddv_s16(i8* nocapture readonly %a, i32* %c, i32 %N, <8 x i16> %pass) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i8* %lsr.iv to <8 x i8>* |
| %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 8 |
| %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef) |
| %sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16> |
| %sub = sub <8 x i16> %sext.wide, %pass |
| %reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %sub) |
| %sext.reduce = sext i16 %reduce to i32 |
| store i32 %sext.reduce, i32* %store.addr |
| %store.next = getelementptr i32, i32* %store.addr, i32 1 |
| %scevgep = getelementptr i8, i8* %lsr.iv, i32 8 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| ret void |
| } |
| |
| define dso_local i32 @illegal_vaddva_s16(i8* nocapture readonly %a, i32 %N, <8 x i16> %pass) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] |
| %lsr.iv17 = bitcast i8* %lsr.iv to <8 x i8>* |
| %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 8 |
| %wide.masked.load = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* %lsr.iv17, i32 1, <8 x i1> %tmp8, <8 x i8> undef) |
| %sext.wide = sext <8 x i8> %wide.masked.load to <8 x i16> |
| %sub = sub <8 x i16> %sext.wide, %pass |
| %reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %sub) |
| %sext.reduce = sext i16 %reduce to i32 |
| %acc.next = add i32 %sext.reduce, %acc |
| %scevgep = getelementptr i8, i8* %lsr.iv, i32 8 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] |
| ret i32 %res |
| } |
| |
| define dso_local void @illegal_vaddv_u16(i16* nocapture readonly %a, i32* %c, i32 %N, <8 x i16> %pass) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <8 x i16>* |
| %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 8 |
| %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) |
| %sub = sub <8 x i16> %wide.masked.load, %pass |
| %reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %sub) |
| %zext.reduce = zext i16 %reduce to i32 |
| store i32 %zext.reduce, i32* %store.addr |
| %store.next = getelementptr i32, i32* %store.addr, i32 1 |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 8 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| ret void |
| } |
| |
| define dso_local i32 @illegal_vaddva_u16(i16* nocapture readonly %a, i32 %N, <8 x i16> %pass) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 3 |
| %tmp1 = lshr i32 %tmp, 2 |
| %tmp2 = shl nuw i32 %tmp1, 2 |
| %tmp3 = add i32 %tmp2, -4 |
| %tmp4 = lshr i32 %tmp3, 2 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] |
| %lsr.iv17 = bitcast i16* %lsr.iv to <8 x i16>* |
| %tmp8 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 8 |
| %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv17, i32 2, <8 x i1> %tmp8, <8 x i16> undef) |
| %sub = sub <8 x i16> %wide.masked.load, %pass |
| %reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %sub) |
| %zext.reduce = zext i16 %reduce to i32 |
| %acc.next = add i32 %zext.reduce, %acc |
| %scevgep = getelementptr i16, i16* %lsr.iv, i32 8 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] |
| ret i32 %res |
| } |
| |
| define dso_local void @illegal_vaddv_s8(i8* nocapture readonly %a, i32* %c, i32 %N, <16 x i8> %pass) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 7 |
| %tmp1 = lshr i32 %tmp, 3 |
| %tmp2 = shl nuw i32 %tmp1, 3 |
| %tmp3 = add i32 %tmp2, -7 |
| %tmp4 = lshr i32 %tmp3, 3 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* |
| %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 16 |
| %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) |
| %xor = xor <16 x i8> %wide.masked.load, %pass |
| %reduce = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %xor) |
| %sext.reduce = sext i8 %reduce to i32 |
| store i32 %sext.reduce, i32* %store.addr |
| %store.next = getelementptr i32, i32* %store.addr, i32 1 |
| %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| ret void |
| } |
| |
| define dso_local i32 @illegal_vaddva_s8(i8* nocapture readonly %a, i32 %N, <16 x i8> %pass) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 7 |
| %tmp1 = lshr i32 %tmp, 3 |
| %tmp2 = shl nuw i32 %tmp1, 3 |
| %tmp3 = add i32 %tmp2, -7 |
| %tmp4 = lshr i32 %tmp3, 3 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] |
| %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* |
| %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 16 |
| %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) |
| %xor = xor <16 x i8> %wide.masked.load, %pass |
| %reduce = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %xor) |
| %sext.reduce = sext i8 %reduce to i32 |
| %acc.next = add i32 %sext.reduce, %acc |
| %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] |
| ret i32 %res |
| } |
| |
| define dso_local void @illegal_vaddv_u8(i8* nocapture readonly %a, i32* %c, i32 %N, <16 x i8> %pass) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 7 |
| %tmp1 = lshr i32 %tmp, 3 |
| %tmp2 = shl nuw i32 %tmp1, 3 |
| %tmp3 = add i32 %tmp2, -7 |
| %tmp4 = lshr i32 %tmp3, 3 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %store.addr = phi i32* [ %c, %vector.ph ], [ %store.next, %vector.body ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* |
| %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 16 |
| %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) |
| %xor = xor <16 x i8> %wide.masked.load, %pass |
| %reduce = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %xor) |
| %zext.reduce = zext i8 %reduce to i32 |
| store i32 %zext.reduce, i32* %store.addr |
| %store.next = getelementptr i32, i32* %store.addr, i32 1 |
| %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| ret void |
| } |
| |
| define dso_local i32 @illegal_vaddva_u8(i8* nocapture readonly %a, i32 %N, <16 x i8> %pass) { |
| entry: |
| %cmp9 = icmp eq i32 %N, 0 |
| %tmp = add i32 %N, 7 |
| %tmp1 = lshr i32 %tmp, 3 |
| %tmp2 = shl nuw i32 %tmp1, 3 |
| %tmp3 = add i32 %tmp2, -7 |
| %tmp4 = lshr i32 %tmp3, 3 |
| %tmp5 = add nuw nsw i32 %tmp4, 1 |
| br i1 %cmp9, label %exit, label %vector.ph |
| |
| vector.ph: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %tmp5) |
| br label %vector.body |
| |
| vector.body: ; preds = %vector.body, %vector.ph |
| %lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %tmp5, %vector.ph ] |
| %lsr.iv = phi i8* [ %scevgep, %vector.body ], [ %a, %vector.ph ] |
| %tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ] |
| %acc = phi i32 [ 0, %vector.ph ], [ %acc.next, %vector.body ] |
| %lsr.iv17 = bitcast i8* %lsr.iv to <16 x i8>* |
| %tmp8 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %tmp7) |
| %tmp9 = sub i32 %tmp7, 16 |
| %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv17, i32 1, <16 x i1> %tmp8, <16 x i8> undef) |
| %xor = xor <16 x i8> %wide.masked.load, %pass |
| %reduce = call i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8> %xor) |
| %zext.reduce = zext i8 %reduce to i32 |
| %acc.next = add i32 %zext.reduce, %acc |
| %scevgep = getelementptr i8, i8* %lsr.iv, i32 16 |
| %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1) |
| %tmp13 = icmp ne i32 %tmp12, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv1, -1 |
| br i1 %tmp13, label %vector.body, label %exit |
| |
| exit: ; preds = %vector.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %vector.body ] |
| ret i32 %res |
| } |
| |
| define hidden i32 @regalloc_legality_vaddva_u32(i16* %x, i16* %y, i32 %n) { |
| entry: |
| %cmp22 = icmp sgt i32 %n, 0 |
| %0 = add i32 %n, 3 |
| %1 = icmp slt i32 %n, 4 |
| %smin = select i1 %1, i32 %n, i32 4 |
| %2 = sub i32 %0, %smin |
| %3 = lshr i32 %2, 2 |
| %4 = add nuw nsw i32 %3, 1 |
| br i1 %cmp22, label %while.body.preheader, label %while.end |
| |
| while.body.preheader: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %4) |
| br label %while.body |
| |
| while.body: ; preds = %while.body.preheader, %while.body |
| %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] |
| %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] |
| %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] |
| %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] |
| %5 = phi i32 [ %4, %while.body.preheader ], [ %6, %while.body ] |
| %tmp3 = bitcast i16* %y.addr.025 to <4 x i16>* |
| %tmp1 = bitcast i16* %x.addr.026 to <4 x i16>* |
| %tmp = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.023) |
| %tmp2 = tail call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %tmp1, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer) |
| %zext.wide.1 = zext <4 x i16> %tmp2 to <4 x i32> |
| %tmp4 = tail call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %tmp3, i32 2, <4 x i1> %tmp, <4 x i16> zeroinitializer) |
| %zext.wide.2 = zext <4 x i16> %tmp4 to <4 x i32> |
| %or = or <4 x i32> %zext.wide.1, %zext.wide.2 |
| %reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %or) |
| %acc.next = add i32 %reduce, %acc |
| %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 4 |
| %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 4 |
| %sub = add nsw i32 %n.addr.023, -4 |
| %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) |
| %7 = icmp ne i32 %6, 0 |
| br i1 %7, label %while.body, label %while.end |
| |
| while.end: ; preds = %while.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] |
| ret i32 %res |
| } |
| |
| define hidden i32 @regalloc_legality_vaddv_u16(i16* %x, i16* %y, i32 %n) { |
| entry: |
| %cmp22 = icmp sgt i32 %n, 0 |
| %0 = add i32 %n, 7 |
| %1 = icmp slt i32 %n, 8 |
| %smin = select i1 %1, i32 %n, i32 8 |
| %2 = sub i32 %0, %smin |
| %3 = lshr i32 %2, 3 |
| %4 = add nuw nsw i32 %3, 1 |
| br i1 %cmp22, label %while.body.preheader, label %while.end |
| |
| while.body.preheader: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %4) |
| br label %while.body |
| |
| while.body: ; preds = %while.body.preheader, %while.body |
| %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] |
| %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] |
| %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] |
| %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] |
| %5 = phi i32 [ %4, %while.body.preheader ], [ %6, %while.body ] |
| %tmp3 = bitcast i16* %y.addr.025 to <8 x i16>* |
| %tmp1 = bitcast i16* %x.addr.026 to <8 x i16>* |
| %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023) |
| %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) |
| %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) |
| %or = or <8 x i16> %tmp2, %tmp4 |
| %reduce = call i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16> %or) |
| %zext.reduce = zext i16 %reduce to i32 |
| %acc.next = add i32 %zext.reduce, %acc |
| %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8 |
| %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8 |
| %sub = add nsw i32 %n.addr.023, -8 |
| %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) |
| %7 = icmp ne i32 %6, 0 |
| br i1 %7, label %while.body, label %while.end |
| |
| while.end: ; preds = %while.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] |
| ret i32 %res |
| } |
| |
| define hidden i32 @regalloc_illegality_vaddva_s32(i16* %x, i16* %y, i16* %z, i32 %n) { |
| entry: |
| %cmp22 = icmp sgt i32 %n, 0 |
| %0 = add i32 %n, 7 |
| %1 = icmp slt i32 %n, 8 |
| %smin = select i1 %1, i32 %n, i32 8 |
| %2 = sub i32 %0, %smin |
| %3 = lshr i32 %2, 3 |
| %4 = add nuw nsw i32 %3, 1 |
| br i1 %cmp22, label %while.body.preheader, label %while.end |
| |
| while.body.preheader: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %4) |
| br label %while.body |
| |
| while.body: ; preds = %while.body.preheader, %while.body |
| %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] |
| %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] |
| %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] |
| %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] |
| %5 = phi i32 [ %4, %while.body.preheader ], [ %6, %while.body ] |
| %tmp3 = bitcast i16* %y.addr.025 to <8 x i16>* |
| %tmp1 = bitcast i16* %x.addr.026 to <8 x i16>* |
| %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023) |
| %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) |
| %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) |
| %tmp5 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1) |
| %tmp6 = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 0) |
| %mul = add <4 x i32> %tmp5, %tmp6 |
| %reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %mul) |
| %acc.next = add i32 %reduce, %acc |
| %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8 |
| %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8 |
| %sub = add nsw i32 %n.addr.023, -8 |
| %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) |
| %7 = icmp ne i32 %6, 0 |
| br i1 %7, label %while.body, label %while.end |
| |
| while.end: ; preds = %while.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] |
| ret i32 %res |
| } |
| |
| define hidden i32 @illegal_vmull_non_zero(i16* %x, i16* %y, i16* %z, i32 %n) { |
| entry: |
| %cmp22 = icmp sgt i32 %n, 0 |
| %0 = add i32 %n, 7 |
| %1 = icmp slt i32 %n, 8 |
| %smin = select i1 %1, i32 %n, i32 8 |
| %2 = sub i32 %0, %smin |
| %3 = lshr i32 %2, 3 |
| %4 = add nuw nsw i32 %3, 1 |
| br i1 %cmp22, label %while.body.preheader, label %while.end |
| |
| while.body.preheader: ; preds = %entry |
| call void @llvm.set.loop.iterations.i32(i32 %4) |
| br label %while.body |
| |
| while.body: ; preds = %while.body.preheader, %while.body |
| %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ] |
| %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ] |
| %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ] |
| %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ] |
| %5 = phi i32 [ %4, %while.body.preheader ], [ %6, %while.body ] |
| %tmp3 = bitcast i16* %y.addr.025 to <8 x i16>* |
| %tmp1 = bitcast i16* %x.addr.026 to <8 x i16>* |
| %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023) |
| %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) |
| %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer) |
| %mul = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1) |
| %reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %mul) |
| %acc.next = add i32 %reduce, %acc |
| %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8 |
| %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8 |
| %sub = add nsw i32 %n.addr.023, -8 |
| %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1) |
| %7 = icmp ne i32 %6, 0 |
| br i1 %7, label %while.body, label %while.end |
| |
| while.end: ; preds = %while.body, %entry |
| %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ] |
| ret i32 %res |
| } |
| |
| declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>) |
| declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) |
| declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>) |
| declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>) |
| declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>) |
| declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) |
| declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>) |
| declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>) |
| declare i16 @llvm.experimental.vector.reduce.add.v8i16(<8 x i16>) |
| declare i32 @llvm.experimental.vector.reduce.add.v16i32(<16 x i32>) |
| declare i8 @llvm.experimental.vector.reduce.add.v16i8(<16 x i8>) |
| declare void @llvm.set.loop.iterations.i32(i32) |
| declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) |
| declare <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16>, <8 x i16>, i32, i32) |
| declare <4 x i1> @llvm.arm.mve.vctp32(i32) |
| declare <8 x i1> @llvm.arm.mve.vctp16(i32) |
| declare <16 x i1> @llvm.arm.mve.vctp8(i32) |
| |
| ... |
| --- |
| name: legal_vaddv_s32 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: legal_vaddv_s32 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 |
| ; CHECK: bb.1.vector.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $lr, $r0, $r1 |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg :: (load 8 from %ir.lsr.iv17, align 2) |
| ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg |
| ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.exit: |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $r12 |
| $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| |
| bb.1.vector.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg |
| $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.exit: |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| |
| ... |
| --- |
| name: legal_vaddv_s16 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: legal_vaddv_s16 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2 |
| ; CHECK: bb.1.vector.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $lr, $r0, $r1 |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg :: (load 16 from %ir.lsr.iv17, align 2) |
| ; CHECK: renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg |
| ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.exit: |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $r12 |
| $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| |
| bb.1.vector.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) |
| renamable $r12 = MVE_VADDVs16no_acc killed renamable $q0, 0, $noreg |
| $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.exit: |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| |
| ... |
| --- |
| name: legal_vaddv_s8 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: legal_vaddv_s8 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| ; CHECK: $lr = MVE_DLSTP_8 killed renamable $r2 |
| ; CHECK: bb.1.vector.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $lr, $r0, $r1 |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 0, killed $noreg :: (load 16 from %ir.lsr.iv17, align 1) |
| ; CHECK: renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg |
| ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.exit: |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $r12 |
| $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| |
| bb.1.vector.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) |
| renamable $r12 = MVE_VADDVs8no_acc killed renamable $q0, 0, $noreg |
| $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.exit: |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| |
| ... |
| --- |
| name: legal_vaddva_s32 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: legal_vaddva_s32 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCBZ $r1, %bb.4 |
| ; CHECK: bb.1.vector.ph: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1 |
| ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1 |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: bb.2.vector.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $lr, $r0, $r2 |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, killed $noreg :: (load 8 from %ir.lsr.iv17, align 2) |
| ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.exit: |
| ; CHECK: liveins: $r2 |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| liveins: $r0, $r1, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCBZ $r1, %bb.4 |
| |
| bb.1.vector.ph: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1 |
| |
| renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $r2 |
| $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| |
| bb.2.vector.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg |
| $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.exit: |
| liveins: $r2 |
| |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: illegal_vaddv_s32 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddv_s32 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r12 |
| ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| ; CHECK: bb.1.vector.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.exit: |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $r12 |
| $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| |
| bb.1.vector.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 |
| $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.exit: |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| |
| ... |
| --- |
| name: illegal_vaddva_s32 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddva_s32 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCBZ $r1, %bb.4 |
| ; CHECK: bb.1.vector.ph: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1 |
| ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r2 |
| ; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: bb.2.vector.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.exit: |
| ; CHECK: liveins: $r2 |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| liveins: $r0, $r1, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCBZ $r1, %bb.4 |
| |
| bb.1.vector.ph: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1 |
| |
| renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $r2 |
| $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| |
| bb.2.vector.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg |
| renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.exit: |
| liveins: $r2 |
| |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: illegal_vaddv_u32 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddv_u32 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r12 |
| ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| ; CHECK: bb.1.vector.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.exit: |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r7, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $r12 |
| $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| |
| bb.1.vector.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 |
| $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| early-clobber renamable $r1 = t2STR_POST killed renamable $r12, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.exit: |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| |
| ... |
| --- |
| name: illegal_vaddva_u32 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddva_u32 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCBZ $r1, %bb.4 |
| ; CHECK: bb.1.vector.ph: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1 |
| ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r2 |
| ; CHECK: $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: bb.2.vector.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.exit: |
| ; CHECK: liveins: $r2 |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| liveins: $r0, $r1, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCBZ $r1, %bb.4 |
| |
| bb.1.vector.ph: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1 |
| |
| renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $r2 |
| $r3 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| |
| bb.2.vector.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) |
| $lr = tMOVr $r3, 14 /* CC::al */, $noreg |
| renamable $q0 = MVE_VMVN killed renamable $q0, 0, $noreg, undef renamable $q0 |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg |
| renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg |
| renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.exit: |
| liveins: $r2 |
| |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: illegal_vaddv_s16 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 8 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: |
| - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, |
| isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddv_s16 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate |
| ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| ; CHECK: dead $lr = t2DLS renamable $r12 |
| ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| ; CHECK: bb.1.vector.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 |
| ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 1) |
| ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg |
| ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg |
| ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.exit: |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r4, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r4, -8 |
| tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| t2DoLoopStart renamable $r12 |
| $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| |
| bb.1.vector.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $q0, $r0, $r1, $r2, $r4 |
| |
| renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 1) |
| renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg |
| renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| renamable $r3 = t2SXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg |
| early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.exit: |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc |
| |
| ... |
| --- |
| name: illegal_vaddva_s16 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| - { reg: '$r3', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 8 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: |
| - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, |
| isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddva_s16 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 |
| ; CHECK: tCBZ $r1, %bb.4 |
| ; CHECK: bb.1.vector.ph: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 |
| ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) |
| ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r2 |
| ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: bb.2.vector.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 |
| ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 1) |
| ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg |
| ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.exit: |
| ; CHECK: liveins: $r3 |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| liveins: $r0, $r1, $r2, $r3, $r4, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r4, -8 |
| tCBZ $r1, %bb.4 |
| |
| bb.1.vector.ph: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 |
| renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg |
| renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) |
| renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| t2DoLoopStart renamable $r2 |
| $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| |
| bb.2.vector.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $q0, $r0, $r1, $r3, $r4 |
| |
| renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRBS16_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.lsr.iv17, align 1) |
| renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg |
| renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| renamable $r3 = t2SXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg |
| renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.exit: |
| liveins: $r3 |
| |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: illegal_vaddv_u16 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 8 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: |
| - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, |
| isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddv_u16 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate |
| ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| ; CHECK: dead $lr = t2DLS renamable $r12 |
| ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| ; CHECK: bb.1.vector.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 |
| ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) |
| ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg |
| ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg |
| ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.exit: |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r4, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r4, -8 |
| tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| t2DoLoopStart renamable $r12 |
| $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| |
| bb.1.vector.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $q0, $r0, $r1, $r2, $r4 |
| |
| renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) |
| renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| renamable $r12 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg |
| renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| renamable $r3 = t2UXTH killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg |
| early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.exit: |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc |
| |
| ... |
| --- |
| name: illegal_vaddva_u16 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| - { reg: '$r3', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 8 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: |
| - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, |
| isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddva_u16 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 |
| ; CHECK: tCBZ $r1, %bb.4 |
| ; CHECK: bb.1.vector.ph: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 |
| ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) |
| ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r2 |
| ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: bb.2.vector.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 |
| ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) |
| ; CHECK: renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg |
| ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.exit: |
| ; CHECK: liveins: $r3 |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| liveins: $r0, $r1, $r2, $r3, $r4, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r4, -8 |
| tCBZ $r1, %bb.4 |
| |
| bb.1.vector.ph: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 |
| renamable $r2, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg |
| renamable $r2 = t2BICri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) |
| renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| t2DoLoopStart renamable $r2 |
| $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| |
| bb.2.vector.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $q0, $r0, $r1, $r3, $r4 |
| |
| renamable $vpr = MVE_VCTP16 renamable $r1, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 2) |
| renamable $q1 = MVE_VSUBi16 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| renamable $r2 = MVE_VADDVu16no_acc killed renamable $q1, 0, $noreg |
| renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg |
| renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 8, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.exit: |
| liveins: $r3 |
| |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: illegal_vaddv_s8 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 8 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: |
| - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, |
| isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddv_s8 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate |
| ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| ; CHECK: dead $lr = t2DLS renamable $r12 |
| ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| ; CHECK: bb.1.vector.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 |
| ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) |
| ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg |
| ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg |
| ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.exit: |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r4, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r4, -8 |
| tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| t2DoLoopStart renamable $r12 |
| $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| |
| bb.1.vector.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $q0, $r0, $r1, $r2, $r4 |
| |
| renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) |
| renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg |
| renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| renamable $r3 = t2SXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg |
| early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.exit: |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc |
| |
| ... |
| --- |
| name: illegal_vaddva_s8 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| - { reg: '$r3', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 8 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: |
| - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, |
| isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddva_s8 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 |
| ; CHECK: tCBZ $r1, %bb.4 |
| ; CHECK: bb.1.vector.ph: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 |
| ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) |
| ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r2 |
| ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: bb.2.vector.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 |
| ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) |
| ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg |
| ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.exit: |
| ; CHECK: liveins: $r3 |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| liveins: $r0, $r1, $r2, $r3, $r4, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r4, -8 |
| tCBZ $r1, %bb.4 |
| |
| bb.1.vector.ph: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 |
| renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg |
| renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg |
| renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) |
| renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| t2DoLoopStart renamable $r2 |
| $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| |
| bb.2.vector.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $q0, $r0, $r1, $r3, $r4 |
| |
| renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) |
| renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg |
| renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| renamable $r3 = t2SXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg |
| renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.exit: |
| liveins: $r3 |
| |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: illegal_vaddv_u8 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 8 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: |
| - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default, |
| isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddv_u8 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 |
| ; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 0, 8, implicit-def $itstate |
| ; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate |
| ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| ; CHECK: dead $lr = t2DLS renamable $r12 |
| ; CHECK: $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| ; CHECK: bb.1.vector.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 |
| ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) |
| ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg |
| ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg |
| ; CHECK: early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.exit: |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r4, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r4, -8 |
| tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 0, 8, implicit-def $itstate |
| tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate |
| renamable $r3, dead $cpsr = tADDi3 renamable $r2, 7, 14 /* CC::al */, $noreg |
| renamable $r3 = t2BICri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2SUBri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg |
| renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8) |
| t2DoLoopStart renamable $r12 |
| $r4 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| |
| bb.1.vector.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $q0, $r0, $r1, $r2, $r4 |
| |
| renamable $vpr = MVE_VCTP8 renamable $r2, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) |
| renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| renamable $r12 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg |
| renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| renamable $r3 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg |
| early-clobber renamable $r1 = t2STR_POST killed renamable $r3, killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.store.addr) |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.exit: |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc |
| |
| ... |
| --- |
| name: illegal_vaddva_u8 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| - { reg: '$r3', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 8 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: |
| - { id: 0, type: default, offset: 0, size: 8, alignment: 8, stack-id: default, |
| isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vaddva_u8 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 |
| ; CHECK: tCBZ $r1, %bb.4 |
| ; CHECK: bb.1.vector.ph: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 |
| ; CHECK: renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) |
| ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r2 |
| ; CHECK: $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: bb.2.vector.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $q0, $r0, $r1, $r3, $r4 |
| ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) |
| ; CHECK: renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| ; CHECK: $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg |
| ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.exit: |
| ; CHECK: liveins: $r3 |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.4(0x30000000), %bb.1(0x50000000) |
| liveins: $r0, $r1, $r2, $r3, $r4, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r4, -8 |
| tCBZ $r1, %bb.4 |
| |
| bb.1.vector.ph: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $d0 = VMOVDRR killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, implicit-def $q0 |
| renamable $r2, dead $cpsr = tADDi3 renamable $r1, 7, 14 /* CC::al */, $noreg |
| renamable $r2 = t2BICri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 7, 14 /* CC::al */, $noreg |
| renamable $d1 = VLDRD $sp, 2, 14 /* CC::al */, $noreg, implicit killed $q0, implicit-def $q0 :: (load 8 from %fixed-stack.0) |
| renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 27, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| t2DoLoopStart renamable $r2 |
| $r4 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| |
| bb.2.vector.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $q0, $r0, $r1, $r3, $r4 |
| |
| renamable $vpr = MVE_VCTP8 renamable $r1, 0, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv17, align 1) |
| renamable $q1 = MVE_VEOR killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 |
| $lr = tMOVr $r4, 14 /* CC::al */, $noreg |
| renamable $r2 = MVE_VADDVu8no_acc killed renamable $q1, 0, $noreg |
| renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 /* CC::al */, $noreg |
| renamable $r3 = t2UXTAB killed renamable $r3, killed renamable $r2, 0, 14 /* CC::al */, $noreg |
| renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.exit: |
| liveins: $r3 |
| |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: regalloc_legality_vaddva_u32 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: regalloc_legality_vaddva_u32 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr |
| ; CHECK: bb.1.while.body.preheader: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1, $r2 |
| ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 |
| ; CHECK: bb.2.while.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r12 |
| ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 0, $noreg :: (load 8 from %ir.tmp3, align 2) |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 0, killed $noreg :: (load 8 from %ir.tmp1, align 2) |
| ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg |
| ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.while.end: |
| ; CHECK: liveins: $r12 |
| ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.1(0x50000000), %bb.4(0x30000000) |
| liveins: $r0, $r1, $r2, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| $r3 = tMOVr $r2, 14 /* CC::al */, $noreg |
| t2IT 10, 8, implicit-def $itstate |
| renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate |
| tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| tBcc %bb.4, 11 /* CC::lt */, killed $cpsr |
| |
| bb.1.while.body.preheader: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg |
| renamable $r12 = t2ADDri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $lr |
| |
| bb.2.while.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $lr, $r0, $r1, $r2, $r12 |
| |
| renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg |
| MVE_VPST 4, implicit $vpr |
| renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.tmp3, align 2) |
| renamable $r0, renamable $q1 = MVE_VLDRHU32_post killed renamable $r0, 8, 1, killed renamable $vpr :: (load 8 from %ir.tmp1, align 2) |
| renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg |
| renamable $r12 = MVE_VADDVu32acc killed renamable $r12, killed renamable $q0, 0, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.while.end: |
| liveins: $r12 |
| |
| $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg |
| $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: regalloc_legality_vaddv_u16 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: regalloc_legality_vaddv_u16 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr |
| ; CHECK: bb.1.while.body.preheader: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1, $r2 |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $lr = MVE_DLSTP_16 killed renamable $r2 |
| ; CHECK: bb.2.while.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r3 |
| ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.tmp3, align 2) |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, killed $noreg :: (load 16 from %ir.tmp1, align 2) |
| ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg |
| ; CHECK: renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.while.end: |
| ; CHECK: liveins: $r3 |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.1(0x50000000), %bb.4(0x30000000) |
| liveins: $r0, $r1, $r2, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCMPi8 renamable $r2, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| $r3 = tMOVr $r2, 14 /* CC::al */, $noreg |
| t2IT 10, 8, implicit-def $itstate |
| renamable $r3 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate |
| tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| tBcc %bb.4, 11 /* CC::lt */, killed $cpsr |
| |
| bb.1.while.body.preheader: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $r3, dead $cpsr = tSUBrr renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg |
| renamable $r12 = t2ADDri killed renamable $r3, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| t2DoLoopStart renamable $lr |
| |
| bb.2.while.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $lr, $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg |
| MVE_VPST 4, implicit $vpr |
| renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) |
| renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) |
| renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| renamable $r2, dead $cpsr = nsw tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg |
| renamable $r12 = MVE_VADDVu16no_acc killed renamable $q0, 0, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| renamable $r3 = t2UXTAH killed renamable $r3, killed renamable $r12, 0, 14 /* CC::al */, $noreg |
| t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.while.end: |
| liveins: $r3 |
| |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r3, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: regalloc_illegality_vaddva_s32 |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r3', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: regalloc_illegality_vaddva_s32 |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r3, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg |
| ; CHECK: t2IT 10, 8, implicit-def $itstate |
| ; CHECK: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate |
| ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr |
| ; CHECK: bb.1.while.body.preheader: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $lr = t2DLS killed renamable $lr |
| ; CHECK: bb.2.while.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg |
| ; CHECK: MVE_VPST 4, implicit $vpr |
| ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) |
| ; CHECK: renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, undef renamable $q2 |
| ; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, undef renamable $q0 |
| ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.while.end: |
| ; CHECK: liveins: $r2 |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.1(0x50000000), %bb.4(0x30000000) |
| liveins: $r0, $r1, $r3, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| $r2 = tMOVr $r3, 14 /* CC::al */, $noreg |
| t2IT 10, 8, implicit-def $itstate |
| renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate |
| tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| tBcc %bb.4, 11 /* CC::lt */, killed $cpsr |
| |
| bb.1.while.body.preheader: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg |
| renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| t2DoLoopStart renamable $lr |
| |
| bb.2.while.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $lr, $r0, $r1, $r2, $r3 |
| |
| renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg |
| MVE_VPST 4, implicit $vpr |
| renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) |
| renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) |
| renamable $q2 = MVE_VMULLBs16 renamable $q1, renamable $q0, 0, $noreg, undef renamable $q2 |
| renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| renamable $q0 = MVE_VADDi32 killed renamable $q0, killed renamable $q2, 0, $noreg, undef renamable $q0 |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg |
| renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.while.end: |
| liveins: $r2 |
| |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| ... |
| --- |
| name: illegal_vmull_non_zero |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r3', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: illegal_vmull_non_zero |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r3, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: $r2 = tMOVr $r3, 14 /* CC::al */, $noreg |
| ; CHECK: t2IT 10, 8, implicit-def $itstate |
| ; CHECK: renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate |
| ; CHECK: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: tBcc %bb.4, 11 /* CC::lt */, killed $cpsr |
| ; CHECK: bb.1.while.body.preheader: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3 |
| ; CHECK: renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: dead $lr = t2DLS renamable $r2 |
| ; CHECK: $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: bb.2.while.body: |
| ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 |
| ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg |
| ; CHECK: MVE_VPST 4, implicit $vpr |
| ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) |
| ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) |
| ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 |
| ; CHECK: bb.3.while.end: |
| ; CHECK: liveins: $r2 |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| ; CHECK: bb.4: |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| ; CHECK: $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| bb.0.entry: |
| successors: %bb.1(0x50000000), %bb.4(0x30000000) |
| liveins: $r0, $r1, $r3, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| $r2 = tMOVr $r3, 14 /* CC::al */, $noreg |
| t2IT 10, 8, implicit-def $itstate |
| renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate |
| tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| tBcc %bb.4, 11 /* CC::lt */, killed $cpsr |
| |
| bb.1.while.body.preheader: |
| successors: %bb.2(0x80000000) |
| liveins: $r0, $r1, $r2, $r3 |
| |
| renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg |
| renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg |
| renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg |
| t2DoLoopStart renamable $r2 |
| $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| |
| bb.2.while.body: |
| successors: %bb.2(0x7c000000), %bb.3(0x04000000) |
| liveins: $r0, $r1, $r2, $r3, $r12 |
| |
| renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg |
| MVE_VPST 4, implicit $vpr |
| renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2) |
| renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2) |
| $lr = tMOVr $r12, 14 /* CC::al */, $noreg |
| renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg |
| renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg |
| renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr |
| tB %bb.3, 14 /* CC::al */, $noreg |
| |
| bb.3.while.end: |
| liveins: $r2 |
| |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| bb.4: |
| renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg |
| $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg |
| frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0 |
| |
| ... |
