# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
#
--- |
  @mask = external global i16
  define dso_local void @test(i32* noalias nocapture %arg, i32* noalias nocapture readonly %arg1, i32 %arg2, i32* noalias nocapture readonly %arg3) local_unnamed_addr #0 {
  bb:
    %tmp = icmp eq i32 %arg2, 0
    %tmp1 = add i32 %arg2, 3
    %tmp2 = lshr i32 %tmp1, 2
    %tmp3 = shl nuw i32 %tmp2, 2
    %tmp4 = add i32 %tmp3, -4
    %tmp5 = lshr i32 %tmp4, 2
    %tmp6 = add nuw nsw i32 %tmp5, 1
    %mask.gep9 = bitcast i16* @mask to i16*
    %mask.load = load i16, i16* %mask.gep9
    %conv.mask = zext i16 %mask.load to i32
    %invariant.mask = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %conv.mask)
    br i1 %tmp, label %bb27, label %bb3

  bb3:                                              ; preds = %bb
    call void @llvm.set.loop.iterations.i32(i32 %tmp6)
    %scevgep1 = getelementptr i32, i32* %arg3, i32 -4
    br label %bb9

  bb9:                                              ; preds = %bb9, %bb3
    %lsr.iv4 = phi i32* [ %scevgep6, %bb9 ], [ %scevgep1, %bb3 ]
    %lsr.iv2 = phi i32* [ %scevgep3, %bb9 ], [ %arg1, %bb3 ]
    %lsr.iv = phi i32* [ %scevgep, %bb9 ], [ %arg, %bb3 ]
    %tmp7 = phi i32 [ %tmp6, %bb3 ], [ %tmp12, %bb9 ]
    %tmp8 = phi i32 [ %arg2, %bb3 ], [ %tmp11, %bb9 ]
    %lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>*
    %lsr.iv24 = bitcast i32* %lsr.iv2 to <4 x i32>*
    %lsr.iv47 = bitcast i32* %lsr.iv4 to <4 x i32>*
    %vctp = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp8)
    %and = and <4 x i1> %vctp, %invariant.mask
    %tmp11 = sub i32 %tmp8, 4
    %tmp17 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv24, i32 4, <4 x i1> %and, <4 x i32> undef)
    %tmp22 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1, i32 4, <4 x i1> %and, <4 x i32> undef)
    %tmp23 = mul nsw <4 x i32> %tmp22, %tmp17
    %scevgep2 = getelementptr <4 x i32>, <4 x i32>* %lsr.iv47, i32 1
    %load.limits = load <4 x i32>, <4 x i32>* %scevgep2
    %0 = insertelement <4 x i32> undef, i32 %conv.mask, i32 0
    %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> zeroinitializer
    %bad.icmp = icmp ule <4 x i32> %load.limits, %1
    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %tmp23, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %bad.icmp)
    %tmp12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %tmp7, i32 1)
    %tmp13 = icmp ne i32 %tmp12, 0
    %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
    %scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 4
    %scevgep6 = getelementptr i32, i32* %lsr.iv4, i32 4
    br i1 %tmp13, label %bb9, label %bb27

  bb27:                                             ; preds = %bb9, %bb
    ret void
  }
  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
  declare void @llvm.set.loop.iterations.i32(i32)
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
  declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)

...
---
name:            test
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       20
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 3, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 4, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: test
  ; CHECK: bb.0.bb:
  ; CHECK:   successors: %bb.3(0x30000000), %bb.1(0x50000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 16
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r5, -12
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -16
  ; CHECK:   $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 20
  ; CHECK:   tCBZ $r2, %bb.3
  ; CHECK: bb.1.bb3:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3
  ; CHECK:   $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
  ; CHECK:   $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4 = t2BICri killed renamable $r4, 3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 /* CC::al */, $noreg :: (dereferenceable load 2 from %ir.mask.gep9)
  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r4, 4, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r4, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   $vpr = VMSR_P0 $r5, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 16, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.0)
  ; CHECK:   renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0
  ; CHECK:   $r3 = tMOVr $r0, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = t2DLS killed renamable $lr
  ; CHECK: bb.2.bb9:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12
  ; CHECK:   renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.0)
  ; CHECK:   MVE_VPST 2, implicit $vpr
  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
  ; CHECK:   renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
  ; CHECK:   renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
  ; CHECK:   renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8)
  ; CHECK:   MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
  ; CHECK:   MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
  ; CHECK:   $r0 = tMOVr $r3, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
  ; CHECK: bb.3.bb27:
  ; CHECK:   $sp = tADDspi $sp, 1, 14 /* CC::al */, $noreg
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r7, def $pc
  bb.0.bb:
    successors: %bb.3(0x30000000), %bb.1(0x50000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr

    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 16
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    frame-setup CFI_INSTRUCTION offset $r5, -12
    frame-setup CFI_INSTRUCTION offset $r4, -16
    $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
    frame-setup CFI_INSTRUCTION def_cfa_offset 20
    tCBZ $r2, %bb.3

  bb.1.bb3:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r3

    $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg
    renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
    $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg
    renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg
    renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9)
    renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg
    renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
    $vpr = VMSR_P0 $r5, 14, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg
    VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0)
    renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0
    $r3 = tMOVr $r0, 14, $noreg
    t2DoLoopStart renamable $lr

  bb.2.bb9:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12

    renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0)
    MVE_VPST 2, implicit $vpr
    renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr
    renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4)
    renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4)
    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1
    renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8)
    MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr
    MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    $r0 = tMOVr $r3, 14, $noreg
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14, $noreg

  bb.3.bb27:
    $sp = tADDspi $sp, 1, 14, $noreg
    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc

...