; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:     -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN:     -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE

define i32 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt:
; CHECK-P8:       # %bb.0: # %entry
; CHECK-P8-NEXT:    mtfprd f0, r3
; CHECK-P8-NEXT:    xxswapd v2, vs0
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT:    xscvspdpn f1, vs1
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    mtvsrd v3, r4
; CHECK-P8-NEXT:    mffprwz r3, f1
; CHECK-P8-NEXT:    mtvsrd v2, r3
; CHECK-P8-NEXT:    vmrghh v2, v3, v2
; CHECK-P8-NEXT:    xxswapd vs0, v2
; CHECK-P8-NEXT:    mffprwz r3, f0
; CHECK-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test2elt:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    mtfprd f0, r3
; CHECK-P9-NEXT:    xxswapd v2, vs0
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    mtvsrd v2, r3
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    li r3, 0
; CHECK-P9-NEXT:    vmrghh v2, v3, v2
; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-LABEL: test2elt:
; CHECK-BE:       # %bb.0: # %entry
; CHECK-BE-NEXT:    mtfprd f0, r3
; CHECK-BE-NEXT:    xscvspdpn f1, vs0
; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v2, r3
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    li r3, 0
; CHECK-BE-NEXT:    vmrghh v2, v2, v3
; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
; CHECK-BE-NEXT:    blr
entry:
  %0 = bitcast i64 %a.coerce to <2 x float>
  %1 = fptoui <2 x float> %0 to <2 x i16>
  %2 = bitcast <2 x i16> %1 to i32
  ret i32 %2
}

define i64 @test4elt(<4 x float> %a) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt:
; CHECK-P8:       # %bb.0: # %entry
; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
; CHECK-P8-NEXT:    xscvspdpn f1, v2
; CHECK-P8-NEXT:    xxswapd vs2, v2
; CHECK-P8-NEXT:    xxsldwi vs3, v2, v2, 1
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xscvspdpn f2, vs2
; CHECK-P8-NEXT:    xscvspdpn f3, vs3
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    xscvdpsxws f2, f2
; CHECK-P8-NEXT:    xscvdpsxws f3, f3
; CHECK-P8-NEXT:    mffprwz r3, f1
; CHECK-P8-NEXT:    mtvsrd v2, r3
; CHECK-P8-NEXT:    mffprwz r3, f0
; CHECK-P8-NEXT:    mffprwz r4, f2
; CHECK-P8-NEXT:    mtvsrd v3, r3
; CHECK-P8-NEXT:    mffprwz r3, f3
; CHECK-P8-NEXT:    mtvsrd v4, r4
; CHECK-P8-NEXT:    mtvsrd v5, r3
; CHECK-P8-NEXT:    vmrghh v3, v4, v3
; CHECK-P8-NEXT:    vmrghh v2, v2, v5
; CHECK-P8-NEXT:    vmrglw v2, v2, v3
; CHECK-P8-NEXT:    xxswapd vs0, v2
; CHECK-P8-NEXT:    mffprd r3, f0
; CHECK-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test4elt:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    xxswapd vs0, v2
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    xscvspdpn f0, v2
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    vmrghh v3, v4, v3
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    mtvsrd v2, r3
; CHECK-P9-NEXT:    vmrghh v2, v4, v2
; CHECK-P9-NEXT:    vmrglw v2, v2, v3
; CHECK-P9-NEXT:    mfvsrld r3, v2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-LABEL: test4elt:
; CHECK-BE:       # %bb.0: # %entry
; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    xxswapd vs0, v2
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    xscvspdpn f0, v2
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    vmrghh v3, v4, v3
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v2, r3
; CHECK-BE-NEXT:    vmrghh v2, v4, v2
; CHECK-BE-NEXT:    vmrghw v2, v2, v3
; CHECK-BE-NEXT:    mfvsrd r3, v2
; CHECK-BE-NEXT:    blr
entry:
  %0 = fptoui <4 x float> %a to <4 x i16>
  %1 = bitcast <4 x i16> %0 to i64
  ret i64 %1
}

define <8 x i16> @test8elt(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt:
; CHECK-P8:       # %bb.0: # %entry
; CHECK-P8-NEXT:    lvx v2, 0, r3
; CHECK-P8-NEXT:    li r4, 16
; CHECK-P8-NEXT:    lvx v3, r3, r4
; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
; CHECK-P8-NEXT:    xxswapd vs1, v2
; CHECK-P8-NEXT:    xscvspdpn f2, v2
; CHECK-P8-NEXT:    xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT:    xxsldwi vs5, v3, v3, 3
; CHECK-P8-NEXT:    xscvspdpn f3, v3
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xscvspdpn f1, vs1
; CHECK-P8-NEXT:    xscvspdpn f4, vs4
; CHECK-P8-NEXT:    xscvspdpn f5, vs5
; CHECK-P8-NEXT:    xscvdpsxws f2, f2
; CHECK-P8-NEXT:    xscvdpsxws f3, f3
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mffprwz r3, f0
; CHECK-P8-NEXT:    xxswapd vs0, v3
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xxsldwi vs1, v3, v3, 1
; CHECK-P8-NEXT:    mtvsrd v2, r3
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    mffprwz r3, f2
; CHECK-P8-NEXT:    xscvdpsxws f2, f4
; CHECK-P8-NEXT:    xscvspdpn f1, vs1
; CHECK-P8-NEXT:    xscvdpsxws f4, f5
; CHECK-P8-NEXT:    mtvsrd v4, r4
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    vmrghh v2, v4, v2
; CHECK-P8-NEXT:    mffprwz r4, f2
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mtvsrd v3, r3
; CHECK-P8-NEXT:    mffprwz r3, f3
; CHECK-P8-NEXT:    mtvsrd v4, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    vmrghh v3, v3, v4
; CHECK-P8-NEXT:    mtvsrd v4, r3
; CHECK-P8-NEXT:    mffprwz r3, f4
; CHECK-P8-NEXT:    mtvsrd v0, r4
; CHECK-P8-NEXT:    mtvsrd v5, r3
; CHECK-P8-NEXT:    mffprwz r3, f1
; CHECK-P8-NEXT:    vmrghh v5, v0, v5
; CHECK-P8-NEXT:    mtvsrd v1, r3
; CHECK-P8-NEXT:    vmrglw v2, v3, v2
; CHECK-P8-NEXT:    vmrghh v4, v4, v1
; CHECK-P8-NEXT:    vmrglw v3, v4, v5
; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
; CHECK-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test8elt:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    lxv vs1, 0(r3)
; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT:    xscvspdpn f2, vs2
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    lxv vs0, 16(r3)
; CHECK-P9-NEXT:    mffprwz r3, f2
; CHECK-P9-NEXT:    xxswapd vs2, vs1
; CHECK-P9-NEXT:    mtvsrd v2, r3
; CHECK-P9-NEXT:    xscvspdpn f2, vs2
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    mffprwz r3, f2
; CHECK-P9-NEXT:    xscvspdpn f2, vs1
; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    vmrghh v2, v3, v2
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    mffprwz r3, f2
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    vmrghh v3, v3, v4
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    vmrglw v2, v3, v2
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    xxswapd vs1, vs0
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    xscvspdpn f1, vs0
; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    vmrghh v3, v4, v3
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    mtvsrd v5, r3
; CHECK-P9-NEXT:    vmrghh v4, v4, v5
; CHECK-P9-NEXT:    vmrglw v3, v4, v3
; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-LABEL: test8elt:
; CHECK-BE:       # %bb.0: # %entry
; CHECK-BE-NEXT:    lxv vs1, 16(r3)
; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    lxv vs0, 0(r3)
; CHECK-BE-NEXT:    mffprwz r3, f2
; CHECK-BE-NEXT:    xxswapd vs2, vs1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    mtvsrd v2, r3
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    mffprwz r3, f2
; CHECK-BE-NEXT:    xscvspdpn f2, vs1
; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    vmrghh v2, v3, v2
; CHECK-BE-NEXT:    mffprwz r3, f2
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    xxswapd vs1, vs0
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    vmrghh v3, v3, v4
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    vmrghw v2, v3, v2
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    xscvspdpn f1, vs0
; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    vmrghh v3, v4, v3
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v5, r3
; CHECK-BE-NEXT:    vmrghh v4, v4, v5
; CHECK-BE-NEXT:    vmrghw v3, v4, v3
; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
; CHECK-BE-NEXT:    blr
entry:
  %a = load <8 x float>, <8 x float>* %0, align 32
  %1 = fptoui <8 x float> %a to <8 x i16>
  ret <8 x i16> %1
}

define void @test16elt(<16 x i16>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt:
; CHECK-P8:       # %bb.0: # %entry
; CHECK-P8-NEXT:    lvx v5, 0, r4
; CHECK-P8-NEXT:    li r5, 16
; CHECK-P8-NEXT:    li r6, 32
; CHECK-P8-NEXT:    lvx v3, r4, r5
; CHECK-P8-NEXT:    lvx v2, r4, r6
; CHECK-P8-NEXT:    li r6, 48
; CHECK-P8-NEXT:    xxsldwi vs0, v5, v5, 3
; CHECK-P8-NEXT:    xscvspdpn f1, v5
; CHECK-P8-NEXT:    lvx v4, r4, r6
; CHECK-P8-NEXT:    xxswapd vs3, v5
; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
; CHECK-P8-NEXT:    xxsldwi vs7, v3, v3, 3
; CHECK-P8-NEXT:    xxswapd vs8, v3
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xscvspdpn f3, vs3
; CHECK-P8-NEXT:    xscvspdpn f5, vs5
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    xscvspdpn f7, vs7
; CHECK-P8-NEXT:    xscvspdpn f8, vs8
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    xscvdpsxws f3, f3
; CHECK-P8-NEXT:    xscvspdpn f2, v3
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xscvdpsxws f1, f5
; CHECK-P8-NEXT:    mtvsrd v5, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    xxsldwi vs0, v3, v3, 1
; CHECK-P8-NEXT:    xscvspdpn f4, v2
; CHECK-P8-NEXT:    xscvdpsxws f5, f7
; CHECK-P8-NEXT:    xxsldwi vs7, v4, v4, 3
; CHECK-P8-NEXT:    mtvsrd v3, r4
; CHECK-P8-NEXT:    mffprwz r4, f3
; CHECK-P8-NEXT:    xxsldwi vs3, v2, v2, 3
; CHECK-P8-NEXT:    xscvspdpn f6, v4
; CHECK-P8-NEXT:    mtvsrd v0, r4
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xscvdpsxws f1, f8
; CHECK-P8-NEXT:    xxswapd vs8, v4
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xscvdpsxws f2, f2
; CHECK-P8-NEXT:    mtvsrd v1, r4
; CHECK-P8-NEXT:    mffprwz r4, f5
; CHECK-P8-NEXT:    xxswapd vs5, v2
; CHECK-P8-NEXT:    xscvspdpn f3, vs3
; CHECK-P8-NEXT:    xscvdpsxws f4, f4
; CHECK-P8-NEXT:    vmrghh v3, v0, v3
; CHECK-P8-NEXT:    mtvsrd v0, r4
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xscvdpsxws f6, f6
; CHECK-P8-NEXT:    xscvspdpn f1, vs5
; CHECK-P8-NEXT:    xxsldwi vs5, v2, v2, 1
; CHECK-P8-NEXT:    mtvsrd v6, r4
; CHECK-P8-NEXT:    mffprwz r4, f2
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    vmrghh v2, v5, v1
; CHECK-P8-NEXT:    vmrghh v5, v6, v0
; CHECK-P8-NEXT:    mtvsrd v0, r4
; CHECK-P8-NEXT:    mffprwz r4, f4
; CHECK-P8-NEXT:    xscvdpsxws f2, f3
; CHECK-P8-NEXT:    xscvspdpn f5, vs5
; CHECK-P8-NEXT:    mtvsrd v1, r4
; CHECK-P8-NEXT:    mffprwz r4, f6
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mtvsrd v6, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    xscvspdpn f7, vs7
; CHECK-P8-NEXT:    mtvsrd v7, r4
; CHECK-P8-NEXT:    mffprwz r4, f2
; CHECK-P8-NEXT:    xxsldwi vs2, v4, v4, 1
; CHECK-P8-NEXT:    xscvspdpn f8, vs8
; CHECK-P8-NEXT:    xscvdpsxws f0, f5
; CHECK-P8-NEXT:    mtvsrd v4, r4
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xscvspdpn f1, vs2
; CHECK-P8-NEXT:    xscvdpsxws f3, f7
; CHECK-P8-NEXT:    mtvsrd v8, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    xscvdpsxws f0, f8
; CHECK-P8-NEXT:    mtvsrd v9, r4
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mffprwz r4, f3
; CHECK-P8-NEXT:    vmrghh v0, v0, v7
; CHECK-P8-NEXT:    mtvsrd v7, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    vmrghh v4, v8, v4
; CHECK-P8-NEXT:    mtvsrd v8, r4
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    vmrghh v1, v1, v9
; CHECK-P8-NEXT:    mtvsrd v9, r4
; CHECK-P8-NEXT:    vmrghh v7, v8, v7
; CHECK-P8-NEXT:    vmrghh v6, v6, v9
; CHECK-P8-NEXT:    vmrglw v2, v2, v3
; CHECK-P8-NEXT:    vmrglw v3, v0, v5
; CHECK-P8-NEXT:    vmrglw v4, v1, v4
; CHECK-P8-NEXT:    vmrglw v5, v6, v7
; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
; CHECK-P8-NEXT:    stvx v2, 0, r3
; CHECK-P8-NEXT:    xxmrgld v3, v5, v4
; CHECK-P8-NEXT:    stvx v3, r3, r5
; CHECK-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test16elt:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    lxv vs2, 0(r4)
; CHECK-P9-NEXT:    xxsldwi vs3, vs2, vs2, 3
; CHECK-P9-NEXT:    xxswapd vs4, vs2
; CHECK-P9-NEXT:    xscvspdpn f3, vs3
; CHECK-P9-NEXT:    xscvspdpn f4, vs4
; CHECK-P9-NEXT:    xscvdpsxws f3, f3
; CHECK-P9-NEXT:    xscvdpsxws f4, f4
; CHECK-P9-NEXT:    xscvspdpn f5, vs2
; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT:    xscvspdpn f2, vs2
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    mffprwz r5, f3
; CHECK-P9-NEXT:    lxv vs1, 16(r4)
; CHECK-P9-NEXT:    xxsldwi vs6, vs1, vs1, 3
; CHECK-P9-NEXT:    xxswapd vs3, vs1
; CHECK-P9-NEXT:    mtvsrd v2, r5
; CHECK-P9-NEXT:    mffprwz r5, f4
; CHECK-P9-NEXT:    xscvdpsxws f4, f5
; CHECK-P9-NEXT:    xscvspdpn f3, vs3
; CHECK-P9-NEXT:    mtvsrd v3, r5
; CHECK-P9-NEXT:    vmrghh v2, v3, v2
; CHECK-P9-NEXT:    mffprwz r5, f4
; CHECK-P9-NEXT:    xscvspdpn f4, vs6
; CHECK-P9-NEXT:    mtvsrd v3, r5
; CHECK-P9-NEXT:    mffprwz r5, f2
; CHECK-P9-NEXT:    xscvspdpn f2, vs1
; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT:    xscvdpsxws f4, f4
; CHECK-P9-NEXT:    xscvdpsxws f3, f3
; CHECK-P9-NEXT:    lxv vs0, 32(r4)
; CHECK-P9-NEXT:    mtvsrd v4, r5
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    vmrghh v3, v3, v4
; CHECK-P9-NEXT:    vmrglw v2, v3, v2
; CHECK-P9-NEXT:    mffprwz r5, f4
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    mtvsrd v4, r5
; CHECK-P9-NEXT:    mffprwz r5, f3
; CHECK-P9-NEXT:    xxsldwi vs3, vs0, vs0, 3
; CHECK-P9-NEXT:    mtvsrd v5, r5
; CHECK-P9-NEXT:    mffprwz r5, f2
; CHECK-P9-NEXT:    xscvspdpn f2, vs3
; CHECK-P9-NEXT:    vmrghh v4, v5, v4
; CHECK-P9-NEXT:    mtvsrd v5, r5
; CHECK-P9-NEXT:    mffprwz r5, f1
; CHECK-P9-NEXT:    xxswapd vs1, vs0
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    mtvsrd v0, r5
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    vmrghh v5, v5, v0
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    vmrglw v3, v5, v4
; CHECK-P9-NEXT:    mffprwz r5, f2
; CHECK-P9-NEXT:    xscvspdpn f2, vs0
; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT:    mtvsrd v0, r5
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    mffprwz r5, f1
; CHECK-P9-NEXT:    lxv vs1, 48(r4)
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mtvsrd v1, r5
; CHECK-P9-NEXT:    vmrghh v0, v1, v0
; CHECK-P9-NEXT:    mffprwz r4, f2
; CHECK-P9-NEXT:    xxmrgld vs2, v3, v2
; CHECK-P9-NEXT:    mtvsrd v4, r4
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT:    mtvsrd v2, r4
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    vmrghh v2, v4, v2
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    vmrglw v2, v2, v0
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    xxswapd vs0, vs1
; CHECK-P9-NEXT:    mtvsrd v3, r4
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    xscvspdpn f0, vs1
; CHECK-P9-NEXT:    mtvsrd v4, r4
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    vmrghh v3, v4, v3
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 1
; CHECK-P9-NEXT:    mtvsrd v4, r4
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    mtvsrd v5, r4
; CHECK-P9-NEXT:    vmrghh v4, v4, v5
; CHECK-P9-NEXT:    vmrglw v3, v4, v3
; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
; CHECK-P9-NEXT:    stxv vs0, 16(r3)
; CHECK-P9-NEXT:    stxv vs2, 0(r3)
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-LABEL: test16elt:
; CHECK-BE:       # %bb.0: # %entry
; CHECK-BE-NEXT:    lxv vs1, 16(r4)
; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    xxswapd vs3, vs1
; CHECK-BE-NEXT:    xscvspdpn f3, vs3
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    xscvdpsxws f3, f3
; CHECK-BE-NEXT:    mffprwz r5, f2
; CHECK-BE-NEXT:    xscvspdpn f4, vs1
; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    mtvsrd v2, r5
; CHECK-BE-NEXT:    mffprwz r5, f3
; CHECK-BE-NEXT:    xscvdpsxws f3, f4
; CHECK-BE-NEXT:    lxv vs0, 0(r4)
; CHECK-BE-NEXT:    xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    mtvsrd v3, r5
; CHECK-BE-NEXT:    vmrghh v2, v3, v2
; CHECK-BE-NEXT:    mffprwz r5, f3
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    mtvsrd v3, r5
; CHECK-BE-NEXT:    mffprwz r5, f1
; CHECK-BE-NEXT:    xxswapd vs1, vs0
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    mtvsrd v4, r5
; CHECK-BE-NEXT:    mffprwz r5, f2
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    vmrghh v3, v3, v4
; CHECK-BE-NEXT:    mtvsrd v4, r5
; CHECK-BE-NEXT:    vmrghw v2, v3, v2
; CHECK-BE-NEXT:    mffprwz r5, f1
; CHECK-BE-NEXT:    xscvspdpn f1, vs0
; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v5, r5
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    vmrghh v4, v5, v4
; CHECK-BE-NEXT:    mffprwz r5, f1
; CHECK-BE-NEXT:    lxv vs1, 48(r4)
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    mtvsrd v5, r5
; CHECK-BE-NEXT:    mffprwz r5, f0
; CHECK-BE-NEXT:    lxv vs0, 32(r4)
; CHECK-BE-NEXT:    xscvspdpn f5, vs1
; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    xscvdpsxws f5, f5
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    xxswapd vs3, vs1
; CHECK-BE-NEXT:    mtvsrd v0, r5
; CHECK-BE-NEXT:    vmrghh v5, v5, v0
; CHECK-BE-NEXT:    xscvspdpn f3, vs3
; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    vmrghw v3, v5, v4
; CHECK-BE-NEXT:    xscvdpsxws f3, f3
; CHECK-BE-NEXT:    mffprwz r4, f5
; CHECK-BE-NEXT:    xxmrghd vs4, v3, v2
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v2, r4
; CHECK-BE-NEXT:    mffprwz r4, f2
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    stxv vs4, 0(r3)
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v3, r4
; CHECK-BE-NEXT:    mffprwz r4, f3
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v4, r4
; CHECK-BE-NEXT:    mffprwz r4, f1
; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    vmrghh v3, v4, v3
; CHECK-BE-NEXT:    mtvsrd v4, r4
; CHECK-BE-NEXT:    mffprwz r4, f1
; CHECK-BE-NEXT:    xxswapd vs1, vs0
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    vmrghh v2, v2, v4
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    vmrghw v2, v2, v3
; CHECK-BE-NEXT:    mtvsrd v3, r4
; CHECK-BE-NEXT:    mffprwz r4, f1
; CHECK-BE-NEXT:    xscvspdpn f1, vs0
; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v4, r4
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    vmrghh v3, v4, v3
; CHECK-BE-NEXT:    mffprwz r4, f1
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v4, r4
; CHECK-BE-NEXT:    mffprwz r4, f0
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v5, r4
; CHECK-BE-NEXT:    vmrghh v4, v4, v5
; CHECK-BE-NEXT:    vmrghw v3, v4, v3
; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
; CHECK-BE-NEXT:    stxv vs0, 16(r3)
; CHECK-BE-NEXT:    blr
entry:
  %a = load <16 x float>, <16 x float>* %0, align 64
  %1 = fptoui <16 x float> %a to <16 x i16>
  store <16 x i16> %1, <16 x i16>* %agg.result, align 32
  ret void
}

define i32 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8:       # %bb.0: # %entry
; CHECK-P8-NEXT:    mtfprd f0, r3
; CHECK-P8-NEXT:    xxswapd v2, vs0
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT:    xscvspdpn f1, vs1
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    mtvsrd v3, r4
; CHECK-P8-NEXT:    mffprwz r3, f1
; CHECK-P8-NEXT:    mtvsrd v2, r3
; CHECK-P8-NEXT:    vmrghh v2, v3, v2
; CHECK-P8-NEXT:    xxswapd vs0, v2
; CHECK-P8-NEXT:    mffprwz r3, f0
; CHECK-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    mtfprd f0, r3
; CHECK-P9-NEXT:    xxswapd v2, vs0
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    mtvsrd v2, r3
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    li r3, 0
; CHECK-P9-NEXT:    vmrghh v2, v3, v2
; CHECK-P9-NEXT:    vextuwrx r3, r3, v2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE:       # %bb.0: # %entry
; CHECK-BE-NEXT:    mtfprd f0, r3
; CHECK-BE-NEXT:    xscvspdpn f1, vs0
; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v2, r3
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    li r3, 0
; CHECK-BE-NEXT:    vmrghh v2, v2, v3
; CHECK-BE-NEXT:    vextuwlx r3, r3, v2
; CHECK-BE-NEXT:    blr
entry:
  %0 = bitcast i64 %a.coerce to <2 x float>
  %1 = fptosi <2 x float> %0 to <2 x i16>
  %2 = bitcast <2 x i16> %1 to i32
  ret i32 %2
}

define i64 @test4elt_signed(<4 x float> %a) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8:       # %bb.0: # %entry
; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
; CHECK-P8-NEXT:    xscvspdpn f1, v2
; CHECK-P8-NEXT:    xxswapd vs2, v2
; CHECK-P8-NEXT:    xxsldwi vs3, v2, v2, 1
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xscvspdpn f2, vs2
; CHECK-P8-NEXT:    xscvspdpn f3, vs3
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    xscvdpsxws f2, f2
; CHECK-P8-NEXT:    xscvdpsxws f3, f3
; CHECK-P8-NEXT:    mffprwz r3, f1
; CHECK-P8-NEXT:    mtvsrd v2, r3
; CHECK-P8-NEXT:    mffprwz r3, f0
; CHECK-P8-NEXT:    mffprwz r4, f2
; CHECK-P8-NEXT:    mtvsrd v3, r3
; CHECK-P8-NEXT:    mffprwz r3, f3
; CHECK-P8-NEXT:    mtvsrd v4, r4
; CHECK-P8-NEXT:    mtvsrd v5, r3
; CHECK-P8-NEXT:    vmrghh v3, v4, v3
; CHECK-P8-NEXT:    vmrghh v2, v2, v5
; CHECK-P8-NEXT:    vmrglw v2, v2, v3
; CHECK-P8-NEXT:    xxswapd vs0, v2
; CHECK-P8-NEXT:    mffprd r3, f0
; CHECK-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    xxswapd vs0, v2
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    xscvspdpn f0, v2
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    vmrghh v3, v4, v3
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    mtvsrd v2, r3
; CHECK-P9-NEXT:    vmrghh v2, v4, v2
; CHECK-P9-NEXT:    vmrglw v2, v2, v3
; CHECK-P9-NEXT:    mfvsrld r3, v2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE:       # %bb.0: # %entry
; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    xxswapd vs0, v2
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    xscvspdpn f0, v2
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    vmrghh v3, v4, v3
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v2, r3
; CHECK-BE-NEXT:    vmrghh v2, v4, v2
; CHECK-BE-NEXT:    vmrghw v2, v2, v3
; CHECK-BE-NEXT:    mfvsrd r3, v2
; CHECK-BE-NEXT:    blr
entry:
  %0 = fptosi <4 x float> %a to <4 x i16>
  %1 = bitcast <4 x i16> %0 to i64
  ret i64 %1
}

define <8 x i16> @test8elt_signed(<8 x float>* nocapture readonly) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8:       # %bb.0: # %entry
; CHECK-P8-NEXT:    lvx v2, 0, r3
; CHECK-P8-NEXT:    li r4, 16
; CHECK-P8-NEXT:    lvx v3, r3, r4
; CHECK-P8-NEXT:    xxsldwi vs0, v2, v2, 3
; CHECK-P8-NEXT:    xxswapd vs1, v2
; CHECK-P8-NEXT:    xscvspdpn f2, v2
; CHECK-P8-NEXT:    xxsldwi vs4, v2, v2, 1
; CHECK-P8-NEXT:    xxsldwi vs5, v3, v3, 3
; CHECK-P8-NEXT:    xscvspdpn f3, v3
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xscvspdpn f1, vs1
; CHECK-P8-NEXT:    xscvspdpn f4, vs4
; CHECK-P8-NEXT:    xscvspdpn f5, vs5
; CHECK-P8-NEXT:    xscvdpsxws f2, f2
; CHECK-P8-NEXT:    xscvdpsxws f3, f3
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mffprwz r3, f0
; CHECK-P8-NEXT:    xxswapd vs0, v3
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xxsldwi vs1, v3, v3, 1
; CHECK-P8-NEXT:    mtvsrd v2, r3
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    mffprwz r3, f2
; CHECK-P8-NEXT:    xscvdpsxws f2, f4
; CHECK-P8-NEXT:    xscvspdpn f1, vs1
; CHECK-P8-NEXT:    xscvdpsxws f4, f5
; CHECK-P8-NEXT:    mtvsrd v4, r4
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    vmrghh v2, v4, v2
; CHECK-P8-NEXT:    mffprwz r4, f2
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mtvsrd v3, r3
; CHECK-P8-NEXT:    mffprwz r3, f3
; CHECK-P8-NEXT:    mtvsrd v4, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    vmrghh v3, v3, v4
; CHECK-P8-NEXT:    mtvsrd v4, r3
; CHECK-P8-NEXT:    mffprwz r3, f4
; CHECK-P8-NEXT:    mtvsrd v0, r4
; CHECK-P8-NEXT:    mtvsrd v5, r3
; CHECK-P8-NEXT:    mffprwz r3, f1
; CHECK-P8-NEXT:    vmrghh v5, v0, v5
; CHECK-P8-NEXT:    mtvsrd v1, r3
; CHECK-P8-NEXT:    vmrglw v2, v3, v2
; CHECK-P8-NEXT:    vmrghh v4, v4, v1
; CHECK-P8-NEXT:    vmrglw v3, v4, v5
; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
; CHECK-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    lxv vs1, 0(r3)
; CHECK-P9-NEXT:    xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT:    xscvspdpn f2, vs2
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    lxv vs0, 16(r3)
; CHECK-P9-NEXT:    mffprwz r3, f2
; CHECK-P9-NEXT:    xxswapd vs2, vs1
; CHECK-P9-NEXT:    mtvsrd v2, r3
; CHECK-P9-NEXT:    xscvspdpn f2, vs2
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    mffprwz r3, f2
; CHECK-P9-NEXT:    xscvspdpn f2, vs1
; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    vmrghh v2, v3, v2
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    mffprwz r3, f2
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    vmrghh v3, v3, v4
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    vmrglw v2, v3, v2
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    xxswapd vs1, vs0
; CHECK-P9-NEXT:    mtvsrd v3, r3
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    xscvspdpn f1, vs0
; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    vmrghh v3, v4, v3
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r3, f1
; CHECK-P9-NEXT:    mtvsrd v4, r3
; CHECK-P9-NEXT:    mffprwz r3, f0
; CHECK-P9-NEXT:    mtvsrd v5, r3
; CHECK-P9-NEXT:    vmrghh v4, v4, v5
; CHECK-P9-NEXT:    vmrglw v3, v4, v3
; CHECK-P9-NEXT:    xxmrgld v2, v3, v2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE:       # %bb.0: # %entry
; CHECK-BE-NEXT:    lxv vs1, 16(r3)
; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    lxv vs0, 0(r3)
; CHECK-BE-NEXT:    mffprwz r3, f2
; CHECK-BE-NEXT:    xxswapd vs2, vs1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    mtvsrd v2, r3
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    mffprwz r3, f2
; CHECK-BE-NEXT:    xscvspdpn f2, vs1
; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    vmrghh v2, v3, v2
; CHECK-BE-NEXT:    mffprwz r3, f2
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    xxswapd vs1, vs0
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    vmrghh v3, v3, v4
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    vmrghw v2, v3, v2
; CHECK-BE-NEXT:    mtvsrd v3, r3
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    xscvspdpn f1, vs0
; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    vmrghh v3, v4, v3
; CHECK-BE-NEXT:    mffprwz r3, f1
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v4, r3
; CHECK-BE-NEXT:    mffprwz r3, f0
; CHECK-BE-NEXT:    sldi r3, r3, 48
; CHECK-BE-NEXT:    mtvsrd v5, r3
; CHECK-BE-NEXT:    vmrghh v4, v4, v5
; CHECK-BE-NEXT:    vmrghw v3, v4, v3
; CHECK-BE-NEXT:    xxmrghd v2, v3, v2
; CHECK-BE-NEXT:    blr
entry:
  %a = load <8 x float>, <8 x float>* %0, align 32
  %1 = fptosi <8 x float> %a to <8 x i16>
  ret <8 x i16> %1
}

define void @test16elt_signed(<16 x i16>* noalias nocapture sret %agg.result, <16 x float>* nocapture readonly) local_unnamed_addr #3 {
; CHECK-P8-LABEL: test16elt_signed:
; CHECK-P8:       # %bb.0: # %entry
; CHECK-P8-NEXT:    lvx v5, 0, r4
; CHECK-P8-NEXT:    li r5, 16
; CHECK-P8-NEXT:    li r6, 32
; CHECK-P8-NEXT:    lvx v3, r4, r5
; CHECK-P8-NEXT:    lvx v2, r4, r6
; CHECK-P8-NEXT:    li r6, 48
; CHECK-P8-NEXT:    xxsldwi vs0, v5, v5, 3
; CHECK-P8-NEXT:    xscvspdpn f1, v5
; CHECK-P8-NEXT:    lvx v4, r4, r6
; CHECK-P8-NEXT:    xxswapd vs3, v5
; CHECK-P8-NEXT:    xxsldwi vs5, v5, v5, 1
; CHECK-P8-NEXT:    xxsldwi vs7, v3, v3, 3
; CHECK-P8-NEXT:    xxswapd vs8, v3
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xscvspdpn f3, vs3
; CHECK-P8-NEXT:    xscvspdpn f5, vs5
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    xscvspdpn f7, vs7
; CHECK-P8-NEXT:    xscvspdpn f8, vs8
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    xscvdpsxws f3, f3
; CHECK-P8-NEXT:    xscvspdpn f2, v3
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xscvdpsxws f1, f5
; CHECK-P8-NEXT:    mtvsrd v5, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    xxsldwi vs0, v3, v3, 1
; CHECK-P8-NEXT:    xscvspdpn f4, v2
; CHECK-P8-NEXT:    xscvdpsxws f5, f7
; CHECK-P8-NEXT:    xxsldwi vs7, v4, v4, 3
; CHECK-P8-NEXT:    mtvsrd v3, r4
; CHECK-P8-NEXT:    mffprwz r4, f3
; CHECK-P8-NEXT:    xxsldwi vs3, v2, v2, 3
; CHECK-P8-NEXT:    xscvspdpn f6, v4
; CHECK-P8-NEXT:    mtvsrd v0, r4
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xscvdpsxws f1, f8
; CHECK-P8-NEXT:    xxswapd vs8, v4
; CHECK-P8-NEXT:    xscvspdpn f0, vs0
; CHECK-P8-NEXT:    xscvdpsxws f2, f2
; CHECK-P8-NEXT:    mtvsrd v1, r4
; CHECK-P8-NEXT:    mffprwz r4, f5
; CHECK-P8-NEXT:    xxswapd vs5, v2
; CHECK-P8-NEXT:    xscvspdpn f3, vs3
; CHECK-P8-NEXT:    xscvdpsxws f4, f4
; CHECK-P8-NEXT:    vmrghh v3, v0, v3
; CHECK-P8-NEXT:    mtvsrd v0, r4
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xscvdpsxws f6, f6
; CHECK-P8-NEXT:    xscvspdpn f1, vs5
; CHECK-P8-NEXT:    xxsldwi vs5, v2, v2, 1
; CHECK-P8-NEXT:    mtvsrd v6, r4
; CHECK-P8-NEXT:    mffprwz r4, f2
; CHECK-P8-NEXT:    xscvdpsxws f0, f0
; CHECK-P8-NEXT:    vmrghh v2, v5, v1
; CHECK-P8-NEXT:    vmrghh v5, v6, v0
; CHECK-P8-NEXT:    mtvsrd v0, r4
; CHECK-P8-NEXT:    mffprwz r4, f4
; CHECK-P8-NEXT:    xscvdpsxws f2, f3
; CHECK-P8-NEXT:    xscvspdpn f5, vs5
; CHECK-P8-NEXT:    mtvsrd v1, r4
; CHECK-P8-NEXT:    mffprwz r4, f6
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mtvsrd v6, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    xscvspdpn f7, vs7
; CHECK-P8-NEXT:    mtvsrd v7, r4
; CHECK-P8-NEXT:    mffprwz r4, f2
; CHECK-P8-NEXT:    xxsldwi vs2, v4, v4, 1
; CHECK-P8-NEXT:    xscvspdpn f8, vs8
; CHECK-P8-NEXT:    xscvdpsxws f0, f5
; CHECK-P8-NEXT:    mtvsrd v4, r4
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    xscvspdpn f1, vs2
; CHECK-P8-NEXT:    xscvdpsxws f3, f7
; CHECK-P8-NEXT:    mtvsrd v8, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    xscvdpsxws f0, f8
; CHECK-P8-NEXT:    mtvsrd v9, r4
; CHECK-P8-NEXT:    xscvdpsxws f1, f1
; CHECK-P8-NEXT:    mffprwz r4, f3
; CHECK-P8-NEXT:    vmrghh v0, v0, v7
; CHECK-P8-NEXT:    mtvsrd v7, r4
; CHECK-P8-NEXT:    mffprwz r4, f0
; CHECK-P8-NEXT:    vmrghh v4, v8, v4
; CHECK-P8-NEXT:    mtvsrd v8, r4
; CHECK-P8-NEXT:    mffprwz r4, f1
; CHECK-P8-NEXT:    vmrghh v1, v1, v9
; CHECK-P8-NEXT:    mtvsrd v9, r4
; CHECK-P8-NEXT:    vmrghh v7, v8, v7
; CHECK-P8-NEXT:    vmrghh v6, v6, v9
; CHECK-P8-NEXT:    vmrglw v2, v2, v3
; CHECK-P8-NEXT:    vmrglw v3, v0, v5
; CHECK-P8-NEXT:    vmrglw v4, v1, v4
; CHECK-P8-NEXT:    vmrglw v5, v6, v7
; CHECK-P8-NEXT:    xxmrgld v2, v3, v2
; CHECK-P8-NEXT:    stvx v2, 0, r3
; CHECK-P8-NEXT:    xxmrgld v3, v5, v4
; CHECK-P8-NEXT:    stvx v3, r3, r5
; CHECK-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    lxv vs2, 0(r4)
; CHECK-P9-NEXT:    xxsldwi vs3, vs2, vs2, 3
; CHECK-P9-NEXT:    xxswapd vs4, vs2
; CHECK-P9-NEXT:    xscvspdpn f3, vs3
; CHECK-P9-NEXT:    xscvspdpn f4, vs4
; CHECK-P9-NEXT:    xscvdpsxws f3, f3
; CHECK-P9-NEXT:    xscvdpsxws f4, f4
; CHECK-P9-NEXT:    xscvspdpn f5, vs2
; CHECK-P9-NEXT:    xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT:    xscvspdpn f2, vs2
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    mffprwz r5, f3
; CHECK-P9-NEXT:    lxv vs1, 16(r4)
; CHECK-P9-NEXT:    xxsldwi vs6, vs1, vs1, 3
; CHECK-P9-NEXT:    xxswapd vs3, vs1
; CHECK-P9-NEXT:    mtvsrd v2, r5
; CHECK-P9-NEXT:    mffprwz r5, f4
; CHECK-P9-NEXT:    xscvdpsxws f4, f5
; CHECK-P9-NEXT:    xscvspdpn f3, vs3
; CHECK-P9-NEXT:    mtvsrd v3, r5
; CHECK-P9-NEXT:    vmrghh v2, v3, v2
; CHECK-P9-NEXT:    mffprwz r5, f4
; CHECK-P9-NEXT:    xscvspdpn f4, vs6
; CHECK-P9-NEXT:    mtvsrd v3, r5
; CHECK-P9-NEXT:    mffprwz r5, f2
; CHECK-P9-NEXT:    xscvspdpn f2, vs1
; CHECK-P9-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT:    xscvdpsxws f4, f4
; CHECK-P9-NEXT:    xscvdpsxws f3, f3
; CHECK-P9-NEXT:    lxv vs0, 32(r4)
; CHECK-P9-NEXT:    mtvsrd v4, r5
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    vmrghh v3, v3, v4
; CHECK-P9-NEXT:    vmrglw v2, v3, v2
; CHECK-P9-NEXT:    mffprwz r5, f4
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    mtvsrd v4, r5
; CHECK-P9-NEXT:    mffprwz r5, f3
; CHECK-P9-NEXT:    xxsldwi vs3, vs0, vs0, 3
; CHECK-P9-NEXT:    mtvsrd v5, r5
; CHECK-P9-NEXT:    mffprwz r5, f2
; CHECK-P9-NEXT:    xscvspdpn f2, vs3
; CHECK-P9-NEXT:    vmrghh v4, v5, v4
; CHECK-P9-NEXT:    mtvsrd v5, r5
; CHECK-P9-NEXT:    mffprwz r5, f1
; CHECK-P9-NEXT:    xxswapd vs1, vs0
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    mtvsrd v0, r5
; CHECK-P9-NEXT:    xscvspdpn f1, vs1
; CHECK-P9-NEXT:    vmrghh v5, v5, v0
; CHECK-P9-NEXT:    xscvdpsxws f1, f1
; CHECK-P9-NEXT:    vmrglw v3, v5, v4
; CHECK-P9-NEXT:    mffprwz r5, f2
; CHECK-P9-NEXT:    xscvspdpn f2, vs0
; CHECK-P9-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT:    mtvsrd v0, r5
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f2, f2
; CHECK-P9-NEXT:    mffprwz r5, f1
; CHECK-P9-NEXT:    lxv vs1, 48(r4)
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mtvsrd v1, r5
; CHECK-P9-NEXT:    vmrghh v0, v1, v0
; CHECK-P9-NEXT:    mffprwz r4, f2
; CHECK-P9-NEXT:    xxmrgld vs2, v3, v2
; CHECK-P9-NEXT:    mtvsrd v4, r4
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT:    mtvsrd v2, r4
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    vmrghh v2, v4, v2
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    vmrglw v2, v2, v0
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    xxswapd vs0, vs1
; CHECK-P9-NEXT:    mtvsrd v3, r4
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    xscvspdpn f0, vs1
; CHECK-P9-NEXT:    mtvsrd v4, r4
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    vmrghh v3, v4, v3
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    xxsldwi vs0, vs1, vs1, 1
; CHECK-P9-NEXT:    mtvsrd v4, r4
; CHECK-P9-NEXT:    xscvspdpn f0, vs0
; CHECK-P9-NEXT:    xscvdpsxws f0, f0
; CHECK-P9-NEXT:    mffprwz r4, f0
; CHECK-P9-NEXT:    mtvsrd v5, r4
; CHECK-P9-NEXT:    vmrghh v4, v4, v5
; CHECK-P9-NEXT:    vmrglw v3, v4, v3
; CHECK-P9-NEXT:    xxmrgld vs0, v3, v2
; CHECK-P9-NEXT:    stxv vs0, 16(r3)
; CHECK-P9-NEXT:    stxv vs2, 0(r3)
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE:       # %bb.0: # %entry
; CHECK-BE-NEXT:    lxv vs1, 16(r4)
; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    xxswapd vs3, vs1
; CHECK-BE-NEXT:    xscvspdpn f3, vs3
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    xscvdpsxws f3, f3
; CHECK-BE-NEXT:    mffprwz r5, f2
; CHECK-BE-NEXT:    xscvspdpn f4, vs1
; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    mtvsrd v2, r5
; CHECK-BE-NEXT:    mffprwz r5, f3
; CHECK-BE-NEXT:    xscvdpsxws f3, f4
; CHECK-BE-NEXT:    lxv vs0, 0(r4)
; CHECK-BE-NEXT:    xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    mtvsrd v3, r5
; CHECK-BE-NEXT:    vmrghh v2, v3, v2
; CHECK-BE-NEXT:    mffprwz r5, f3
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    mtvsrd v3, r5
; CHECK-BE-NEXT:    mffprwz r5, f1
; CHECK-BE-NEXT:    xxswapd vs1, vs0
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    mtvsrd v4, r5
; CHECK-BE-NEXT:    mffprwz r5, f2
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    vmrghh v3, v3, v4
; CHECK-BE-NEXT:    mtvsrd v4, r5
; CHECK-BE-NEXT:    vmrghw v2, v3, v2
; CHECK-BE-NEXT:    mffprwz r5, f1
; CHECK-BE-NEXT:    xscvspdpn f1, vs0
; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v5, r5
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    vmrghh v4, v5, v4
; CHECK-BE-NEXT:    mffprwz r5, f1
; CHECK-BE-NEXT:    lxv vs1, 48(r4)
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    mtvsrd v5, r5
; CHECK-BE-NEXT:    mffprwz r5, f0
; CHECK-BE-NEXT:    lxv vs0, 32(r4)
; CHECK-BE-NEXT:    xscvspdpn f5, vs1
; CHECK-BE-NEXT:    xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT:    xscvspdpn f2, vs2
; CHECK-BE-NEXT:    xscvdpsxws f5, f5
; CHECK-BE-NEXT:    sldi r5, r5, 48
; CHECK-BE-NEXT:    xxswapd vs3, vs1
; CHECK-BE-NEXT:    mtvsrd v0, r5
; CHECK-BE-NEXT:    vmrghh v5, v5, v0
; CHECK-BE-NEXT:    xscvspdpn f3, vs3
; CHECK-BE-NEXT:    xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f2, f2
; CHECK-BE-NEXT:    vmrghw v3, v5, v4
; CHECK-BE-NEXT:    xscvdpsxws f3, f3
; CHECK-BE-NEXT:    mffprwz r4, f5
; CHECK-BE-NEXT:    xxmrghd vs4, v3, v2
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v2, r4
; CHECK-BE-NEXT:    mffprwz r4, f2
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    stxv vs4, 0(r3)
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v3, r4
; CHECK-BE-NEXT:    mffprwz r4, f3
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v4, r4
; CHECK-BE-NEXT:    mffprwz r4, f1
; CHECK-BE-NEXT:    xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    vmrghh v3, v4, v3
; CHECK-BE-NEXT:    mtvsrd v4, r4
; CHECK-BE-NEXT:    mffprwz r4, f1
; CHECK-BE-NEXT:    xxswapd vs1, vs0
; CHECK-BE-NEXT:    xscvspdpn f1, vs1
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    vmrghh v2, v2, v4
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    vmrghw v2, v2, v3
; CHECK-BE-NEXT:    mtvsrd v3, r4
; CHECK-BE-NEXT:    mffprwz r4, f1
; CHECK-BE-NEXT:    xscvspdpn f1, vs0
; CHECK-BE-NEXT:    xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    xscvdpsxws f1, f1
; CHECK-BE-NEXT:    xscvspdpn f0, vs0
; CHECK-BE-NEXT:    mtvsrd v4, r4
; CHECK-BE-NEXT:    xscvdpsxws f0, f0
; CHECK-BE-NEXT:    vmrghh v3, v4, v3
; CHECK-BE-NEXT:    mffprwz r4, f1
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v4, r4
; CHECK-BE-NEXT:    mffprwz r4, f0
; CHECK-BE-NEXT:    sldi r4, r4, 48
; CHECK-BE-NEXT:    mtvsrd v5, r4
; CHECK-BE-NEXT:    vmrghh v4, v4, v5
; CHECK-BE-NEXT:    vmrghw v3, v4, v3
; CHECK-BE-NEXT:    xxmrghd vs0, v3, v2
; CHECK-BE-NEXT:    stxv vs0, 16(r3)
; CHECK-BE-NEXT:    blr
entry:
  %a = load <16 x float>, <16 x float>* %0, align 64
  %1 = fptosi <16 x float> %a to <16 x i16>
  store <16 x i16> %1, <16 x i16>* %agg.result, align 32
  ret void
}