# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---
name:            cbz_s32
legalized:       true
regBankSelected: true

body:             |
  ; CHECK-LABEL: name: cbz_s32
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK:   CBZW [[COPY]], %bb.1
  ; CHECK:   B %bb.0
  ; CHECK: bb.1:
  bb.0:
    liveins: $w0
    successors: %bb.0, %bb.1

    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 0
    %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
    %3:gpr(s1) = G_TRUNC %2(s32)
    G_BRCOND %3(s1), %bb.1
    G_BR %bb.0

  bb.1:
...

---
name:            cbz_s64
legalized:       true
regBankSelected: true

body:             |
  ; CHECK-LABEL: name: cbz_s64
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
  ; CHECK:   CBZX [[COPY]], %bb.1
  ; CHECK:   B %bb.0
  ; CHECK: bb.1:
  bb.0:
    liveins: $x0
    successors: %bb.0, %bb.1

    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 0
    %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
    %3:gpr(s1) = G_TRUNC %2(s32)
    G_BRCOND %3(s1), %bb.1
    G_BR %bb.0

  bb.1:
...

---
name:            cbnz_s32
legalized:       true
regBankSelected: true

body:             |
  ; CHECK-LABEL: name: cbnz_s32
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK:   [[COPY:%[0-9]+]]:gpr32 = COPY $w0
  ; CHECK:   CBNZW [[COPY]], %bb.1
  ; CHECK:   B %bb.0
  ; CHECK: bb.1:
  bb.0:
    liveins: $w0
    successors: %bb.0, %bb.1

    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 0
    %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
    %3:gpr(s1) = G_TRUNC %2(s32)
    G_BRCOND %3(s1), %bb.1
    G_BR %bb.0

  bb.1:
...

---
name:            cbnz_s64
legalized:       true
regBankSelected: true

body:             |
  ; CHECK-LABEL: name: cbnz_s64
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK:   [[COPY:%[0-9]+]]:gpr64 = COPY $x0
  ; CHECK:   CBNZX [[COPY]], %bb.1
  ; CHECK:   B %bb.0
  ; CHECK: bb.1:
  bb.0:
    liveins: $x0
    successors: %bb.0, %bb.1

    %0:gpr(s64) = COPY $x0
    %1:gpr(s64) = G_CONSTANT i64 0
    %2:gpr(s32) = G_ICMP intpred(ne), %0, %1
    %3:gpr(s1) = G_TRUNC %2(s32)
    G_BRCOND %3(s1), %bb.1
    G_BR %bb.0

  bb.1:
...
---
name:            test_rhs_inttoptr
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_rhs_inttoptr
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK:   liveins: $x0
  ; CHECK:   [[COPY:%[0-9]+]]:gpr64common = COPY $x0
  ; CHECK:   CBZX [[COPY]], %bb.2
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   STRXui $xzr, [[COPY]], 0 :: (store 8)
  ; CHECK: bb.2:
  ; CHECK:   RET_ReallyLR
  bb.1:
    successors: %bb.2, %bb.3
    liveins: $x0

    %0:gpr(p0) = COPY $x0
    %2:gpr(s64) = G_CONSTANT i64 0
    %1:gpr(p0) = G_INTTOPTR %2(s64)
    %4:gpr(s32) = G_ICMP intpred(eq), %0(p0), %1
    %3:gpr(s1) = G_TRUNC %4(s32)
    G_BRCOND %3(s1), %bb.3

  bb.2:
    %5:gpr(s64) = G_CONSTANT i64 0
    G_STORE %5(s64), %0(p0) :: (store 8)

  bb.3:
    RET_ReallyLR

...
---
name:            test_rhs_unknown
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: test_rhs_unknown
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK:   liveins: $x0
  ; CHECK:   [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
  ; CHECK:   [[LDRXui:%[0-9]+]]:gpr64common = LDRXui [[COPY]], 0 :: (load 8)
  ; CHECK:   $xzr = SUBSXri [[LDRXui]], 42, 0, implicit-def $nzcv
  ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   STRXui $xzr, [[COPY]], 0 :: (store 8)
  ; CHECK: bb.2:
  ; CHECK:   RET_ReallyLR
  bb.1:
    successors: %bb.2, %bb.3
    liveins: $x0

    %0:gpr(p0) = COPY $x0
    %2:gpr(s64) = G_CONSTANT i64 42
    %4:gpr(s64) = G_CONSTANT i64 0
    %1:gpr(s64) = G_LOAD %0(p0) :: (load 8)
    %5:gpr(s32) = G_ICMP intpred(eq), %1(s64), %2
    %3:gpr(s1) = G_TRUNC %5(s32)
    G_BRCOND %3(s1), %bb.3

  bb.2:
    %6:gpr(s64) = G_CONSTANT i64 0
    G_STORE %6(s64), %0(p0) :: (store 8)

  bb.3:
    RET_ReallyLR

...
---
name:            update_pred_minus_one
legalized:       true
regBankSelected: true

body:             |
  ; The G_ICMP here will be optimized into a slt against 0.
  ; The branch should inherit this change, so we should have Bcc 11 rather than
  ; Bcc 13.

  ; CHECK-LABEL: name: update_pred_minus_one
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK:   [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
  ; CHECK:   $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
  ; CHECK:   Bcc 11, %bb.1, implicit $nzcv
  ; CHECK:   B %bb.0
  ; CHECK: bb.1:
  bb.0:
    liveins: $w0
    successors: %bb.0, %bb.1

    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = G_CONSTANT i32 -1
    %2:gpr(s32) = G_ICMP intpred(sle), %0, %1
    %3:gpr(s1) = G_TRUNC %2(s32)
    G_BRCOND %3(s1), %bb.1
    G_BR %bb.0

  bb.1:
...