)]}'
{
  "commit": "911fe6cfab59ea7f2ec17b4e667c5312c9eba0b2",
  "tree": "d2c646d737afe98a823fba89f5d1d28d8f0d451b",
  "parents": [
    "821a5f0bef9dba8919067cfee44c4f71bca2b744"
  ],
  "author": {
    "name": "JayYang",
    "email": "jay.yang@intel.com",
    "time": "Mon Oct 19 19:52:26 2026 +0800"
  },
  "committer": {
    "name": "intel-mediadev",
    "email": "mediadev@intel.com",
    "time": "Mon Oct 19 20:15:02 2026 +0800"
  },
  "message": "[VP] [PDVT-SH] Embed SR3 slim bounded IR and add L0 IR graph compile\n\nEmbed the SR3 slim bounded OpenVINO IR (XML + BIN) as generated C++\nsource and add the Level Zero interface that compiles an IR into an NPU\ngraph at runtime. NPU is 64-bit only, so both the asset and the compile\npath are integrated for 64-bit builds only. There is no consumer yet.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e6b785ec8f4c27cc4088e712309fd0e7939b3ae9",
      "old_mode": 33188,
      "old_path": "media_softlet/agnostic/common/os/levelzero/levelzero_npu_interface.h",
      "new_id": "b3118662be633c217ce934c97f6837a1ed9a78d3",
      "new_mode": 33188,
      "new_path": "media_softlet/agnostic/common/os/levelzero/levelzero_npu_interface.h"
    },
    {
      "type": "modify",
      "old_id": "641a3241b98faf799a159ac98e7835e72fe7f57f",
      "old_mode": 33188,
      "old_path": "media_softlet/linux/common/os/levelzero/levelzero_npu_interface.cpp",
      "new_id": "c775179071a14e7c73505c993c677d500c9410d6",
      "new_mode": 33188,
      "new_path": "media_softlet/linux/common/os/levelzero/levelzero_npu_interface.cpp"
    }
  ]
}