)]}'
{
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        "time": "Tue Jun 18 16:28:57 2019 -0700"
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      "committer": {
        "name": "mcu-administrator",
        "email": "mcu_administrator@intel.com",
        "time": "Tue Jun 18 16:28:57 2019 -0700"
      },
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    {
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      "tree": "833e7e02a0ff1f08caeaaea5d324c35de3819090",
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        "email": "phil.meyers@intel.com",
        "time": "Thu May 16 07:41:55 2019 -0700"
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        "name": "rpmeyers",
        "email": "phil.meyers@intel.com",
        "time": "Thu May 16 07:41:55 2019 -0700"
      },
      "message": "Corrections to previous version of releasenote.\n\nCorrected versions:\nIVB-E/EP\t   C1/M1/S1  6-3e-4/ed 0000042d-\u003e0000042e  Core Gen3 X Series; Xeon E5 v2\nBDX-ML     B0/M0/R0  6-4f-1/ef 0b00002e-\u003e0b0000036  Xeon E5/E7 v4; Core i7-69xx/68xx\n\nAdded missed line:\nAPL  E0  6-5c-a/03  0000000c-\u003e00000016  Atom x5-E9xx\n"
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        "time": "Tue May 14 07:15:15 2019 -0700"
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      "committer": {
        "name": "mcu-administrator",
        "email": "mcu_administrator@intel.com",
        "time": "Tue May 14 08:24:17 2019 -0700"
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      "message": "microcode-20190514 Release\n"
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    {
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        "time": "Tue Mar 12 10:54:00 2019 -0700"
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      "committer": {
        "name": "mcu-administrator",
        "email": "mcu_administrator@intel.com",
        "time": "Tue Mar 12 10:54:00 2019 -0700"
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      "message": "microcode-20190312 Release\n"
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      "committer": {
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}