commit 19ab5207419aed944a37c07087a2e2274e70621e
author johnbasha shaik <johnbasha.shaik@intel.com> Wed Sep 04 15:17:28 2019 +0530
committer johnbasha shaik <johnbasha.shaik@intel.com> Wed Sep 04 15:17:28 2019 +0530
tree bce30ea6b17fdd908c507ac32475709e429a7083
parent 2d58b09a0af3b76ad965be7228aa9eca20e9380e

Fix static MOCS table for Gen9 Atom platforms

Description: Static MOCS table for Gen9 Atom platforms had a bug where
it was setting LRUM/Age to 0 for MOCS index 2. This patch fixes this
issue.

Change-Id: I6acc9236b2ee65cded23402b2d322c72661051ee

Source/GmmLib/CachePolicy/GmmGen9CachePolicy.cpp

diff --git a/Source/GmmLib/CachePolicy/GmmGen9CachePolicy.cpp b/Source/GmmLib/CachePolicy/GmmGen9CachePolicy.cpp
index 06500b3..c16516f 100644
--- a/Source/GmmLib/CachePolicy/GmmGen9CachePolicy.cpp
+++ b/Source/GmmLib/CachePolicy/GmmGen9CachePolicy.cpp
@@ -144,11 +144,11 @@
                pGmmGlobalContext->GetPlatformInfo().Platform.eProductFamily == IGFX_GEMINILAKE)
             {
                 UsageEle.LeCC.AOM          = 0;
-                UsageEle.LeCC.LRUM         = 0;
                 UsageEle.LeCC.Cacheability = LeCC_UNCACHEABLE; // To avoid side effects use 01b even though 01b(UC) 11b(WB) are equivalent option
 
 #if defined(GMM_DYNAMIC_MOCS_TABLE)
                 UsageEle.LeCC.TargetCache = TC_LLC; // No LLC for Broxton, but we still set it to LLC since it is needed for IA coherency cases
+                UsageEle.LeCC.LRUM         = 0;
 #else
                 UsageEle.LeCC.TargetCache = TC_LLC_ELLC; // To match I915_GEN9_MOCS[0]
 #endif