)]}' { "log": [ { "commit": "2801427972c4b0d4c0165edb509f21186103f21f", "tree": "aecbc2e38a55de2019fb1b8c9b37668cec426cdd", "parents": [ "31cc34762c58d16eaee59abff5c4cc3cd0e68399", "66e46af64f0c15ee2ddb22fda39df836c6ec1937" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Mon Jan 26 15:31:35 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 26 15:31:35 2026 +0000" }, "message": "Merge changes I6deddab4,I432b05b2,I4af7371d,I2318ea4b into integration\n\n* changes:\n feat(rdv3): use SFCP PSA call instead of RSE comms\n feat(tc): use SFCP PSA call instead of RSE comms\n feat(tc): add tc_sfcp.c\n feat(sfcp): add SFCP stack and PSA call\n" }, { "commit": "31cc34762c58d16eaee59abff5c4cc3cd0e68399", "tree": "5f7d1587eeef464514be7004ba2ec742055fc61d", "parents": [ "666a488beaf67f8de2c553810ca3fbcb1616351c", "424539959690bdc8180469b4e67eeec00b617aec" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sat Jan 24 02:30:30 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Jan 24 02:30:30 2026 +0000" }, "message": "Merge changes from topic \"jp/cve-2025-0647\" into integration\n\n* changes:\n fix(security): add CVE-2025-0647 for C1-Premium\n fix(security): add CVE-2025-0647 for C1-Ultra\n fix(security): add CVE-2025-0647 for Neoverse-V3\n fix(security): add CVE-2025-0647 for Neoverse-V2\n fix(security): add CVE-2025-0647 for Neoverse-N2\n fix(security): add CVE-2025-0647 for Cortex-X925\n fix(security): add CVE-2025-0647 for Cortex-X4\n fix(security): add CVE-2025-0647 for Cortex-X3\n fix(security): add CVE-2025-0647 for Cortex-X2\n fix(security): add CVE-2025-0647 for Cortex-A710\n" }, { "commit": "666a488beaf67f8de2c553810ca3fbcb1616351c", "tree": "e140e770aaa01a2945a5bf7c5acdd7ad75951ad8", "parents": [ "e4731b1cf2a3b8a779944e12bfb94f107df5e6fe", "416b8613bc65b277d40fa43c90f36f4b65f67b96" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Sat Jan 24 02:30:08 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Sat Jan 24 02:30:08 2026 +0000" }, "message": "Merge \"fix(security): add workaround for CVE-2025-0647\" into integration" }, { "commit": "424539959690bdc8180469b4e67eeec00b617aec", "tree": "5f7d1587eeef464514be7004ba2ec742055fc61d", "parents": [ "2bf674ef6ec6b9aa3852e4ccf7c458d6a31e385b" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:46:18 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for C1-Premium\n\nThis patch mitigates CVE-2025-0647 for C1-Premium CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: Iec070b6e2a73c6218d150e32149b25ba4c94ea3a\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "416b8613bc65b277d40fa43c90f36f4b65f67b96", "tree": "e140e770aaa01a2945a5bf7c5acdd7ad75951ad8", "parents": [ "e4731b1cf2a3b8a779944e12bfb94f107df5e6fe" ], "author": { "name": "John Powell", "email": "john.powell@arm.com", "time": "Wed Mar 05 13:23:35 2025 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add workaround for CVE-2025-0647\n\nThis workaround fixes an issue with the CPP RCTX instruction by\nissuing an instruction patch sequence to trap uses of the CPP RCTX\ninstruction from EL0, EL1, and EL2 to EL3 and perform a workaround\nprocedure using the implementation defined trap handler to ensure\nthe correct behavior of the system. In addition, it includes an EL3\nAPI to be used if EL3 firmware needs to use the CPP RCTX instruction.\nThis saves the overhead of exception handling, and EL3 does not\ngenerically support trapping EL3-\u003eEL3, and adding support for that\nis not trivial due to the implications for context management.\n\nThe issue affects the following CPUs:\n\nC1-Premium\nC1-Ultra\nCortex-A710\nCortex-X2\nCortex-X3\nCortex-X4\nCortex-X925\nNeoverse N2\nNeoverse V2\nNeoverse V3\nNeoverse V3AE (handled same as V3 CPU in TF-A CPU-Lib)\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: I5e7589afbeb69ebb79c01bec80e29f572aff3d89\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "2bf674ef6ec6b9aa3852e4ccf7c458d6a31e385b", "tree": "a6042521bf5fdafb55bd2daa95dff037f204576b", "parents": [ "efdd8ce6c7a5a23c3cac5dc01cedbaefad4010fa" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:44:43 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for C1-Ultra\n\nThis patch mitigates CVE-2025-0647 for C1-Ultra CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: I506007ec8702b183e377be50eede72d6803b344b\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "efdd8ce6c7a5a23c3cac5dc01cedbaefad4010fa", "tree": "758bd9919467873ae973881187a9583d0e9e386c", "parents": [ "145603e9739fcfd020aa16330d662a5765522b81" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:21:24 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for Neoverse-V3\n\nThis patch mitigates CVE-2025-0647 for Neoverse-V3 CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: Ic52ad93474c5f81e01eb4839ece726c84c3348ff\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "145603e9739fcfd020aa16330d662a5765522b81", "tree": "cbe5b2c213c64fe83f2b2772d86306c79e451e53", "parents": [ "a142b1020d1f6345a982d49009ab727d6acb3ef2" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:20:40 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for Neoverse-V2\n\nThis patch mitigates CVE-2025-0647 for Neoverse-V2 CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: I7ec215a9dd168eb045366b589a02b54148f587c2\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "a142b1020d1f6345a982d49009ab727d6acb3ef2", "tree": "b975b33f580b3f3f7905520978da786e7529aece", "parents": [ "f26fb932474d93621711434faf9ff5f1057b4751" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:19:52 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for Neoverse-N2\n\nThis patch mitigates CVE-2025-0647 for Neoverse-N2 CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: I366c2683cca22403d33f0761487e1ffa62e964ce\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "f26fb932474d93621711434faf9ff5f1057b4751", "tree": "3c5bbc27a7e3531340515e5e4f1128aed72ae8c9", "parents": [ "680a74b115648cffae29d9ebe92837a7814fa173" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:19:08 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for Cortex-X925\n\nThis patch mitigates CVE-2025-0647 for Cortex-X925 CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: I4c1ac2be3620566813c90f5815ffcc7205bb5ac9\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "680a74b115648cffae29d9ebe92837a7814fa173", "tree": "d66955badde3c89e466137b2e3122899c25cd537", "parents": [ "7fe900e3862ee09f66dff849addf384e7047f03e" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:18:37 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for Cortex-X4\n\nThis patch mitigates CVE-2025-0647 for Cortex-X4 CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: I585a7ea516515fe16a3eca907695728068cef611\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "7fe900e3862ee09f66dff849addf384e7047f03e", "tree": "a2a78dc2325e38171f068088073bf5520c398ddb", "parents": [ "9c17b3ef57d55788498038479e12859995e8a2d5" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:17:33 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for Cortex-X3\n\nThis patch mitigates CVE-2025-0647 for Cortex-X3 CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: Ic276befafc1ca0b456826532437ca453eb7717a6\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "9c17b3ef57d55788498038479e12859995e8a2d5", "tree": "173524e1818474bae1823588d4b7d56ddb03a140", "parents": [ "a52dcaee5ae926c4afa0dd01fd7b58e71fd3fb58" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:09:56 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for Cortex-X2\n\nThis patch mitigates CVE-2025-0647 for Cortex-X2 CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: Idba607340d944a6387759c856e8eacc967e0ec06\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "a52dcaee5ae926c4afa0dd01fd7b58e71fd3fb58", "tree": "2042e7db99323a156acc0f5b9c82c2571e2f26c4", "parents": [ "416b8613bc65b277d40fa43c90f36f4b65f67b96" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 15:06:15 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 23 15:14:36 2026 -0600" }, "message": "fix(security): add CVE-2025-0647 for Cortex-A710\n\nThis patch mitigates CVE-2025-0647 for Cortex-A710 CPU.\n\nArm Security Bulletin Document:\nhttps://developer.arm.com/documentation/111546\n\nChange-Id: I522dedfffd3108f7a94df1ce2cabd742ce682334\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\nSigned-off-by: John Powell \u003cjohn.powell@arm.com\u003e\n" }, { "commit": "e4731b1cf2a3b8a779944e12bfb94f107df5e6fe", "tree": "bd7a767371f074e90156dc67cdd98629b93046f0", "parents": [ "a806cc5a43899f1ec7889f4b479a161225e1a766", "a60aeae75c0596cc594ea4e881bef62f9ead247a" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Fri Jan 23 15:19:05 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 23 15:19:05 2026 +0000" }, "message": "Merge changes from topic \"upstream_ddr_training\" into integration\n\n* changes:\n feat(s32g274ardb): add DDR post training setup\n feat(s32g274ardb): add training for 1D and 2D\n feat(s32g274ardb): add DDR training stubs\n" }, { "commit": "a806cc5a43899f1ec7889f4b479a161225e1a766", "tree": "6890109d77aa3d27c01d199a635ad561756c259c", "parents": [ "6da9177c1f10f5ed532f1f8c6244050519fb4ac8", "996d08b8b909250327284ee42cf218c0773ff233" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Jan 22 20:13:51 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 22 20:13:51 2026 +0000" }, "message": "Merge changes I2485d583,I1374c482,I07e29dbb,I949e6486 into integration\n\n* changes:\n feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB\n feat(cpufeat): update FEAT_SB\u0027s FEAT_STATE_CHECKED status\n feat(cpufeat): advertise support for FEAT_RASv2\n feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again\n" }, { "commit": "6da9177c1f10f5ed532f1f8c6244050519fb4ac8", "tree": "81ddb9e43761a6655e12f5010074c95571b1a003", "parents": [ "4d1680c951b60b699a36ec97ce38d0f95153a603", "ed98a62602052094799aae342a7593c7740ec729" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 22 16:57:39 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 22 16:57:39 2026 +0000" }, "message": "Merge changes from topic \"xl/c1-workaround-fix\" into integration\n\n* changes:\n fix(cpus): fix the ordering of errata for C1 Premium\n fix(cpus): fix the ordering of errata for C1 Ultra\n" }, { "commit": "4d1680c951b60b699a36ec97ce38d0f95153a603", "tree": "d5e72f001f14831047a1de458a8b530e68e867cc", "parents": [ "7b2567911b53a4739607721d16ae15d88681e1ae", "5eceb40373a146f668115cb3be8c50176676c404" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 22 16:46:03 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 22 16:46:03 2026 +0000" }, "message": "Merge changes I3a2243d0,Ifeb88c8f,I8ac77336 into integration\n\n* changes:\n feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION\n docs(cpufeat): add analysis of 2024 features\n fix(cpufeat): add FEAT_SPE to FEATURE_DETECTION\n" }, { "commit": "7b2567911b53a4739607721d16ae15d88681e1ae", "tree": "735b15db920a15bfed28017ac0ef8ebfb6fd6d96", "parents": [ "50a819f7d3a2052125a5bfd39d232a289718e409", "7cc8f16593faa7c74284547fb0b9917ddd71fa84" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Thu Jan 22 15:54:48 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 22 15:54:48 2026 +0000" }, "message": "Merge \"fix(arm): build fails on RESET_TO_BL2\u003d1 and ARM_FW_CONFIG_LOAD_ENABLE\u003d1\" into integration" }, { "commit": "ed98a62602052094799aae342a7593c7740ec729", "tree": "10ce164f7a99349d9f2c1a5d18660a19a4f93cf4", "parents": [ "b8fd42ac248375f05683823f9d85a96879ba4a09" ], "author": { "name": "Xialin Liu", "email": "xialin.liu@arm.com", "time": "Thu Jan 22 08:44:31 2026 -0600" }, "committer": { "name": "Xialin Liu", "email": "xialin.liu@arm.com", "time": "Thu Jan 22 08:49:36 2026 -0600" }, "message": "fix(cpus): fix the ordering of errata for C1 Premium\n\nReorder the errata to comply with the convention.\n\nChange-Id: Ifd1c73224060c1c2e94c5f7978e9dc79e0229bd4\nSigned-off-by: Xialin Liu \u003cxialin.liu@arm.com\u003e\n" }, { "commit": "b8fd42ac248375f05683823f9d85a96879ba4a09", "tree": "8a089097d1d53975e2c8a77bcaf67c165962a96e", "parents": [ "1ff8aec1b5feceb286501d7eb0237d0cc503c5db" ], "author": { "name": "Xialin Liu", "email": "xialin.liu@arm.com", "time": "Thu Jan 22 08:23:36 2026 -0600" }, "committer": { "name": "Xialin Liu", "email": "xialin.liu@arm.com", "time": "Thu Jan 22 08:49:36 2026 -0600" }, "message": "fix(cpus): fix the ordering of errata for C1 Ultra\n\nThe CVE workaround is placed before errata workaround,\nfix it to comply with the convention.\n\nChange-Id: I6482ce4015541c64d9ac0d9c9df2e84d0c9eaae0\nSigned-off-by: Xialin Liu \u003cxialin.liu@arm.com\u003e\n" }, { "commit": "50a819f7d3a2052125a5bfd39d232a289718e409", "tree": "3f005276b1701e3ad6e20d02eb21e05cb9000a74", "parents": [ "14215dac2e5d0b5c5060fc897514a4efa5a29daa", "c46f2d9882b497d40a9808fc2854fa5e2bf86b76" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 22 14:47:04 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 22 14:47:04 2026 +0000" }, "message": "Merge \"fix(build): assign the ldflags-common variable before appending to it\" into integration" }, { "commit": "a60aeae75c0596cc594ea4e881bef62f9ead247a", "tree": "5df2c63257bfe23e3e4eb7c96612f59c0d359881", "parents": [ "47f0a591a46da853bafdc7c3936836f6b4733cb5" ], "author": { "name": "Khristine Andreea Barbulescu", "email": "khristineandreea.barbulescu@nxp.com", "time": "Thu Oct 09 14:13:48 2025 +0300" }, "committer": { "name": "Khristine Andreea Barbulescu", "email": "khristineandreea.barbulescu@nxp.com", "time": "Thu Jan 22 16:42:13 2026 +0200" }, "message": "feat(s32g274ardb): add DDR post training setup\n\nAdd the final configuration step after PHY\ntraining, including CSR storage, memory\ninitialization and DDRC adjustments.\n\nThe post training setup is now integrated into\nthe DDR initialization flow.\n\nChange-Id: I457d1f58479b282607c9d42773d6f922f563b2fb\nSigned-off-by: Ghennadi Procopciuc \u003cghennadi.procopciuc@nxp.com\u003e\nSigned-off-by: Andrei Cherechesu \u003candrei.cherechesu@nxp.com\u003e\nSigned-off-by: Khristine Andreea Barbulescu \u003ckhristineandreea.barbulescu@nxp.com\u003e\n" }, { "commit": "14215dac2e5d0b5c5060fc897514a4efa5a29daa", "tree": "caffc9535bc92a73b3698303d8174a037cb8930e", "parents": [ "1ff8aec1b5feceb286501d7eb0237d0cc503c5db", "7724f91e36269aa927de859fd5c22e9b018e1969" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 22 14:37:14 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 22 14:37:14 2026 +0000" }, "message": "Merge \"refactor(psci): make CMOs target the whole psci_cpu_data_t\" into integration" }, { "commit": "66e46af64f0c15ee2ddb22fda39df836c6ec1937", "tree": "bd6bd8d199eec4b79476fd911fc9aa51ff54516d", "parents": [ "65a492522d60a889ac5b8a394a1ae6511df8a610" ], "author": { "name": "Jackson Cooper-Driver", "email": "jackson.cooper-driver@arm.com", "time": "Tue Dec 02 10:50:20 2025 +0000" }, "committer": { "name": "Jackson Cooper-Driver", "email": "jackson.cooper-driver@arm.com", "time": "Thu Jan 22 10:58:58 2026 +0000" }, "message": "feat(rdv3): use SFCP PSA call instead of RSE comms\n\nIn a similar manner to the TC platform, add the SFCP platform\ndefinitions for RDV3. SFCP is then used instead of RSE comms for making\nPSA calls into the RSE.\n\nChange-Id: I6deddab452026ba24bd2462bcf2f11846af6f80b\nSigned-off-by: Jackson Cooper-Driver \u003cjackson.cooper-driver@arm.com\u003e\n" }, { "commit": "65a492522d60a889ac5b8a394a1ae6511df8a610", "tree": "8bd8c2dfe10356007f28a316bfe1bb8c7c14111a", "parents": [ "05076cbf009dc60f7a197a6be792786bc56d5491" ], "author": { "name": "Jackson Cooper-Driver", "email": "jackson.cooper-driver@arm.com", "time": "Tue Dec 02 10:19:15 2025 +0000" }, "committer": { "name": "Jackson Cooper-Driver", "email": "jackson.cooper-driver@arm.com", "time": "Thu Jan 22 10:58:58 2026 +0000" }, "message": "feat(tc): use SFCP PSA call instead of RSE comms\n\nAdd the platform specific implementation for SFCP (the implementation of\nthe functions in sfcp_platform.h). This includes functions which specify\nthe device structures and also the routing tables.\n\nNote that, because initially the SFCP stack is only used to make PSA\ncalls to the RSE, routing is only implemented for the TF-A \u003c-\u003e RSE\nnodes. The only MHU devices defined in the SFCP platform implementation\nare for this link and all other routes, as defined in the routing table,\nas invalid.\n\nThis patch also removes compilation of RSE comms in favour of SFCP for\nTC.\n\nChange-Id: I432b05b2955c790c4a5ecff04764605c6ff0ceea\nSigned-off-by: Jackson Cooper-Driver \u003cjackson.cooper-driver@arm.com\u003e\n" }, { "commit": "05076cbf009dc60f7a197a6be792786bc56d5491", "tree": "7ddcea9823db7bd9c668ec1f8bc595bee3484cd3", "parents": [ "479e2648eb22a5bf39aed18ea9f2ff834cf26200" ], "author": { "name": "Jackson Cooper-Driver", "email": "jackson.cooper-driver@arm.com", "time": "Thu Jan 22 10:53:22 2026 +0000" }, "committer": { "name": "Jackson Cooper-Driver", "email": "jackson.cooper-driver@arm.com", "time": "Thu Jan 22 10:56:16 2026 +0000" }, "message": "feat(tc): add tc_sfcp.c\n\nAdd the SFCP platform configuration file for TC. This file defines the\nfunctions in declared in sfcp_platform.h; these are used in\nsfcp_link_hal.c.\n\nNote that these functions are expected to be implemented by any TF-A\nplatform which makes use of the SFCP library, they define the underlying\ndevice driver structures and the routing layout of the platform.\n\nChange-Id: I4af7371decd1faabbd0ed7bc186339668a0c6b1a\nSigned-off-by: Jackson Cooper-Driver \u003cjackson.cooper-driver@arm.com\u003e\n" }, { "commit": "479e2648eb22a5bf39aed18ea9f2ff834cf26200", "tree": "77cbef20509b8b95e225df381cfbca5db66e4f3b", "parents": [ "1ff8aec1b5feceb286501d7eb0237d0cc503c5db" ], "author": { "name": "Jackson Cooper-Driver", "email": "jackson.cooper-driver@arm.com", "time": "Thu Nov 27 16:15:16 2025 +0000" }, "committer": { "name": "Jackson Cooper-Driver", "email": "jackson.cooper-driver@arm.com", "time": "Thu Jan 22 10:48:32 2026 +0000" }, "message": "feat(sfcp): add SFCP stack and PSA call\n\nAdd SFCP stack from trusted-firmware-m commit 8eb72a3bc5cc. SFCP is the\nSimple Firmware Communication Protocol, which is a more substantial\nsoftware stack designed to replace the existing RSE comms (and indeed\nwider communication between firmware components in the system). It has\nsupport for both polling mode and interrupt driver communication\nhandling, and is able to support any underlying transport (this patch\nadds MHU only). It requires a static routing layout between system\ncomponents.\n\nThis patch adds the link layer (with support for the MHU transport),\ntop-level SFCP API implementation and the implementation of PSA\ncall making use of the SFCP API.\n\nNote that encryption support is not implemented and only the stub\nencryption implementation is added in this patch. This can be\nimplemented when TF-A needs it.\n\nThe sfcp_link_hal.c implementation is the same as that in\ntrusted-firmware-m, and it makes use of the MHU V2 and V3 drivers\ndirectly. This is possible as the underlying MHU driver APIs is the same\nin trusted-firmware-m and trusted-firmware-a.\n\nChange-Id: I2318ea4bdb4e533b8a4a5000040aec0635a83857\nSigned-off-by: Jackson Cooper-Driver \u003cjackson.cooper-driver@arm.com\u003e\n" }, { "commit": "1ff8aec1b5feceb286501d7eb0237d0cc503c5db", "tree": "473f5e9599fe2d9545a0ac96910055d8901ce1df", "parents": [ "d76ad885e9db69ee02b156a44a521669c33e82a8", "b0c7709a651f2dbb0a5982e8f86b66b1d11fcd23" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Jan 21 16:13:55 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 21 16:13:55 2026 +0000" }, "message": "Merge \"fix(cpufeat): give `stxr` distinct src and ret registers\" into integration" }, { "commit": "d76ad885e9db69ee02b156a44a521669c33e82a8", "tree": "1226366d0febb1a71789193b3c3f10db373b6a9c", "parents": [ "16f29ded6f712577b2435956920755a4c8ec62b8", "802a68b504805952aac4e12993f3ecad1d9d201e" ], "author": { "name": "Madhukar Pappireddy", "email": "madhukar.pappireddy@arm.com", "time": "Wed Jan 21 13:30:17 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 21 13:30:17 2026 +0000" }, "message": "Merge \"refactor(s32g274ardb): add MC RGM DDR periph macro\" into integration" }, { "commit": "16f29ded6f712577b2435956920755a4c8ec62b8", "tree": "4572ca5abce7b0bce2e51564e17f6cd4a3c83865", "parents": [ "00e3fb94969bd4cebf428eef40f4fe9c28018fb7", "be276a82bfe5cfc95ce4e5f9a8eccc3377efa458" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Wed Jan 21 08:59:01 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 21 08:59:01 2026 +0000" }, "message": "Merge changes I907156cb,I377ef950 into integration\n\n* changes:\n fix(mt8196): check apusys write ce binary address\n fix(mt8196): increase apusys hardware semaphore timeout duration\n" }, { "commit": "b0c7709a651f2dbb0a5982e8f86b66b1d11fcd23", "tree": "efad3f27b595f6f271755f27114895bf5b5b2b0c", "parents": [ "040ab75ddc5d5b1e01bdb3b150a28986eaa47515" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jan 20 08:21:52 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Wed Jan 21 08:39:46 2026 +0000" }, "message": "fix(cpufeat): give `stxr` distinct src and ret registers\n\nThe stxr can cause UNDEF exceptions if the source and return\noperands overlap. Add an early-clobber constraint to tell the compiler\nnot to do that.\n\nChange-Id: I1d2752839e17b847f8981169eaf2798ee8fd100a\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "47f0a591a46da853bafdc7c3936836f6b4733cb5", "tree": "e1fcc8363d1d92a7981ac0e4e7dc170b6c4cd7b2", "parents": [ "54239065309a41a5b7901b928fc13723fd3483db" ], "author": { "name": "Khristine Andreea Barbulescu", "email": "khristineandreea.barbulescu@nxp.com", "time": "Thu Oct 09 14:11:36 2025 +0300" }, "committer": { "name": "Khristine Andreea Barbulescu", "email": "khristineandreea.barbulescu@nxp.com", "time": "Wed Jan 21 10:30:15 2026 +0200" }, "message": "feat(s32g274ardb): add training for 1D and 2D\n\nExtend the logic for executing the training stage\nto include 1D and 2D PHY training.\n\nChange-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea\nSigned-off-by: Ghennadi Procopciuc \u003cghennadi.procopciuc@nxp.com\u003e\nSigned-off-by: Andrei Cherechesu \u003candrei.cherechesu@nxp.com\u003e\nSigned-off-by: Khristine Andreea Barbulescu \u003ckhristineandreea.barbulescu@nxp.com\u003e\n" }, { "commit": "54239065309a41a5b7901b928fc13723fd3483db", "tree": "0047894918d00e60090ef23e377dd82dfb7beacf", "parents": [ "040ab75ddc5d5b1e01bdb3b150a28986eaa47515" ], "author": { "name": "Khristine Andreea Barbulescu", "email": "khristineandreea.barbulescu@nxp.com", "time": "Thu Oct 09 14:05:25 2025 +0300" }, "committer": { "name": "Khristine Andreea Barbulescu", "email": "khristineandreea.barbulescu@nxp.com", "time": "Wed Jan 21 10:29:35 2026 +0200" }, "message": "feat(s32g274ardb): add DDR training stubs\n\nIntroduce logic to load DDR firmware configuration\ndata from memory into internal structures.\n\nIntroduce the components required to initialize\nthe DDR controller and prepare for PHY training.\nIt includes controller setup and the training\norchestration function.\n\nChange-Id: Icd8649516d9bad1a6d72616a774b8b60c6bae067\nSigned-off-by: Ghennadi Procopciuc \u003cghennadi.procopciuc@nxp.com\u003e\nSigned-off-by: Andrei Cherechesu \u003candrei.cherechesu@nxp.com\u003e\nSigned-off-by: Khristine Andreea Barbulescu \u003ckhristineandreea.barbulescu@nxp.com\u003e\n" }, { "commit": "802a68b504805952aac4e12993f3ecad1d9d201e", "tree": "8d4c807fac19f0ff83d7d48f18fde468f013bd8e", "parents": [ "4f2f477636be9bf7fe54068136f3c0a405c869af" ], "author": { "name": "Khristine Andreea Barbulescu", "email": "khristineandreea.barbulescu@nxp.com", "time": "Sun Nov 02 22:10:26 2025 +0200" }, "committer": { "name": "Khristine Andreea Barbulescu", "email": "khristineandreea.barbulescu@nxp.com", "time": "Wed Jan 21 10:20:52 2026 +0200" }, "message": "refactor(s32g274ardb): add MC RGM DDR periph macro\n\nReplace value with MC_RGM_DDR_PERIPH macro\nto clearly identify the DDR peripheral ID\nused in MC_RGM register operations.\n\nChange-Id: I43756e5df068fb4f523b37a9db3a4a9ce8be836a\nSigned-off-by: Khristine Andreea Barbulescu \u003ckhristineandreea.barbulescu@nxp.com\u003e\n" }, { "commit": "be276a82bfe5cfc95ce4e5f9a8eccc3377efa458", "tree": "4572ca5abce7b0bce2e51564e17f6cd4a3c83865", "parents": [ "61718651158f4d27c02d024e3f68958917aac36d" ], "author": { "name": "Yuan-chang Hsieh", "email": "yuan-chang.hsieh@mediatek.corp-partner.google.com", "time": "Fri Jan 16 13:41:38 2026 +0800" }, "committer": { "name": "Yuan-chang Hsieh", "email": "yuan-chang.hsieh@mediatek.corp-partner.google.com", "time": "Wed Jan 21 15:16:55 2026 +0800" }, "message": "fix(mt8196): check apusys write ce binary address\n\nThe address and value to be written to the CE bin are set by the image\nloaded by the kernel.\nCheck the address to ensure that no illegal address is accessed.\n\nChange-Id: I907156cb9f304825839433cae0e31b319abc22bd\nSigned-off-by: Yuan-chang Hsieh \u003cyuan-chang.hsieh@mediatek.corp-partner.google.com\u003e\n" }, { "commit": "61718651158f4d27c02d024e3f68958917aac36d", "tree": "a91f16cb5de9dd547ca5e3339e4079251817728f", "parents": [ "867fe8ec915303fabcc67b28576ddf36afc03b14" ], "author": { "name": "Yuan-chang Hsieh", "email": "yuan-chang.hsieh@mediatek.corp-partner.google.com", "time": "Wed Jan 14 15:52:56 2026 +0800" }, "committer": { "name": "Yuan-chang Hsieh", "email": "yuan-chang.hsieh@mediatek.corp-partner.google.com", "time": "Wed Jan 21 15:16:02 2026 +0800" }, "message": "fix(mt8196): increase apusys hardware semaphore timeout duration\n\nIncrease the hw semaphore timeout duration because the kernel may\noccasionally fail to acquire semaphore, resulting in power on/off\nfailed.\n\nChange-Id: I377ef95063eb82abf2a63ea8f8fce803ef45bcf6\nSigned-off-by: Yuan-chang Hsieh \u003cyuan-chang.hsieh@mediatek.corp-partner.google.com\u003e\n" }, { "commit": "00e3fb94969bd4cebf428eef40f4fe9c28018fb7", "tree": "9352f203e97f52c31988e9328433e3e107769452", "parents": [ "4f2f477636be9bf7fe54068136f3c0a405c869af", "867fe8ec915303fabcc67b28576ddf36afc03b14" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Jan 20 15:31:42 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 20 15:31:42 2026 +0000" }, "message": "Merge \"refactor(cpus): export midr_match to a more global location\" into integration" }, { "commit": "867fe8ec915303fabcc67b28576ddf36afc03b14", "tree": "9352f203e97f52c31988e9328433e3e107769452", "parents": [ "4f2f477636be9bf7fe54068136f3c0a405c869af" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jan 20 11:13:44 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jan 20 11:14:42 2026 +0000" }, "message": "refactor(cpus): export midr_match to a more global location\n\nIt\u0027s a useful little helper that is horribly underused. Put it in common\ncode so that we can use it in future.\n\nChange-Id: I635c581644b07a6ca5ff68bb4fa475c4052da691\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "4f2f477636be9bf7fe54068136f3c0a405c869af", "tree": "9d0efddb702f5c0ef7a7876e111d824474877b7c", "parents": [ "040ab75ddc5d5b1e01bdb3b150a28986eaa47515", "785b7df2d5ed8e3eacbb6fa1a17c28b9a882126b" ], "author": { "name": "Manish V Badarkhe", "email": "manish.badarkhe@arm.com", "time": "Tue Jan 20 08:22:47 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 20 08:22:47 2026 +0000" }, "message": "Merge \"feat(rse): fix iovec parameter check in rse comms\" into integration" }, { "commit": "996d08b8b909250327284ee42cf218c0773ff233", "tree": "bd5ad1af16a45e65a56ddf26a11039899b087df5", "parents": [ "9dda4082afac4e87cbcf7ede6f9ef43961d1a960" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jan 13 11:58:12 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jan 19 10:50:58 2026 +0000" }, "message": "feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB\n\nBoth are now FEAT_STATE_CHECKED enabled so they can be now be used.\n\nChange-Id: I2485d583349e432014808a775ef57799eed4a596\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "9dda4082afac4e87cbcf7ede6f9ef43961d1a960", "tree": "42223c2e58b9e9163f106634e876023d55156261", "parents": [ "caf00e1b81f16be760b1270fee261306a2524de7" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jan 13 11:52:55 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jan 19 10:50:58 2026 +0000" }, "message": "feat(cpufeat): update FEAT_SB\u0027s FEAT_STATE_CHECKED status\n\nFEAT_SB is mostly FEAT_STATE_CHECKED enabled but that is not apparent\nfrom docs and code\u0027s check is sub-optimal. Update docs to make this\napparent and update code to have a proper FEAT_STATE_CHECKED fallback.\n\nAlso enable it for FVP so it\u0027s tested a bit more.\n\nChange-Id: I1374c4828b235ad16904f6c4ac9e39b9c2596a37\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "caf00e1b81f16be760b1270fee261306a2524de7", "tree": "8920de86450d3a6c062ceeebb9c22c943dac4395", "parents": [ "553c24c3ad1fd996b4ae873b09a325c1747990a8" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jul 08 10:07:03 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jan 19 10:50:58 2026 +0000" }, "message": "feat(cpufeat): advertise support for FEAT_RASv2\n\nFrom a PE architecture standpoint, FEAT_RASv2 only does three things:\n* adds the SCR_EL3.TWERR trap bit (active high). That defaults to 0\n unless RAS_TRAP_NS_ERR_REC_ACCESS overrides it but that\u0027s unused.\n* adds the read only ERXGSR_EL1 register which cannot be saved/restored.\n* changes the signalling of Uncontainable Instruction Aborts. When\n FEAT_RASv2 is present Uncontainable EAs cannot happen and instead\n SErrors will be signalled with more information.\n\nSo there isn\u0027t much to do and we can safely advertise FEAT_RASv2\nsupport.\n\nChange-Id: I07e29dbbd7fe824bed5a22ae22bd50eb16a0acd0\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "553c24c3ad1fd996b4ae873b09a325c1747990a8", "tree": "b7d68a1cb1c1e9d0997a8d154a95df98c17496f3", "parents": [ "869cac12df11d4af1f746b25ed42731b81b4a0ef" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jul 07 13:21:13 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jan 19 10:50:58 2026 +0000" }, "message": "feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again\n\nFEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.\nHowever, the ability to use it was removed with 970a4a8d8 by simply\nsaying it impacts execution at EL3. That\u0027s true, but FEAT_STATE_CHECKED\ncan still be allowed by being a bit clever about it.\n\nFirst, the remainder of common code can be converted to use the\nis_feat_ras_supported() helper instead of the `#if FEATURE` pattern.\nThere are no corner cases to consider there. The feature is either\npresent (and appropriate action must be taken) or the feature is not (so\nwe can skip RAS code).\n\nA conscious choice is taken to check the RAS code in synchronize_errors\ndespite it being in a hot path. Any fixed platform that seeks to be\nperformant should be setting features to 0 or 1. Then, the\nSCTLR_EL3.IESB bit is always set if ENABLE_FEAT_RAS !\u003d 0 since we expect\nFEAT_IESB to be present if FEAT_RAS is (despite the architecture not\nguaranteeing it). If FEAT_RAS isn\u0027t present then we don\u0027t particularly\ncare about the status of FEAT_IESB.\n\nSecond, platforms that don\u0027t set ENABLE_FEAT_RAS must continue to work.\nThis is true out of the box with the is_feat_xyz_supported() helpers, as\nthey make sure to fully disable code within them.\n\nThird, platforms that do set ENABLE_FEAT_RAS\u003d1 must continue to work.\nThis is also true out of the box and no logical change is undertaken in\ncommon code.\n\nFinally, ENABLE_FEAT_RAS is set to 2 on FVP. Having RAS implies that the\nwhole handling machinery will be built-in and registered as appropriate.\nHowever, when RAS is built-in but not present in hardware, these\nregistrations can still happen, they will only never be invoked at\nruntime.\n\nChange-Id: I949e648601dc0951ef9c2b217f34136b6ea4b3dc\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "785b7df2d5ed8e3eacbb6fa1a17c28b9a882126b", "tree": "2473127ceee20439a272e03e57115e6071148dc1", "parents": [ "8fd4c786594239de20669f062e416fe1a37ca59e" ], "author": { "name": "Martin Fonai", "email": "martin.fonai@arm.com", "time": "Thu Jan 15 14:38:31 2026 +0100" }, "committer": { "name": "Martin Fonai", "email": "martin.fonai@arm.com", "time": "Mon Jan 19 11:31:43 2026 +0100" }, "message": "feat(rse): fix iovec parameter check in rse comms\n\nAllow NULL pointers as in/outvec pointer, but only if the\ncorresponding length is 0, in which case it is not used.\nIntroduce check for outvec as well, where NULL pointer\nwould cause illegal dereferencing on evaluation of\nout_vec[0].base\n\nSigned-off-by: Martin Fonai \u003cmartin.fonai@arm.com\u003e\nChange-Id: Ie5ea11ed63d942a063a9cfed8333b553b96e9924\n" }, { "commit": "040ab75ddc5d5b1e01bdb3b150a28986eaa47515", "tree": "64d1a77c50339dbc9392989f3293d3cdc5320ac6", "parents": [ "96c0c13d8f7c471da9d6de89e6b9f5aac12674a8", "c9017cbc299a837b0f1c5912fa1beab33b87873e" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jan 19 10:14:23 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 19 10:14:23 2026 +0000" }, "message": "Merge \"feat(cpus): add support for Rosillo cpu\" into integration" }, { "commit": "96c0c13d8f7c471da9d6de89e6b9f5aac12674a8", "tree": "f95a8b360751d72bd02e459715b1fff0f458f5b1", "parents": [ "d62f795ccaa2a18e76fb6b4c387338c3b194e051", "2edb8b6d32caabc8b4ba2e47dcaed81818c0fbb2" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jan 19 10:11:57 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 19 10:11:57 2026 +0000" }, "message": "Merge \"fix(cpufeat): enable access to extended BRPs/WRPs\" into integration" }, { "commit": "d62f795ccaa2a18e76fb6b4c387338c3b194e051", "tree": "1c29b0658a58bef47b6311b429f40427c7971fb5", "parents": [ "2147ce91c27f7910d514b42767908cc7dc416065", "9718d0db921139854e617d1791c6949489c45430" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jan 19 10:09:14 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 19 10:09:14 2026 +0000" }, "message": "Merge changes I215a84bd,I83710d84 into integration\n\n* changes:\n perf(cpus): reduce the footprint of errata reporting\n refactor(cpus): make errata reporting more generic\n" }, { "commit": "2147ce91c27f7910d514b42767908cc7dc416065", "tree": "ba642260349f28984a623b34b7f8d3cd5cac21ff", "parents": [ "869cac12df11d4af1f746b25ed42731b81b4a0ef", "a4efd4289f53b5c3f477e72a421214045c5c719b" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jan 19 10:00:57 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 19 10:00:57 2026 +0000" }, "message": "Merge changes from topic \"upstream_ddr_reg_accesories\" into integration\n\n* changes:\n feat(s32g274ardb): add DDR register accessories\n feat(s32g274ardb): add DDR PHY mailbox support\n" }, { "commit": "c46f2d9882b497d40a9808fc2854fa5e2bf86b76", "tree": "de36e8eb79539adefb10c5e31b48615136761306", "parents": [ "869cac12df11d4af1f746b25ed42731b81b4a0ef" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jan 13 17:28:23 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jan 19 08:37:00 2026 +0000" }, "message": "fix(build): assign the ldflags-common variable before appending to it\n\nOtherwise the first value is lost, causing odd behaviours.\n\nChange-Id: I6df892bf8f706db71d0aa7e67f5076cc9583e477\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "c9017cbc299a837b0f1c5912fa1beab33b87873e", "tree": "ccccc07ab782fa56994bbf27cb1756ce88add963", "parents": [ "869cac12df11d4af1f746b25ed42731b81b4a0ef" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Jan 05 14:38:44 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Fri Jan 16 12:33:58 2026 -0600" }, "message": "feat(cpus): add support for Rosillo cpu\n\nAdd basic CPU library code to support Rosillo CPU\n\nChange-Id: I0e11e511511562297e4dccd2745842ebcfa2bff4\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "869cac12df11d4af1f746b25ed42731b81b4a0ef", "tree": "0c78a0caa2f0768f53184b911209a45789baa8cf", "parents": [ "ced274f3766f594740a296458c83a61cc86484bf", "989362581c6bd1b894ad943204ec97cbe81d12ee" ], "author": { "name": "Yann Gautier", "email": "yann.gautier@st.com", "time": "Thu Jan 15 15:38:24 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 15 15:38:24 2026 +0000" }, "message": "Merge \"refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform\" into integration" }, { "commit": "ced274f3766f594740a296458c83a61cc86484bf", "tree": "6a62a495f4fd81a0654feba323772536c74f3a73", "parents": [ "5c1015b3c7a884303a000240d0578286e5b319c1", "8df6a7c9effc17b7c6016ee399af9e18f49dc2ce" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 15 14:37:39 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 15 14:37:39 2026 +0000" }, "message": "Merge \"feat(el3-runtime): check the exception vector size\" into integration" }, { "commit": "8df6a7c9effc17b7c6016ee399af9e18f49dc2ce", "tree": "6a62a495f4fd81a0654feba323772536c74f3a73", "parents": [ "5c1015b3c7a884303a000240d0578286e5b319c1" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Wed Jan 07 11:43:59 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 15 14:37:32 2026 +0000" }, "message": "feat(el3-runtime): check the exception vector size\n\nCurrently, if the exception vector is too big it will fail with a\n\"Warning: repeat \u003c 0; .fill ignored\" error that is quite unclear. This\nonly happens when the vector entry is bigger than its allocated 128\nbytes so add an explicit check with a descriptive message to ease\ndebugging when this happens.\n\nChange-Id: I4f7acdcedab38bc96416dd0d0c6a8a60b7986e17\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "989362581c6bd1b894ad943204ec97cbe81d12ee", "tree": "8382b36087c3418cb58676587b7b66950dbdd615", "parents": [ "ea6625c639011747bf49ab2afc0ff4152320c4c3" ], "author": { "name": "Nhut Nguyen", "email": "nhut.nguyen.kc@renesas.com", "time": "Fri Dec 05 11:43:07 2025 +0700" }, "committer": { "name": "Nhut Nguyen", "email": "nhut.nguyen.kc@renesas.com", "time": "Thu Jan 15 09:37:45 2026 +0700" }, "message": "refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform\n\nRename console_rcar_ to console_renesas_ prefix for SCIF-based console\ndriver to make it reusable by other Renesas platforms.\n\nDue to the above renaming, function console_renesas_register is duplicated\nin both scif.h and console.h, so it should be removed from scif.h\n\nChange-Id: I42b44d1786578f7ed8db34e7da421836ea60b5e2\nSigned-off-by: Nhut Nguyen \u003cnhut.nguyen.kc@renesas.com\u003e\n" }, { "commit": "5c1015b3c7a884303a000240d0578286e5b319c1", "tree": "05128b28bf67a8483729431fadad0d477dc75c84", "parents": [ "e8e8fc56c53b5735104d9b27d8974568c68cafdb", "e63e5794361b62a8c83514217da5b04f06990a7c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Jan 14 16:57:05 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 14 16:57:05 2026 +0000" }, "message": "Merge \"fix(context-mgmt): actually clear MDCR_EL3 bits\" into integration" }, { "commit": "e8e8fc56c53b5735104d9b27d8974568c68cafdb", "tree": "3fcd4ca83c465fe1b5eb618e20755e62fd038e7e", "parents": [ "10d33abec01d820ad749fdc61afc8dbc6b702b05", "287ad959f3821901afbb7a825470e6d05c401a8c" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Jan 14 16:55:57 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 14 16:55:57 2026 +0000" }, "message": "Merge changes from topic \"bk/simpler_panic\" into integration\n\n* changes:\n refactor(aarch64): remove crash reporting\u0027s dependency on cpu_data\n fix(el3-runtime): remove lower_el_panic()\n" }, { "commit": "10d33abec01d820ad749fdc61afc8dbc6b702b05", "tree": "5bdf84639e13a3ff476620a9d0e4df8897e921cb", "parents": [ "ebc89e7546d4be3e7f867bdc345c5cfdb521796e", "96f40c7b2b843ff830d52e371a8ef72d3497ead3" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Wed Jan 14 16:55:13 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 14 16:55:13 2026 +0000" }, "message": "Merge changes from topic \"at/ras-rdaspen\" into integration\n\n* changes:\n feat(rdaspen/ras): dump the CPER buffer contents\n feat(rdaspen/ras): generate CPER at TF-A EL3\n feat(rdaspen/ras): add DT buffer and IRQ setup\n feat(rdaspen): event handler for CPU RAS\n feat(rdaspen/ras): intr RAS handling for PC CPU\n" }, { "commit": "ebc89e7546d4be3e7f867bdc345c5cfdb521796e", "tree": "fef2e79a905628936c4ef880b9b4be9fa55e35e2", "parents": [ "8fd4c786594239de20669f062e416fe1a37ca59e", "d2d6928641bacfa2370a9bb38cdddad229d99ad6" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Wed Jan 14 15:31:20 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Wed Jan 14 15:31:20 2026 +0000" }, "message": "Merge \"feat(rk3588): report actual measured PVTPLL clocks\" into integration" }, { "commit": "7cc8f16593faa7c74284547fb0b9917ddd71fa84", "tree": "d754383faa98699d3d7ce40a29df2d43324404b1", "parents": [ "8fd4c786594239de20669f062e416fe1a37ca59e" ], "author": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Thu Oct 16 11:46:48 2025 +0100" }, "committer": { "name": "Arunachalam Ganapathy", "email": "arunachalam.ganapathy@arm.com", "time": "Wed Jan 14 10:07:34 2026 +0000" }, "message": "fix(arm): build fails on RESET_TO_BL2\u003d1 and ARM_FW_CONFIG_LOAD_ENABLE\u003d1\n\nUse ARM_FW_CONFIG_BASE and ARM_FW_CONFIG_MAX_SIZE instead of platform\nmacros PLAT_FW_CONFIG_BASE and PLAT_FW_CONFIG_MAX_SIZE when\nRESET_TO_BL2 and ARM_FW_CONFIG_LOAD_ENABLE are set to 1.\n\nSigned-off-by: Arunachalam Ganapathy \u003carunachalam.ganapathy@arm.com\u003e\nChange-Id: I0848852250eba5a3328e25cbea4fff413f344327\n" }, { "commit": "96f40c7b2b843ff830d52e371a8ef72d3497ead3", "tree": "5d8497363cb0b86296e930ae2edd63f8aa766503", "parents": [ "cbad38ff58980c4abd7c8f603f24870435883ac4" ], "author": { "name": "Sanjana Virupakshagouda", "email": "sanjana.virupakshagouda@arm.com", "time": "Tue Nov 11 15:23:36 2025 +0530" }, "committer": { "name": "Ahmed Tiba", "email": "ahmed.tiba@arm.com", "time": "Tue Jan 13 16:47:40 2026 +0000" }, "message": "feat(rdaspen/ras): dump the CPER buffer contents\n\nPrint the contents of the buffer to verify the fields set.\n\nChange-Id: Ibb0683c99eed17d40ed5ce410fe19fab7e6bb9e6\nSigned-off-by: Sanjana Virupakshagouda \u003csanjana.virupakshagouda@arm.com\u003e\nSigned-off-by: Ahmed Tiba \u003cahmed.tiba@arm.com\u003e\n" }, { "commit": "cbad38ff58980c4abd7c8f603f24870435883ac4", "tree": "3046f59b41bc9f2131e8332b77fdb6d8e27617d2", "parents": [ "761d0c72c32bfd45d2a2bedbf92e5a0e629729d6" ], "author": { "name": "Sanjana Virupakshagouda", "email": "sanjana.virupakshagouda@arm.com", "time": "Fri Nov 07 12:37:50 2025 +0530" }, "committer": { "name": "Ahmed Tiba", "email": "ahmed.tiba@arm.com", "time": "Tue Jan 13 16:47:40 2026 +0000" }, "message": "feat(rdaspen/ras): generate CPER at TF-A EL3\n\nGenerate CPER buffer at TF-A EL3, that emits the error data,\nwhen there is a CPU RAS error in the system.\n\nThe CPER record consists of:\nESB Header\nESB Data Entry\nCPER CPU Error Section\n- Arm Processor Error Record\n- Arm Processor Error Information\n- Arm Processor Context Information\n\nChange-Id: I7e9703a69edec15cbb6f0522333700bb8d7007bf\nSigned-off-by: Sanjana Virupakshagouda \u003csanjana.virupakshagouda@arm.com\u003e\nSigned-off-by: Ahmed Tiba \u003cahmed.tiba@arm.com\u003e\n" }, { "commit": "761d0c72c32bfd45d2a2bedbf92e5a0e629729d6", "tree": "bd75a88b018a441a25d58945e90d46962f932ccd", "parents": [ "0702fe72cf4cc8ace77530f484456b2a7d450919" ], "author": { "name": "Sanjana Virupakshagouda", "email": "sanjana.virupakshagouda@arm.com", "time": "Wed Oct 22 09:56:49 2025 +0530" }, "committer": { "name": "Ahmed Tiba", "email": "ahmed.tiba@arm.com", "time": "Tue Jan 13 16:47:40 2026 +0000" }, "message": "feat(rdaspen/ras): add DT buffer and IRQ setup\n\nAdded node to map reserved memory for CPER.\nInterrupt set from TF-A for RAS error notification.\n\nChange-Id: Id7e296772275cdf76c81d8d62294b0bce94bbf57\nSigned-off-by: Sanjana Virupakshagouda \u003csanjana.virupakshagouda@arm.com\u003e\n" }, { "commit": "0702fe72cf4cc8ace77530f484456b2a7d450919", "tree": "728570aa99ef4d5262178caf3405a1e51df7b2d3", "parents": [ "3f3b9ec69730d5bc02aab7da2cb7cc0f8a30c130" ], "author": { "name": "Ahmed Azeem", "email": "ahmed.azeem@arm.com", "time": "Sat May 24 15:31:36 2025 +0100" }, "committer": { "name": "Ahmed Tiba", "email": "ahmed.tiba@arm.com", "time": "Tue Jan 13 16:47:40 2026 +0000" }, "message": "feat(rdaspen): event handler for CPU RAS\n\nThis patch introduces assembly helpers for cleaning CPU\nRAS, and introduces a way to deassert FAULT IRQ generated\nfrom CE injection.\n\nThis also enables all inband errors to be handled on AP according\nto a CPU RAS event handler:\n\n- Skips spurious entries – returns early when\n `ERXSTATUS.{V|CE}` is already clear, disposing of queued phantom\n interrupts.\n\n- Clears the error record – rewrites `ERXSTATUS_EL1`, zeros\n `ERXMISC0`, `PFG_CTL`, and `PFG_CDN`, then logs the post clear state\n for firmware trace.\n\nInband errors only consist of:\n- Corrected Errors\n- Deferred Errors\n\n- Change the RAS CPU intr handler logs from VERBOSE to WARN.\n\nChange-Id: I7eb8fecb42095551f51c9d1c5752775f1b577970\nSigned-off-by: Ahmed Azeem \u003cahmed.azeem@arm.com\u003e\nSigned-off-by: Ahmed Tiba \u003cahmed.tiba@arm.com\u003e\n" }, { "commit": "3f3b9ec69730d5bc02aab7da2cb7cc0f8a30c130", "tree": "f0ed8a08f285458005d36d2009e6f72676461031", "parents": [ "8fd4c786594239de20669f062e416fe1a37ca59e" ], "author": { "name": "Ahmed Azeem", "email": "ahmed.azeem@arm.com", "time": "Wed May 07 17:28:36 2025 +0100" }, "committer": { "name": "Ahmed Tiba", "email": "ahmed.tiba@arm.com", "time": "Tue Jan 13 16:47:40 2026 +0000" }, "message": "feat(rdaspen/ras): intr RAS handling for PC CPU\n\nThis introduces and enables the RAS framework and enables\nthe RAS for CPU handling.\n\nThis commit ensures that RAS settings are initialized on\nall CPU cores during the firmware boot stage. Previously,\nthe initialization for RAS processing was only done on\nthe primary CPU core.\n\nThis also introduces a custom bl31_platform_setup to\nallow RAS specific intialisations.\n\nChange-Id: Ia3258aed63b8994c53ec8cc49bd27d0d907e218e\nSigned-off-by: Ahmed Azeem \u003cahmed.azeem@arm.com\u003e\nSigned-off-by: Ahmed Tiba \u003cahmed.tiba@arm.com\u003e\n" }, { "commit": "8fd4c786594239de20669f062e416fe1a37ca59e", "tree": "5c4a77ea76cad04d1ea158a7a43c03f38a46ee74", "parents": [ "a760277d83a16575c2feaf5b2368f40d4bc720c7", "71b6bf71497dc546267ba19c5a37141e4f69a596" ], "author": { "name": "Mark Dykes", "email": "mark.dykes@arm.com", "time": "Tue Jan 13 16:29:10 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 13 16:29:10 2026 +0000" }, "message": "Merge \"fix(rcar3): disable stack protector for functions in SRAM\" into integration" }, { "commit": "5eceb40373a146f668115cb3be8c50176676c404", "tree": "9f699f322861efd00e0baebd3220a4f2ba85be1a", "parents": [ "f6d3a40d6753fbf4a33993d77efda86f467459d7" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jan 12 18:04:56 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jan 13 16:14:09 2026 +0000" }, "message": "feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION\n\nNow that the 2024 features have been analysed, bump those that don\u0027t\nneed any specific EL3 support so that FEATURE_DETECTION doesn\u0027t complain\nwhen it encounters them.\n\nChange-Id: I3a2243d021a9a5385d14b3c1d569142e34145e51\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "f6d3a40d6753fbf4a33993d77efda86f467459d7", "tree": "d66f2e8a4daf39e84f2fcd6ac0ee571d18b3a582", "parents": [ "b4f47d8418cbf469c2222ef281dc41ed5fe1b40b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jan 12 16:40:02 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jan 13 16:14:09 2026 +0000" }, "message": "docs(cpufeat): add analysis of 2024 features\n\nHaving gone through the list, write down the features that require no\nEL3 enablement and leave out the ones that do.\n\nMinor revisions of major features (eg FEAT_SPE) that introduce a\nmandatory feature are counted as independent features.\n\nChange-Id: Ifeb88c8fb7a754eaa0df2edaa935090cbdfa35ad\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "b4f47d8418cbf469c2222ef281dc41ed5fe1b40b", "tree": "76b67fa45f947a0048a50cb45d534d50896ff4e2", "parents": [ "4fed6933825b928aecd6d90453fc444bd1bfdda3" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Jan 12 16:35:13 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Tue Jan 13 16:14:09 2026 +0000" }, "message": "fix(cpufeat): add FEAT_SPE to FEATURE_DETECTION\n\nDocumentation in docs/architecture_features.rst suggests we\u0027re okay with\nanything up to FEAT_SPEv1p3 but FEAT_DETECT is unaware of it. Add it to\nthe list.\n\nChange-Id: I8ac773361fb8d18b850da1e45fdb6a54cfe65063\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "a760277d83a16575c2feaf5b2368f40d4bc720c7", "tree": "f858821fa0a2c38f80a5bee495f546b21c0c44bd", "parents": [ "4fed6933825b928aecd6d90453fc444bd1bfdda3", "d0650203103da8fe69f0900266d2b08f67b02594" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Jan 13 16:04:57 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 13 16:04:57 2026 +0000" }, "message": "Merge \"fix(debug): add debug log build option\" into integration" }, { "commit": "4fed6933825b928aecd6d90453fc444bd1bfdda3", "tree": "4bd3c2766ca45d46d4ff9d64d0cd834634aa9351", "parents": [ "585088ebc2d9da1303a2dfddba4d05b1d6d810f8", "3247828c3d6c43c2e591b07cb7cf0091c3a84189" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Jan 13 15:49:11 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 13 15:49:11 2026 +0000" }, "message": "Merge \"fix(morello): avoid capability tag fault on data access\" into integration" }, { "commit": "585088ebc2d9da1303a2dfddba4d05b1d6d810f8", "tree": "e7e64834ade71633c3a1a5a0208e272a5c03f8d4", "parents": [ "6d1d3cc39a118899395c995f4abd9533825cffaf", "6a548c34675da49dfe59ee93b62af324e1a73157" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Tue Jan 13 15:49:02 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 13 15:49:02 2026 +0000" }, "message": "Merge changes from topic \"morello_upstream\" into integration\n\n* changes:\n feat(morello): add capability load/store/track support to MMU\n feat(morello): add Morello capability enablement changes\n" }, { "commit": "6d1d3cc39a118899395c995f4abd9533825cffaf", "tree": "cdb6e788bf46ffb216aa1998ec7e3cd89dcf6456", "parents": [ "ea6625c639011747bf49ab2afc0ff4152320c4c3", "e3ace29cff630534082c0d0f4c80c1c1a44fbb3f" ], "author": { "name": "Bipin Ravi", "email": "bipin.ravi@arm.com", "time": "Tue Jan 13 15:27:57 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Tue Jan 13 15:27:57 2026 +0000" }, "message": "Merge \"fix(docs): update sme disconnect on power down\" into integration" }, { "commit": "d0650203103da8fe69f0900266d2b08f67b02594", "tree": "624aa1359ed9446ff1ff7f80969ef06c08230ebb", "parents": [ "ea6625c639011747bf49ab2afc0ff4152320c4c3" ], "author": { "name": "Jaiprakash Singh", "email": "jaiprakashs@marvell.com", "time": "Fri Dec 12 01:50:47 2025 -0800" }, "committer": { "name": "Jaiprakash Singh", "email": "jaiprakashs@marvell.com", "time": "Tue Jan 13 02:28:48 2026 -0800" }, "message": "fix(debug): add debug log build option\n\nWhen log level set to verbose, xlat prints\nalot of translation table debug logs.These\ndetail logs keeps on printing for minutes\nand increase boot time. Also, not all users\nmight be interested in the xlat detail\nlogs when verbose is on.\n\nLOG_DEBUG is added to print xlat detail\nlogs only when someone intentionally\nenables logging.\n\nChange-Id: I3308b49779a692bdce87fb6929c88fdcb713e628\nSigned-off-by: Jaiprakash Singh \u003cjaiprakashs@marvell.com\u003e\n" }, { "commit": "71b6bf71497dc546267ba19c5a37141e4f69a596", "tree": "6dfdd9ca78b491d62ffa4214a6480a7c2abf1cd4", "parents": [ "ea6625c639011747bf49ab2afc0ff4152320c4c3" ], "author": { "name": "Toshiyuki Ogasahara", "email": "toshiyuki.ogasahara.bo@hitachi.com", "time": "Mon Jul 12 19:01:36 2021 +0900" }, "committer": { "name": "Marex", "email": "marek.vasut+renesas@mailbox.org", "time": "Tue Jan 13 09:44:53 2026 +0000" }, "message": "fix(rcar3): disable stack protector for functions in SRAM\n\nDisable the BL31 stack protector for all functions placed in SRAM,\nbecause the canary value in __stack_chk_guard in DRAM can not be\nread when running Suspend To RAM code from SRAM. The SSP functions\nin DRAM can also not be called from that code. Make sure the code\nin SRAM is self-contained by marking rcar_pwrc_go_suspend_to_ram()\nas noinline. To assure the stack protector is active otherwise,\nuse no_stack_protector function attribute for the select functions\nwhich are placed in SRAM.\n\nChange-Id: Idc43e70fd5217ea130a48c46f227a37c568dc8bd\nFixes: cfa466ab733f (\"feat(rcar3): enable the stack protection\")\nSigned-off-by: Toshiyuki Ogasahara \u003ctoshiyuki.ogasahara.bo@hitachi.com\u003e\nSigned-off-by: Yoshifumi Hosoya \u003cyoshifumi.hosoya.wj@renesas.com\u003e\nSigned-off-by: Dien Pham \u003cdien.pham.ry@renesas.com\u003e\nSigned-off-by: Hieu Nguyen \u003chieu.nguyen.dn@renesas.com\u003e\nSigned-off-by: Marek Vasut \u003cmarek.vasut+renesas@mailbox.org\u003e\n" }, { "commit": "3247828c3d6c43c2e591b07cb7cf0091c3a84189", "tree": "5abeec30be73220de1585ef7317fb6a72f37841a", "parents": [ "6a548c34675da49dfe59ee93b62af324e1a73157" ], "author": { "name": "Manoj Kumar", "email": "manoj.kumar3@arm.com", "time": "Tue Aug 02 15:14:20 2022 +0100" }, "committer": { "name": "Varshit Pandya", "email": "varshit.pandya@arm.com", "time": "Tue Jan 13 08:05:39 2026 +0000" }, "message": "fix(morello): avoid capability tag fault on data access\n\nTF-A runtime service at EL3 switches the stack pointer from SP_EL3\nto SP_EL0. This creates a capability tag fault when the DDC_EL0 is\nzeroed out (purecap user space) as any data accesses computes\ntag/permission with DDC_EL0 value when SpSel is 0 and when EL3 is\nin hybrid mode.\n\nAs a workaround, this patch creates a per cpu context variable\nto store DDC_EL0 value so that when EL3 runtime is entered DDC_EL0\nis saved on to stack. DDC_EL3 is then copied into DDC_EL0 after\nswitching SP to SP_EL0. Once the runtime finishes, during el3_exit,\nthe saved DDC_EL0 is restored from stack.\n\nSigned-off-by: Selvarasu Ganesan \u003cselvarasu.ganesan@arm.com\u003e\nSigned-off-by: Manoj Kumar \u003cmanoj.kumar3@arm.com\u003e\nSigned-off-by: Varshit Pandya \u003cvarshit.pandya@arm.com\u003e\nChange-Id: I4e4010f0e20913cb4e35b58fb49a177bdf26feb1\n" }, { "commit": "6a548c34675da49dfe59ee93b62af324e1a73157", "tree": "f906cffb66b92885d5bcc9cd8359614acae9dd92", "parents": [ "27bc1386f00a2a5089e27ff00f97b41821dc08ed" ], "author": { "name": "Manoj Kumar", "email": "manoj.kumar3@arm.com", "time": "Tue Aug 02 15:04:05 2022 +0100" }, "committer": { "name": "Varshit Pandya", "email": "varshit.pandya@arm.com", "time": "Tue Jan 13 08:02:18 2026 +0000" }, "message": "feat(morello): add capability load/store/track support to MMU\n\nMorello architecture adds additional bits to TCR_EL3 and uses the\nHWU bits of page/block descriptors to provision permission for\nloading, storing and tracking of valid capability tags.\n\nThis patch reserves bit 31 of the existing translation table\nattribute field which can be used by the user to enable capability\nload/store/track permission for a given memory region.\n\nThis patch also enables this permission for BL31 region.\n\nSigned-off-by: Manoj Kumar \u003cmanoj.kumar3@arm.com\u003e\nSigned-off-by: Varshit Pandya \u003cvarshit.pandya@arm.com\u003e\nChange-Id: I1939c70aac3585969d74b0956529681e840d6f63\n" }, { "commit": "27bc1386f00a2a5089e27ff00f97b41821dc08ed", "tree": "04866b92c6ba02ea256527e4dd1776ffc06683e7", "parents": [ "ea6625c639011747bf49ab2afc0ff4152320c4c3" ], "author": { "name": "Manoj Kumar", "email": "manoj.kumar3@arm.com", "time": "Fri Oct 02 17:11:15 2020 +0100" }, "committer": { "name": "Varshit Pandya", "email": "varshit.pandya@arm.com", "time": "Tue Jan 13 08:02:15 2026 +0000" }, "message": "feat(morello): add Morello capability enablement changes\n\nThis patch adds a build macro ENABLE_FEAT_MORELLO which when set will\ncompile BL31 firmware with changes required to boot capability\naware software.\n\nIt also adds helper function in c and assmbly to check if morello\nhardware is present and if morello capability is enabled or not.\n\nCE field, bits [23:20] in ID_AA64PFR1_EL1 defines whether morello\narchitecture is present or not, 0b0000 indicates that it is absent\nand 0b0001 indicates that it is present. While whether capabilities\nare enabled or not is decided at runtime with ENABLE_FEAT_MORELLO build\noption.\n\nReference: https://developer.arm.com/documentation/ddi0606/latest/\n\nSigned-off-by: Manoj Kumar \u003cmanoj.kumar3@arm.com\u003e\nSigned-off-by: Varshit Pandya \u003cvarshit.pandya@arm.com\u003e\nChange-Id: Ib16877acbfcb72c4bd8c08e97e44edc0a3e46089\n" }, { "commit": "2edb8b6d32caabc8b4ba2e47dcaed81818c0fbb2", "tree": "87ff60473545cea39487e1e4ec1003c5573e0a79", "parents": [ "e3ace29cff630534082c0d0f4c80c1c1a44fbb3f" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Jan 12 12:48:51 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Jan 12 12:59:02 2026 -0600" }, "message": "fix(cpufeat): enable access to extended BRPs/WRPs\n\nAccess to Extended Breakpoints(BRPs) and Watchpoints(WRPs) are enabled\nthrough EBWE bit and this available from DebugV8P9. So enable access to\nmode select register default from lower EL\u0027s.\n\nThough this bit RES0 when we have less than 16 BRPs/WRPs the Mode select\nregister is also RAZ/WI. So having EBWE write by default is harmless.\nAnd will avoid trap to EL3 when enable access to bank selection when we\nhave more than 16 BRPs/WRPs.\n\nChange-Id: Ib308be758c0beedde05a5558b0d24a161b79273a\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "e3ace29cff630534082c0d0f4c80c1c1a44fbb3f", "tree": "cdb6e788bf46ffb216aa1998ec7e3cd89dcf6456", "parents": [ "ea6625c639011747bf49ab2afc0ff4152320c4c3" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 08 17:17:07 2026 -0600" }, "committer": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Jan 12 12:59:02 2026 -0600" }, "message": "fix(docs): update sme disconnect on power down\n\nWith `ERRATA_SME_POWER_DOWN` enabled we disconnect SME from\ncore to power down the core correctly, we actually don\u0027t disable sme.\n\nChange-Id: I42b99bd5ef125868f55a2a3ef96c0ac1b054f509\nSigned-off-by: Govindraj Raja \u003cgovindraj.raja@arm.com\u003e\n" }, { "commit": "ea6625c639011747bf49ab2afc0ff4152320c4c3", "tree": "47210b36bf4b0c4cf463d86ace2937b39828d01b", "parents": [ "aaec8b1cb5055512e3b2dd02cc9dca12e4e7609d", "8cd9c18bfd5a5ef2a399506d76c592721a98626f" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Mon Jan 12 18:37:37 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 12 18:37:37 2026 +0000" }, "message": "Merge changes from topic \"bk/amu_private\" into integration\n\n* changes:\n fix(cpufeat): prevent FEAT_AMU counters 2 and 3 from counting across worlds\n fix(cpufeat): disable FEAT_AMU counters on context restore\n feat(per-cpu): migrate AArch32 amu_ctx to per-cpu framework\n" }, { "commit": "aaec8b1cb5055512e3b2dd02cc9dca12e4e7609d", "tree": "7638aeabc4770bbde4538477ccc2366910b53cdb", "parents": [ "90fe41595838a36e1d062f96d1f9bd25bb55a539", "1df0bb505644bb00d2e700e4baeea2c1ab730de4" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jan 12 16:29:56 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 12 16:29:56 2026 +0000" }, "message": "Merge \"fix(cpus): enable Neoverse-V2 external LLC support\" into integration" }, { "commit": "1df0bb505644bb00d2e700e4baeea2c1ab730de4", "tree": "7638aeabc4770bbde4538477ccc2366910b53cdb", "parents": [ "90fe41595838a36e1d062f96d1f9bd25bb55a539" ], "author": { "name": "Jaiprakash Singh", "email": "jaiprakashs@marvell.com", "time": "Thu Dec 11 23:17:24 2025 -0800" }, "committer": { "name": "Jaiprakash Singh", "email": "jaiprakashs@marvell.com", "time": "Mon Jan 12 16:29:45 2026 +0000" }, "message": "fix(cpus): enable Neoverse-V2 external LLC support\n\nChange-Id: I9582c7405db6862e77db240822e241d4082966f2\nSigned-off-by: Jaiprakash Singh \u003cjaiprakashs@marvell.com\u003e\n" }, { "commit": "90fe41595838a36e1d062f96d1f9bd25bb55a539", "tree": "f9198408d21243f3bb836b5f8e8361a035ab8331", "parents": [ "f22cc37970f9471e67ac38026419b6764486cd40", "4a6b037d87199ea63602be38e41272ab0d00172f" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Mon Jan 12 15:55:39 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Mon Jan 12 15:55:39 2026 +0000" }, "message": "Merge changes Ia7a1c37b,Ia933c505 into integration\n\n* changes:\n feat(rcar): fold console_rcar_* functions into rcar_printf.c\n feat(rcar): rewrite SCIF driver from assembler to C\n" }, { "commit": "4a6b037d87199ea63602be38e41272ab0d00172f", "tree": "f9198408d21243f3bb836b5f8e8361a035ab8331", "parents": [ "656a8564ec06a4f737c2eeb9fd6e580e8f002c14" ], "author": { "name": "Marek Vasut", "email": "marek.vasut+renesas@mailbox.org", "time": "Tue Jan 06 23:13:08 2026 +0100" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@mailbox.org", "time": "Sat Jan 10 03:08:34 2026 +0100" }, "message": "feat(rcar): fold console_rcar_* functions into rcar_printf.c\n\nThe three console_rcar_{init,putc,flush}() no-op functions can\neasily be C functions, they do not need assembler wrappers. Move\nthe functions into rcar_printf.c which is part of the custom\nR-Car Gen3 memory logging console. Remove rcar_printf.c from\nBL2 builds, as it is not useful there. Rename rcar_set_log_data()\nto console_rcar_putc() and update its signature, it is no longer\nnecessary to have such a wrapper around C function.\n\nSigned-off-by: Marek Vasut \u003cmarek.vasut+renesas@mailbox.org\u003e\nChange-Id: Ia7a1c37b2151f6217cde70ffd2b367643d3184e4\n" }, { "commit": "656a8564ec06a4f737c2eeb9fd6e580e8f002c14", "tree": "0e9d606533cea44e23769b5ffa4cbbd56ac396e2", "parents": [ "f22cc37970f9471e67ac38026419b6764486cd40" ], "author": { "name": "Marek Vasut", "email": "marek.vasut+renesas@mailbox.org", "time": "Tue Jan 06 21:45:20 2026 +0100" }, "committer": { "name": "Marek Vasut", "email": "marek.vasut+renesas@mailbox.org", "time": "Sat Jan 10 03:08:32 2026 +0100" }, "message": "feat(rcar): rewrite SCIF driver from assembler to C\n\nRewrite the SCIF driver from difficult to read assembler to plain C.\nUse scif-common.c which contains putc() and flush() helper functions\nto avoid duplication, so only fill in the initialization code. Drop\nsupport for external clock, which is unused. Clean up macros and drop\nones which are not referenced.\n\nSigned-off-by: Marek Vasut \u003cmarek.vasut+renesas@mailbox.org\u003e\nChange-Id: Ia933c505c33e133e45448c82776a17629f3df1eb\n" }, { "commit": "f22cc37970f9471e67ac38026419b6764486cd40", "tree": "e51539a461ebbb2567e428d6fb97499d41b0cc81", "parents": [ "048cb1dd5ddd487561b4b5ac89b8f795d6115da7", "75ecfa7895e4ca6e7ba6694e5cb8abfab619e675" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Fri Jan 09 15:51:16 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Fri Jan 09 15:51:16 2026 +0000" }, "message": "Merge \"fix(rdaspen): dts: make cache nodes DT spec compliant\" into integration" }, { "commit": "287ad959f3821901afbb7a825470e6d05c401a8c", "tree": "00d116450f7d047e7724b94053fc818a8ee18632", "parents": [ "574db8ec86c88af5e0d132ae171cf9e0599f990b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Mon Aug 11 16:03:30 2025 +0100" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Jan 09 15:44:00 2026 +0000" }, "message": "refactor(aarch64): remove crash reporting\u0027s dependency on cpu_data\n\nCrash reporting is useful as early as possible, even before most of the\nruntime has been set up. This means that all of its dependencies,\ncurrently only cpu_data, must be set up as early as possible too. This\ncan be constraining as fiddling with the general EL3 runtime from the\nearly entrypoint is very difficult. So remove the cpu_data dependency.\nFurther benefits are that crash reporting will work even earlier (during\ncpu reset functions!) and also in other BLs.\n\nChange-Id: I92bb6b3921c6dec10560f8341b3bca5cdacfb492\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "574db8ec86c88af5e0d132ae171cf9e0599f990b", "tree": "8d61f3671b6977064dddc954978bf9dc2a73e66d", "parents": [ "048cb1dd5ddd487561b4b5ac89b8f795d6115da7" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Dec 19 14:50:07 2025 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Fri Jan 09 15:42:50 2026 +0000" }, "message": "fix(el3-runtime): remove lower_el_panic()\n\nA panic at EL3 is bad news and should never happen. What caused it isn\u0027t\nexactly relevant or possible to figure out without manual debugging\n(surely there wouldn\u0027t have been a panic if not). A misbehaving lower EL\nshould never be able to cause problems for a higher EL and since EL3 is\nin control of all lower ELs a panic at EL3 means that there is a\nproblem with EL3.\n\nThis patch removes lower_el panic and replaces it with a simple panic\nfor simplicity. There is a slight loss of information when an AArch32\nlower EL has one of its instructions trapped by EL3. An explicit error\nmessage is added to preserve this information.\n\nChange-Id: Iefd20eb43d69cbcf6d66ed5cc894c4e0255782e3\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" }, { "commit": "048cb1dd5ddd487561b4b5ac89b8f795d6115da7", "tree": "3e0d9521a81aeffc318ee39b8c078595ef5768ef", "parents": [ "dee3312e6c62a078c3204bf715248dfdf7288906", "ada9e227e90f78dfe36ffe924faba3747a988745" ], "author": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 08 16:31:44 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 08 16:31:44 2026 +0000" }, "message": "Merge changes from topic \"xlnx_fix_misra_opteed\" into integration\n\n* changes:\n fix(optee): initialize the structure\n fix(optee): add missing curly braces\n fix(optee): add parenthesis for macro expressions\n fix(optee): move function to conditional block\n fix(optee): add boolean type for expressions\n fix(optee): evaluate condition for boolean\n fix(optee): typecast operands to match data type\n fix(el3-runtime): resolve essential-type mismatch\n" }, { "commit": "ada9e227e90f78dfe36ffe924faba3747a988745", "tree": "3e0d9521a81aeffc318ee39b8c078595ef5768ef", "parents": [ "6c61ed4d97782060d08539fcad28845dcd46cb0c" ], "author": { "name": "Taticharla Venkata Sai", "email": "venkatasai.taticharla@amd.com", "time": "Tue Aug 12 14:57:02 2025 +0530" }, "committer": { "name": "Venkata Sai Taticharla", "email": "venkatasai.taticharla@amd.com", "time": "Thu Jan 08 16:31:27 2026 +0000" }, "message": "fix(optee): initialize the structure\n\nThis corrects the MISRA violation C2012-9.1:\nInitialize the structure with memset to ensures the structure\ncontains predictable zero values before being passed to functions,\npreventing potential undefined behavior from uninitialized\nautomatic storage.\n\nChange-Id: Ib89b45b8aeefa211afacc77f948a5888815f9e68\nSigned-off-by: Taticharla Venkata Sai \u003cvenkatasai.taticharla@amd.com\u003e\n" }, { "commit": "6c61ed4d97782060d08539fcad28845dcd46cb0c", "tree": "201a2fe6260a804565db6efd0d9b415f16561c68", "parents": [ "c9535e669ef4e494b7afc612c8a32706ab3ebd0f" ], "author": { "name": "Taticharla Venkata Sai", "email": "venkatasai.taticharla@amd.com", "time": "Tue Sep 09 17:17:55 2025 +0530" }, "committer": { "name": "Venkata Sai Taticharla", "email": "venkatasai.taticharla@amd.com", "time": "Thu Jan 08 16:31:27 2026 +0000" }, "message": "fix(optee): add missing curly braces\n\nThis corrects the MISRA violation C2012-15.6:\nThe body of an iteration-statement or a selection-statement shall\nbe a compound-statement. Enclosed statement body within the curly\nbraces.\n\nChange-Id: Ic8523f1d6ffa367c1ea3753de367a9c88008b55d\nSigned-off-by: Taticharla Venkata Sai \u003cvenkatasai.taticharla@amd.com\u003e\n" }, { "commit": "c9535e669ef4e494b7afc612c8a32706ab3ebd0f", "tree": "833cdc201ebbc4092b27f7ef6061d63db43c6427", "parents": [ "18f8d11e5489ed140917007294ae681265150c7d" ], "author": { "name": "Taticharla Venkata Sai", "email": "venkatasai.taticharla@amd.com", "time": "Wed Jul 23 10:10:41 2025 +0000" }, "committer": { "name": "Venkata Sai Taticharla", "email": "venkatasai.taticharla@amd.com", "time": "Thu Jan 08 16:31:27 2026 +0000" }, "message": "fix(optee): add parenthesis for macro expressions\n\nThis corrects MISRA violation C2012‑20.7:\nmacro parameters used within expressions\nwere not enclosed in parentheses, risking\nincorrect operator precedence after expansion.\n\nThe fix wraps all macro parameters in expressions\nwith parentheses to ensure intended evaluation\norder and compliance with the rule.\n\nChange-Id: Iaf5626afab2d8d8d945caf96798e0a8b33b32e53\nSigned-off-by: Taticharla Venkata Sai \u003cvenkatasai.taticharla@amd.com\u003e\n" }, { "commit": "18f8d11e5489ed140917007294ae681265150c7d", "tree": "f74423ad8d1361a6320defd3296920070eedb5cd", "parents": [ "bf7901cd6dd76a0d73c581ad7a788225590ba699" ], "author": { "name": "Taticharla Venkata Sai", "email": "venkatasai.taticharla@amd.com", "time": "Mon Jul 21 15:06:20 2025 +0530" }, "committer": { "name": "Venkata Sai Taticharla", "email": "venkatasai.taticharla@amd.com", "time": "Thu Jan 08 16:31:27 2026 +0000" }, "message": "fix(optee): move function to conditional block\n\nThis corrects the MISRA violation C2012-8.4:\nA compatible declaration shall be visible when an object or\nfunction with external linkage is defined.\n\nMoving the function definition to match its usage scope.\nThe function is only called within a conditional compilation\nblock, so it should be defined within the same conditional scope.\n\nChange-Id: I51071c9bb18591a3017e9ae4a2de1d7fca37de16\nSigned-off-by: Taticharla Venkata Sai \u003cvenkatasai.taticharla@amd.com\u003e\n" }, { "commit": "bf7901cd6dd76a0d73c581ad7a788225590ba699", "tree": "217fbc476aa52f7c285849266cb37a144fcb200a", "parents": [ "a080ef55039ac603730c4c69a22188c16c3eeb33" ], "author": { "name": "Taticharla Venkata Sai", "email": "venkatasai.taticharla@amd.com", "time": "Mon Jul 21 10:16:51 2025 +0530" }, "committer": { "name": "Venkata Sai Taticharla", "email": "venkatasai.taticharla@amd.com", "time": "Thu Jan 08 16:31:27 2026 +0000" }, "message": "fix(optee): add boolean type for expressions\n\nThis corrects MISRA violation C2012‑14.4:\nconditional or loop constructs were using non‑Boolean\nexpressions directly instead of comparisons or Boolean types.\n\nThe fix replaces them with explicit Boolean tests enforcing\nthat all controlling expressions have essentially Boolean type\nand improving code clarity and type safety.\n\nChange-Id: I150a8a674e8abf9c5409cc3d557af0e288ba1668\nSigned-off-by: Taticharla Venkata Sai \u003cvenkatasai.taticharla@amd.com\u003e\n" }, { "commit": "a080ef55039ac603730c4c69a22188c16c3eeb33", "tree": "b123392c07633e351bdbeae6c69e19c780aaf05a", "parents": [ "3b9016d683c49378ecd56f9647932a9d042ca4f1" ], "author": { "name": "Taticharla Venkata Sai", "email": "venkatasai.taticharla@amd.com", "time": "Sun Jul 20 16:21:01 2025 +0530" }, "committer": { "name": "Venkata Sai Taticharla", "email": "venkatasai.taticharla@amd.com", "time": "Thu Jan 08 16:31:27 2026 +0000" }, "message": "fix(optee): evaluate condition for boolean\n\nThis corrects the MISRA violation C2012-11.9:\nThe macro NULL shall be the only permitted form of integer\nnull pointer constant.\n\nThe condition is compared with NULL to get boolean result.\n\nChange-Id: Ib386b5a3c3a7febbbcb5da7546e72ea6269744dc\nSigned-off-by: Taticharla Venkata Sai \u003cvenkatasai.taticharla@amd.com\u003e\n" }, { "commit": "3b9016d683c49378ecd56f9647932a9d042ca4f1", "tree": "7f3968d85cb2e5fdadceea7dfa4a7c4c5cb26fbf", "parents": [ "6de7520a3b997a246d341b7df465844d5574a08d" ], "author": { "name": "Taticharla Venkata Sai", "email": "venkatasai.taticharla@amd.com", "time": "Tue Sep 09 17:07:47 2025 +0530" }, "committer": { "name": "Venkata Sai Taticharla", "email": "venkatasai.taticharla@amd.com", "time": "Thu Jan 08 16:31:27 2026 +0000" }, "message": "fix(optee): typecast operands to match data type\n\nThis corrects the MISRA violation C2012-10.1:\n\nOperands of different essential types were used in\nbitwise, arithmetic, or logical operations, violating\ntype uniformity.\n\nThe fix suffixes integer literals with \u0027U\u0027 to specify\nthem as unsigned constants, ensuring operands in\nbitwise, arithmetic, or logical operations have\nconsistent unsigned types. This approach avoids implicit\ntype promotions and maintains type safety by properly\ndeclaring the intended type of literals.\n\nChange-Id: Iead89348f107772175bbf7768554258b0095a922\nSigned-off-by: Taticharla Venkata Sai \u003cvenkatasai.taticharla@amd.com\u003e\n" }, { "commit": "6de7520a3b997a246d341b7df465844d5574a08d", "tree": "e40627b13ad3de1ffb390189d1f569c463af7fb0", "parents": [ "dee3312e6c62a078c3204bf715248dfdf7288906" ], "author": { "name": "Taticharla Venkata Sai", "email": "venkatasai.taticharla@amd.com", "time": "Sun Jul 20 16:17:05 2025 +0530" }, "committer": { "name": "Manish Pandey", "email": "manish.pandey2@arm.com", "time": "Thu Jan 08 16:31:27 2026 +0000" }, "message": "fix(el3-runtime): resolve essential-type mismatch\n\nThis resolves MISRA C:2012 Rule 10.7 violation\nwhere a composite expression involved operands of differing\nessential types, causing unintended implicit conversions.\n\nThe fix ensures all operands in the expression have matching\nessential types by introducing explicit casts,\npreventing unsafe or inconsistent arithmetic operations.\n\nChange-Id: If01dfe78e7a5cffc8b0efa6ac969b262e236852b\nSigned-off-by: Taticharla Venkata Sai \u003cvenkatasai.taticharla@amd.com\u003e\n" }, { "commit": "dee3312e6c62a078c3204bf715248dfdf7288906", "tree": "8d4d8120870665dab086e382a60e49ad659c33af", "parents": [ "3f637a40d624a9b620284f9e9ddc42706e02234c", "cf14b88725c775fd087248b0aa77959e3192b903" ], "author": { "name": "Govindraj Raja", "email": "govindraj.raja@arm.com", "time": "Thu Jan 08 16:02:18 2026 +0000" }, "committer": { "name": "TrustedFirmware Code Review", "email": "review@review.trustedfirmware.org", "time": "Thu Jan 08 16:02:18 2026 +0000" }, "message": "Merge \"fix(el3-runtime): actually check for the EA bit on exception entry\" into integration" }, { "commit": "cf14b88725c775fd087248b0aa77959e3192b903", "tree": "ed956c62eaef4beed0d2548096082f505a612484", "parents": [ "0eaf5de8e0a0678ab57602f8e804bd35245fcc2b" ], "author": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Wed Jan 07 08:09:50 2026 +0000" }, "committer": { "name": "Boyan Karatotev", "email": "boyan.karatotev@arm.com", "time": "Thu Jan 08 16:00:05 2026 +0000" }, "message": "fix(el3-runtime): actually check for the EA bit on exception entry\n\nThe C conversion patch - 14320bce3 - had a typo in it that it would\nbitwise or SCR_EL3 with the EA bit effectively making the check always\ntrue. Correct it to a bitwise and to actually check the bit.\n\nChange-Id: I9897cd6d816f5d86024a05bd58585d5fb2ab2e1d\nSigned-off-by: Boyan Karatotev \u003cboyan.karatotev@arm.com\u003e\n" } ], "next": "3f637a40d624a9b620284f9e9ddc42706e02234c" }