diff --git a/vendor/arm/mali/hwc_names.hpp b/vendor/arm/mali/hwc_names.hpp
index 65c4774..84a6e3f 100644
--- a/vendor/arm/mali/hwc_names.hpp
+++ b/vendor/arm/mali/hwc_names.hpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019 ARM Limited.
+ * Copyright (c) 2017-2020 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -52,8 +52,7 @@
  * where no counter exists.
  */
 
-static const char *const hardware_counters_mali_t60x[] =
-    {
+    static const char * const hardware_counters_mali_t60x[] = {
         /* Job Manager */
         "",
         "",
@@ -120,7 +119,7 @@
         "",
         "",
 
-        /*Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -252,7 +251,7 @@
         "T60x_AXI_BEATS_READ",
         "T60x_AXI_BEATS_WRITTEN",
 
-        /*L2 and MMU */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -318,8 +317,7 @@
         "T60x_L2_SNOOP_FULL",
         "T60x_L2_REPLAY_FULL"};
 
-static const char *const hardware_counters_mali_t62x[] =
-    {
+    static const char * const hardware_counters_mali_t62x[] = {
         /* Job Manager */
         "",
         "",
@@ -386,7 +384,7 @@
         "",
         "",
 
-        /*Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -518,7 +516,7 @@
         "T62x_AXI_BEATS_READ",
         "T62x_AXI_BEATS_WRITTEN",
 
-        /*L2 and MMU */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -584,8 +582,7 @@
         "T62x_L2_SNOOP_FULL",
         "T62x_L2_REPLAY_FULL"};
 
-static const char *const hardware_counters_mali_t72x[] =
-    {
+    static const char * const hardware_counters_mali_t72x[] = {
         /* Job Manager */
         "",
         "",
@@ -652,7 +649,7 @@
         "",
         "",
 
-        /*Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -784,7 +781,7 @@
         "",
         "",
 
-        /*L2 and MMU */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -850,8 +847,7 @@
         "",
         ""};
 
-static const char *const hardware_counters_mali_t76x[] =
-    {
+    static const char * const hardware_counters_mali_t76x[] = {
         /* Job Manager */
         "",
         "",
@@ -918,7 +914,7 @@
         "",
         "",
 
-        /*Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -1050,7 +1046,7 @@
         "T76x_AXI_BEATS_READ",
         "T76x_AXI_BEATS_WRITTEN",
 
-        /*L2 and MMU */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -1116,8 +1112,7 @@
         "T76x_L2_SNOOP_FULL",
         "T76x_L2_REPLAY_FULL"};
 
-static const char *const hardware_counters_mali_t82x[] =
-    {
+    static const char * const hardware_counters_mali_t82x[] = {
         /* Job Manager */
         "",
         "",
@@ -1184,7 +1179,7 @@
         "",
         "",
 
-        /*Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -1316,7 +1311,7 @@
         "T82x_AXI_BEATS_READ",
         "T82x_AXI_BEATS_WRITTEN",
 
-        /*L2 and MMU */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -1382,8 +1377,7 @@
         "T82x_L2_SNOOP_FULL",
         "T82x_L2_REPLAY_FULL"};
 
-static const char *const hardware_counters_mali_t83x[] =
-    {
+    static const char * const hardware_counters_mali_t83x[] = {
         /* Job Manager */
         "",
         "",
@@ -1450,7 +1444,7 @@
         "",
         "",
 
-        /*Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -1582,7 +1576,7 @@
         "T83x_AXI_BEATS_READ",
         "T83x_AXI_BEATS_WRITTEN",
 
-        /*L2 and MMU */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -1648,8 +1642,7 @@
         "T83x_L2_SNOOP_FULL",
         "T83x_L2_REPLAY_FULL"};
 
-static const char *const hardware_counters_mali_t86x[] =
-    {
+    static const char * const hardware_counters_mali_t86x[] = {
         /* Job Manager */
         "",
         "",
@@ -1716,7 +1709,7 @@
         "",
         "",
 
-        /*Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -1848,7 +1841,7 @@
         "T86x_AXI_BEATS_READ",
         "T86x_AXI_BEATS_WRITTEN",
 
-        /*L2 and MMU */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -1914,8 +1907,7 @@
         "T86x_L2_SNOOP_FULL",
         "T86x_L2_REPLAY_FULL"};
 
-static const char *const hardware_counters_mali_t88x[] =
-    {
+    static const char * const hardware_counters_mali_t88x[] = {
         /* Job Manager */
         "",
         "",
@@ -1982,7 +1974,7 @@
         "",
         "",
 
-        /*Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -2114,7 +2106,7 @@
         "T88x_AXI_BEATS_READ",
         "T88x_AXI_BEATS_WRITTEN",
 
-        /*L2 and MMU */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -2180,9 +2172,8 @@
         "T88x_L2_SNOOP_FULL",
         "T88x_L2_REPLAY_FULL"};
 
-static const char *const hardware_counters_mali_tHEx[] =
-    {
-        /* Performance counters for the Job Manager */
+    static const char * const hardware_counters_mali_tHEx[] = {
+        /* Job Manager */
         "",
         "",
         "",
@@ -2248,7 +2239,7 @@
         "",
         "",
 
-        /* Performance counters for the Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -2314,7 +2305,7 @@
         "THEx_UTLB_TRANS_MISS_DELAY",
         "THEx_UTLB_MMU_REQ",
 
-        /* Performance counters for the Shader Core */
+        /* Shader Core */
         "",
         "",
         "",
@@ -2380,7 +2371,7 @@
         "THEx_BEATS_WR_TIB",
         "",
 
-        /* Performance counters for the Memory System */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -2444,11 +2435,11 @@
         "",
         "",
         "",
-        ""};
+        "",
+    };
 
-static const char *const hardware_counters_mali_tMIx[] =
-    {
-        /* Performance counters for the Job Manager */
+    static const char * const hardware_counters_mali_tMIx[] = {
+        /* Job Manager */
         "",
         "",
         "",
@@ -2514,7 +2505,7 @@
         "",
         "",
 
-        /* Performance counters for the Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -2530,8 +2521,8 @@
         "TMIx_PRIM_CULLED",
         "TMIx_PRIM_CLIPPED",
         "TMIx_PRIM_SAT_CULLED",
-        "",
-        "",
+        "TMIx_BIN_ALLOC_INIT",
+        "TMIx_BIN_ALLOC_OVERFLOW",
         "TMIx_BUS_READ",
         "",
         "TMIx_BUS_WRITE",
@@ -2580,7 +2571,7 @@
         "TMIx_UTLB_TRANS_MISS_DELAY",
         "TMIx_UTLB_MMU_REQ",
 
-        /* Performance counters for the Shader Core */
+        /* Shader Core */
         "",
         "",
         "",
@@ -2646,7 +2637,7 @@
         "TMIx_BEATS_WR_TIB",
         "",
 
-        /* Performance counters for the Memory System */
+        /* L2 and MMU */
         "",
         "",
         "",
@@ -2710,11 +2701,277 @@
         "",
         "",
         "",
-        ""};
+        "",
+    };
 
-static const char *const hardware_counters_mali_tSIx[] =
-    {
-        /* Performance counters for the Job Manager */
+    static const char * const hardware_counters_mali_tDVx[] = {
+        /* Job Manager */
+        "",
+        "",
+        "",
+        "",
+        "TDVx_MESSAGES_SENT",
+        "TDVx_MESSAGES_RECEIVED",
+        "TDVx_GPU_ACTIVE",
+        "TDVx_IRQ_ACTIVE",
+        "TDVx_JS0_JOBS",
+        "TDVx_JS0_TASKS",
+        "TDVx_JS0_ACTIVE",
+        "TDVx_JS0_WAIT_FLUSH",
+        "TDVx_JS0_WAIT_READ",
+        "TDVx_JS0_WAIT_ISSUE",
+        "TDVx_JS0_WAIT_DEPEND",
+        "TDVx_JS0_WAIT_FINISH",
+        "TDVx_JS1_JOBS",
+        "TDVx_JS1_TASKS",
+        "TDVx_JS1_ACTIVE",
+        "TDVx_JS1_WAIT_FLUSH",
+        "TDVx_JS1_WAIT_READ",
+        "TDVx_JS1_WAIT_ISSUE",
+        "TDVx_JS1_WAIT_DEPEND",
+        "TDVx_JS1_WAIT_FINISH",
+        "TDVx_JS2_JOBS",
+        "TDVx_JS2_TASKS",
+        "TDVx_JS2_ACTIVE",
+        "TDVx_JS2_WAIT_FLUSH",
+        "TDVx_JS2_WAIT_READ",
+        "TDVx_JS2_WAIT_ISSUE",
+        "TDVx_JS2_WAIT_DEPEND",
+        "TDVx_JS2_WAIT_FINISH",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "TDVx_CACHE_FLUSH",
+
+        /* Tiler */
+        "",
+        "",
+        "",
+        "",
+        "TDVx_TILER_ACTIVE",
+        "TDVx_JOBS_PROCESSED",
+        "TDVx_TRIANGLES",
+        "TDVx_LINES",
+        "TDVx_POINTS",
+        "TDVx_FRONT_FACING",
+        "TDVx_BACK_FACING",
+        "TDVx_PRIM_VISIBLE",
+        "TDVx_PRIM_CULLED",
+        "TDVx_PRIM_CLIPPED",
+        "TDVx_PRIM_SAT_CULLED",
+        "TDVx_BIN_ALLOC_INIT",
+        "TDVx_BIN_ALLOC_OVERFLOW",
+        "TDVx_BUS_READ",
+        "",
+        "TDVx_BUS_WRITE",
+        "TDVx_LOADING_DESC",
+        "TDVx_IDVS_POS_SHAD_REQ",
+        "TDVx_IDVS_POS_SHAD_WAIT",
+        "TDVx_IDVS_POS_SHAD_STALL",
+        "TDVx_IDVS_POS_FIFO_FULL",
+        "TDVx_PREFETCH_STALL",
+        "TDVx_VCACHE_HIT",
+        "TDVx_VCACHE_MISS",
+        "TDVx_VCACHE_LINE_WAIT",
+        "TDVx_VFETCH_POS_READ_WAIT",
+        "TDVx_VFETCH_VERTEX_WAIT",
+        "TDVx_VFETCH_STALL",
+        "TDVx_PRIMASSY_STALL",
+        "TDVx_BBOX_GEN_STALL",
+        "TDVx_IDVS_VBU_HIT",
+        "TDVx_IDVS_VBU_MISS",
+        "TDVx_IDVS_VBU_LINE_DEALLOCATE",
+        "TDVx_IDVS_VAR_SHAD_REQ",
+        "TDVx_IDVS_VAR_SHAD_STALL",
+        "TDVx_BINNER_STALL",
+        "TDVx_ITER_STALL",
+        "TDVx_COMPRESS_MISS",
+        "TDVx_COMPRESS_STALL",
+        "TDVx_PCACHE_HIT",
+        "TDVx_PCACHE_MISS",
+        "TDVx_PCACHE_MISS_STALL",
+        "TDVx_PCACHE_EVICT_STALL",
+        "TDVx_PMGR_PTR_WR_STALL",
+        "TDVx_PMGR_PTR_RD_STALL",
+        "TDVx_PMGR_CMD_WR_STALL",
+        "TDVx_WRBUF_ACTIVE",
+        "TDVx_WRBUF_HIT",
+        "TDVx_WRBUF_MISS",
+        "TDVx_WRBUF_NO_FREE_LINE_STALL",
+        "TDVx_WRBUF_NO_AXI_ID_STALL",
+        "TDVx_WRBUF_AXI_STALL",
+        "",
+        "",
+        "",
+        "TDVx_UTLB_TRANS",
+        "TDVx_UTLB_TRANS_HIT",
+        "TDVx_UTLB_TRANS_STALL",
+        "TDVx_UTLB_TRANS_MISS_DELAY",
+        "TDVx_UTLB_MMU_REQ",
+
+        /* Shader Core */
+        "",
+        "",
+        "",
+        "",
+        "TDVx_FRAG_ACTIVE",
+        "TDVx_FRAG_PRIMITIVES",
+        "TDVx_FRAG_PRIM_RAST",
+        "TDVx_FRAG_FPK_ACTIVE",
+        "TDVx_FRAG_STARVING",
+        "TDVx_FRAG_WARPS",
+        "TDVx_FRAG_PARTIAL_WARPS",
+        "TDVx_FRAG_QUADS_RAST",
+        "TDVx_FRAG_QUADS_EZS_TEST",
+        "TDVx_FRAG_QUADS_EZS_UPDATE",
+        "TDVx_FRAG_QUADS_EZS_KILL",
+        "TDVx_FRAG_LZS_TEST",
+        "TDVx_FRAG_LZS_KILL",
+        "",
+        "TDVx_FRAG_PTILES",
+        "TDVx_FRAG_TRANS_ELIM",
+        "TDVx_QUAD_FPK_KILLER",
+        "",
+        "TDVx_COMPUTE_ACTIVE",
+        "TDVx_COMPUTE_TASKS",
+        "TDVx_COMPUTE_WARPS",
+        "TDVx_COMPUTE_STARVING",
+        "TDVx_EXEC_CORE_ACTIVE",
+        "TDVx_EXEC_ACTIVE",
+        "TDVx_EXEC_INSTR_COUNT",
+        "TDVx_EXEC_INSTR_DIVERGED",
+        "TDVx_EXEC_INSTR_STARVING",
+        "TDVx_ARITH_INSTR_SINGLE_FMA",
+        "TDVx_ARITH_INSTR_DOUBLE",
+        "TDVx_ARITH_INSTR_MSG",
+        "TDVx_ARITH_INSTR_MSG_ONLY",
+        "TDVx_TEX_MSGI_NUM_QUADS",
+        "TDVx_TEX_DFCH_NUM_PASSES",
+        "TDVx_TEX_DFCH_NUM_PASSES_MISS",
+        "TDVx_TEX_DFCH_NUM_PASSES_MIP_MAP",
+        "TDVx_TEX_TIDX_NUM_SPLIT_MIP_MAP",
+        "TDVx_TEX_TFCH_NUM_LINES_FETCHED",
+        "TDVx_TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED",
+        "TDVx_TEX_TFCH_NUM_OPERATIONS",
+        "TDVx_TEX_FILT_NUM_OPERATIONS",
+        "TDVx_LS_MEM_READ_FULL",
+        "TDVx_LS_MEM_READ_SHORT",
+        "TDVx_LS_MEM_WRITE_FULL",
+        "TDVx_LS_MEM_WRITE_SHORT",
+        "TDVx_LS_MEM_ATOMIC",
+        "TDVx_VARY_INSTR",
+        "TDVx_VARY_SLOT_32",
+        "TDVx_VARY_SLOT_16",
+        "TDVx_ATTR_INSTR",
+        "TDVx_ARITH_INSTR_FP_MUL",
+        "TDVx_BEATS_RD_FTC",
+        "TDVx_BEATS_RD_FTC_EXT",
+        "TDVx_BEATS_RD_LSC",
+        "TDVx_BEATS_RD_LSC_EXT",
+        "TDVx_BEATS_RD_TEX",
+        "TDVx_BEATS_RD_TEX_EXT",
+        "TDVx_BEATS_RD_OTHER",
+        "TDVx_BEATS_WR_LSC_OTHER",
+        "TDVx_BEATS_WR_TIB",
+        "TDVx_BEATS_WR_LSC_WB",
+
+        /* L2 and MMU */
+        "",
+        "",
+        "",
+        "",
+        "TDVx_MMU_REQUESTS",
+        "TDVx_MMU_TABLE_READS_L3",
+        "TDVx_MMU_TABLE_READS_L2",
+        "TDVx_MMU_HIT_L3",
+        "TDVx_MMU_HIT_L2",
+        "TDVx_MMU_S2_REQUESTS",
+        "TDVx_MMU_S2_TABLE_READS_L3",
+        "TDVx_MMU_S2_TABLE_READS_L2",
+        "TDVx_MMU_S2_HIT_L3",
+        "TDVx_MMU_S2_HIT_L2",
+        "",
+        "",
+        "TDVx_L2_RD_MSG_IN",
+        "TDVx_L2_RD_MSG_IN_STALL",
+        "TDVx_L2_WR_MSG_IN",
+        "TDVx_L2_WR_MSG_IN_STALL",
+        "TDVx_L2_SNP_MSG_IN",
+        "TDVx_L2_SNP_MSG_IN_STALL",
+        "TDVx_L2_RD_MSG_OUT",
+        "TDVx_L2_RD_MSG_OUT_STALL",
+        "TDVx_L2_WR_MSG_OUT",
+        "TDVx_L2_ANY_LOOKUP",
+        "TDVx_L2_READ_LOOKUP",
+        "TDVx_L2_WRITE_LOOKUP",
+        "TDVx_L2_EXT_SNOOP_LOOKUP",
+        "TDVx_L2_EXT_READ",
+        "TDVx_L2_EXT_READ_NOSNP",
+        "TDVx_L2_EXT_READ_UNIQUE",
+        "TDVx_L2_EXT_READ_BEATS",
+        "TDVx_L2_EXT_AR_STALL",
+        "TDVx_L2_EXT_AR_CNT_Q1",
+        "TDVx_L2_EXT_AR_CNT_Q2",
+        "TDVx_L2_EXT_AR_CNT_Q3",
+        "TDVx_L2_EXT_RRESP_0_127",
+        "TDVx_L2_EXT_RRESP_128_191",
+        "TDVx_L2_EXT_RRESP_192_255",
+        "TDVx_L2_EXT_RRESP_256_319",
+        "TDVx_L2_EXT_RRESP_320_383",
+        "TDVx_L2_EXT_WRITE",
+        "TDVx_L2_EXT_WRITE_NOSNP_FULL",
+        "TDVx_L2_EXT_WRITE_NOSNP_PTL",
+        "TDVx_L2_EXT_WRITE_SNP_FULL",
+        "TDVx_L2_EXT_WRITE_SNP_PTL",
+        "TDVx_L2_EXT_WRITE_BEATS",
+        "TDVx_L2_EXT_W_STALL",
+        "TDVx_L2_EXT_AW_CNT_Q1",
+        "TDVx_L2_EXT_AW_CNT_Q2",
+        "TDVx_L2_EXT_AW_CNT_Q3",
+        "TDVx_L2_EXT_SNOOP",
+        "TDVx_L2_EXT_SNOOP_STALL",
+        "TDVx_L2_EXT_SNOOP_RESP_CLEAN",
+        "TDVx_L2_EXT_SNOOP_RESP_DATA",
+        "TDVx_L2_EXT_SNOOP_INTERNAL",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+    };
+
+    static const char * const hardware_counters_mali_tSIx[] = {
+        /* Job Manager */
         "",
         "",
         "",
@@ -2726,7 +2983,7 @@
         "TSIx_JS0_JOBS",
         "TSIx_JS0_TASKS",
         "TSIx_JS0_ACTIVE",
-        "",
+        "TSIx_JS0_WAIT_FLUSH",
         "TSIx_JS0_WAIT_READ",
         "TSIx_JS0_WAIT_ISSUE",
         "TSIx_JS0_WAIT_DEPEND",
@@ -2734,7 +2991,7 @@
         "TSIx_JS1_JOBS",
         "TSIx_JS1_TASKS",
         "TSIx_JS1_ACTIVE",
-        "",
+        "TSIx_JS1_WAIT_FLUSH",
         "TSIx_JS1_WAIT_READ",
         "TSIx_JS1_WAIT_ISSUE",
         "TSIx_JS1_WAIT_DEPEND",
@@ -2742,7 +2999,7 @@
         "TSIx_JS2_JOBS",
         "TSIx_JS2_TASKS",
         "TSIx_JS2_ACTIVE",
-        "",
+        "TSIx_JS2_WAIT_FLUSH",
         "TSIx_JS2_WAIT_READ",
         "TSIx_JS2_WAIT_ISSUE",
         "TSIx_JS2_WAIT_DEPEND",
@@ -2780,7 +3037,7 @@
         "",
         "",
 
-        /* Performance counters for the Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -2796,16 +3053,16 @@
         "TSIx_PRIM_CULLED",
         "TSIx_PRIM_CLIPPED",
         "TSIx_PRIM_SAT_CULLED",
-        "",
-        "",
+        "TSIx_BIN_ALLOC_INIT",
+        "TSIx_BIN_ALLOC_OVERFLOW",
         "TSIx_BUS_READ",
         "",
         "TSIx_BUS_WRITE",
         "TSIx_LOADING_DESC",
-        "",
-        "",
-        "",
-        "",
+        "TSIx_IDVS_POS_SHAD_REQ",
+        "TSIx_IDVS_POS_SHAD_WAIT",
+        "TSIx_IDVS_POS_SHAD_STALL",
+        "TSIx_IDVS_POS_FIFO_FULL",
         "TSIx_PREFETCH_STALL",
         "TSIx_VCACHE_HIT",
         "TSIx_VCACHE_MISS",
@@ -2815,11 +3072,11 @@
         "TSIx_VFETCH_STALL",
         "TSIx_PRIMASSY_STALL",
         "TSIx_BBOX_GEN_STALL",
-        "",
-        "",
-        "",
-        "",
-        "",
+        "TSIx_IDVS_VBU_HIT",
+        "TSIx_IDVS_VBU_MISS",
+        "TSIx_IDVS_VBU_LINE_DEALLOCATE",
+        "TSIx_IDVS_VAR_SHAD_REQ",
+        "TSIx_IDVS_VAR_SHAD_STALL",
         "TSIx_BINNER_STALL",
         "TSIx_ITER_STALL",
         "TSIx_COMPRESS_MISS",
@@ -2846,7 +3103,7 @@
         "TSIx_UTLB_TRANS_MISS_DELAY",
         "TSIx_UTLB_MMU_REQ",
 
-        /* Performance counters for the Shader Core */
+        /* Shader Core */
         "",
         "",
         "",
@@ -2882,15 +3139,15 @@
         "TSIx_ARITH_INSTR_DOUBLE",
         "TSIx_ARITH_INSTR_MSG",
         "TSIx_ARITH_INSTR_MSG_ONLY",
-        "TSIx_TEX_INSTR",
-        "TSIx_TEX_INSTR_MIPMAP",
-        "TSIx_TEX_INSTR_COMPRESSED",
-        "TSIx_TEX_INSTR_3D",
-        "TSIx_TEX_INSTR_TRILINEAR",
-        "TSIx_TEX_COORD_ISSUE",
-        "TSIx_TEX_COORD_STALL",
-        "TSIx_TEX_STARVE_CACHE",
-        "TSIx_TEX_STARVE_FILTER",
+        "TSIx_TEX_MSGI_NUM_QUADS",
+        "TSIx_TEX_DFCH_NUM_PASSES",
+        "TSIx_TEX_DFCH_NUM_PASSES_MISS",
+        "TSIx_TEX_DFCH_NUM_PASSES_MIP_MAP",
+        "TSIx_TEX_TIDX_NUM_SPLIT_MIP_MAP",
+        "TSIx_TEX_TFCH_NUM_LINES_FETCHED",
+        "TSIx_TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED",
+        "TSIx_TEX_TFCH_NUM_OPERATIONS",
+        "TSIx_TEX_FILT_NUM_OPERATIONS",
         "TSIx_LS_MEM_READ_FULL",
         "TSIx_LS_MEM_READ_SHORT",
         "TSIx_LS_MEM_WRITE_FULL",
@@ -2908,25 +3165,25 @@
         "TSIx_BEATS_RD_TEX",
         "TSIx_BEATS_RD_TEX_EXT",
         "TSIx_BEATS_RD_OTHER",
-        "TSIx_BEATS_WR_LSC",
+        "TSIx_BEATS_WR_LSC_OTHER",
         "TSIx_BEATS_WR_TIB",
-        "",
+        "TSIx_BEATS_WR_LSC_WB",
 
-        /* Performance counters for the Memory System */
+        /* L2 and MMU */
         "",
         "",
         "",
         "",
         "TSIx_MMU_REQUESTS",
-        "",
-        "",
-        "",
-        "",
-        "",
-        "",
-        "",
-        "",
-        "",
+        "TSIx_MMU_TABLE_READS_L3",
+        "TSIx_MMU_TABLE_READS_L2",
+        "TSIx_MMU_HIT_L3",
+        "TSIx_MMU_HIT_L2",
+        "TSIx_MMU_S2_REQUESTS",
+        "TSIx_MMU_S2_TABLE_READS_L3",
+        "TSIx_MMU_S2_TABLE_READS_L2",
+        "TSIx_MMU_S2_HIT_L3",
+        "TSIx_MMU_S2_HIT_L2",
         "",
         "",
         "TSIx_L2_RD_MSG_IN",
@@ -2976,11 +3233,11 @@
         "",
         "",
         "",
-        ""};
+        "",
+    };
 
-static const char *const hardware_counters_mali_tNOx[] =
-    {
-        /* Performance counters for the Job Manager */
+    static const char * const hardware_counters_mali_tNOx[] = {
+        /* Job Manager */
         "",
         "",
         "",
@@ -2992,7 +3249,7 @@
         "TNOx_JS0_JOBS",
         "TNOx_JS0_TASKS",
         "TNOx_JS0_ACTIVE",
-        "",
+        "TNOx_JS0_WAIT_FLUSH",
         "TNOx_JS0_WAIT_READ",
         "TNOx_JS0_WAIT_ISSUE",
         "TNOx_JS0_WAIT_DEPEND",
@@ -3000,7 +3257,7 @@
         "TNOx_JS1_JOBS",
         "TNOx_JS1_TASKS",
         "TNOx_JS1_ACTIVE",
-        "",
+        "TNOx_JS1_WAIT_FLUSH",
         "TNOx_JS1_WAIT_READ",
         "TNOx_JS1_WAIT_ISSUE",
         "TNOx_JS1_WAIT_DEPEND",
@@ -3008,7 +3265,7 @@
         "TNOx_JS2_JOBS",
         "TNOx_JS2_TASKS",
         "TNOx_JS2_ACTIVE",
-        "",
+        "TNOx_JS2_WAIT_FLUSH",
         "TNOx_JS2_WAIT_READ",
         "TNOx_JS2_WAIT_ISSUE",
         "TNOx_JS2_WAIT_DEPEND",
@@ -3044,9 +3301,9 @@
         "",
         "",
         "",
-        "",
+        "TNOx_CACHE_FLUSH",
 
-        /* Performance counters for the Tiler */
+        /* Tiler */
         "",
         "",
         "",
@@ -3112,7 +3369,7 @@
         "TNOx_UTLB_TRANS_MISS_DELAY",
         "TNOx_UTLB_MMU_REQ",
 
-        /* Performance counters for the Shader Core */
+        /* Shader Core */
         "",
         "",
         "",
@@ -3154,7 +3411,7 @@
         "TNOx_TEX_DFCH_NUM_PASSES_MIP_MAP",
         "TNOx_TEX_TIDX_NUM_SPLIT_MIP_MAP",
         "TNOx_TEX_TFCH_NUM_LINES_FETCHED",
-        "TNOx_TEX_TFCH_NUM_LINES_FETCHED_BLOCK",
+        "TNOx_TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED",
         "TNOx_TEX_TFCH_NUM_OPERATIONS",
         "TNOx_TEX_FILT_NUM_OPERATIONS",
         "TNOx_LS_MEM_READ_FULL",
@@ -3178,21 +3435,21 @@
         "TNOx_BEATS_WR_TIB",
         "TNOx_BEATS_WR_LSC_WB",
 
-        /* Performance counters for the Memory System */
+        /* L2 and MMU */
         "",
         "",
         "",
         "",
         "TNOx_MMU_REQUESTS",
-        "",
-        "",
-        "",
-        "",
-        "",
-        "",
-        "",
-        "",
-        "",
+        "TNOx_MMU_TABLE_READS_L3",
+        "TNOx_MMU_TABLE_READS_L2",
+        "TNOx_MMU_HIT_L3",
+        "TNOx_MMU_HIT_L2",
+        "TNOx_MMU_S2_REQUESTS",
+        "TNOx_MMU_S2_TABLE_READS_L3",
+        "TNOx_MMU_S2_TABLE_READS_L2",
+        "TNOx_MMU_S2_HIT_L3",
+        "TNOx_MMU_S2_HIT_L2",
         "",
         "",
         "TNOx_L2_RD_MSG_IN",
@@ -3242,7 +3499,806 @@
         "",
         "",
         "",
-        ""};
+        "",
+    };
+
+    static const char * const hardware_counters_mali_tGOx[] = {
+        /* Job Manager */
+        "",
+        "",
+        "",
+        "",
+        "TGOx_MESSAGES_SENT",
+        "TGOx_MESSAGES_RECEIVED",
+        "TGOx_GPU_ACTIVE",
+        "TGOx_IRQ_ACTIVE",
+        "TGOx_JS0_JOBS",
+        "TGOx_JS0_TASKS",
+        "TGOx_JS0_ACTIVE",
+        "TGOx_JS0_WAIT_FLUSH",
+        "TGOx_JS0_WAIT_READ",
+        "TGOx_JS0_WAIT_ISSUE",
+        "TGOx_JS0_WAIT_DEPEND",
+        "TGOx_JS0_WAIT_FINISH",
+        "TGOx_JS1_JOBS",
+        "TGOx_JS1_TASKS",
+        "TGOx_JS1_ACTIVE",
+        "TGOx_JS1_WAIT_FLUSH",
+        "TGOx_JS1_WAIT_READ",
+        "TGOx_JS1_WAIT_ISSUE",
+        "TGOx_JS1_WAIT_DEPEND",
+        "TGOx_JS1_WAIT_FINISH",
+        "TGOx_JS2_JOBS",
+        "TGOx_JS2_TASKS",
+        "TGOx_JS2_ACTIVE",
+        "TGOx_JS2_WAIT_FLUSH",
+        "TGOx_JS2_WAIT_READ",
+        "TGOx_JS2_WAIT_ISSUE",
+        "TGOx_JS2_WAIT_DEPEND",
+        "TGOx_JS2_WAIT_FINISH",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "TGOx_CACHE_FLUSH",
+
+        /* Tiler */
+        "",
+        "",
+        "",
+        "",
+        "TGOx_TILER_ACTIVE",
+        "TGOx_JOBS_PROCESSED",
+        "TGOx_TRIANGLES",
+        "TGOx_LINES",
+        "TGOx_POINTS",
+        "TGOx_FRONT_FACING",
+        "TGOx_BACK_FACING",
+        "TGOx_PRIM_VISIBLE",
+        "TGOx_PRIM_CULLED",
+        "TGOx_PRIM_CLIPPED",
+        "TGOx_PRIM_SAT_CULLED",
+        "TGOx_BIN_ALLOC_INIT",
+        "TGOx_BIN_ALLOC_OVERFLOW",
+        "TGOx_BUS_READ",
+        "",
+        "TGOx_BUS_WRITE",
+        "TGOx_LOADING_DESC",
+        "TGOx_IDVS_POS_SHAD_REQ",
+        "TGOx_IDVS_POS_SHAD_WAIT",
+        "TGOx_IDVS_POS_SHAD_STALL",
+        "TGOx_IDVS_POS_FIFO_FULL",
+        "TGOx_PREFETCH_STALL",
+        "TGOx_VCACHE_HIT",
+        "TGOx_VCACHE_MISS",
+        "TGOx_VCACHE_LINE_WAIT",
+        "TGOx_VFETCH_POS_READ_WAIT",
+        "TGOx_VFETCH_VERTEX_WAIT",
+        "TGOx_VFETCH_STALL",
+        "TGOx_PRIMASSY_STALL",
+        "TGOx_BBOX_GEN_STALL",
+        "TGOx_IDVS_VBU_HIT",
+        "TGOx_IDVS_VBU_MISS",
+        "TGOx_IDVS_VBU_LINE_DEALLOCATE",
+        "TGOx_IDVS_VAR_SHAD_REQ",
+        "TGOx_IDVS_VAR_SHAD_STALL",
+        "TGOx_BINNER_STALL",
+        "TGOx_ITER_STALL",
+        "TGOx_COMPRESS_MISS",
+        "TGOx_COMPRESS_STALL",
+        "TGOx_PCACHE_HIT",
+        "TGOx_PCACHE_MISS",
+        "TGOx_PCACHE_MISS_STALL",
+        "TGOx_PCACHE_EVICT_STALL",
+        "TGOx_PMGR_PTR_WR_STALL",
+        "TGOx_PMGR_PTR_RD_STALL",
+        "TGOx_PMGR_CMD_WR_STALL",
+        "TGOx_WRBUF_ACTIVE",
+        "TGOx_WRBUF_HIT",
+        "TGOx_WRBUF_MISS",
+        "TGOx_WRBUF_NO_FREE_LINE_STALL",
+        "TGOx_WRBUF_NO_AXI_ID_STALL",
+        "TGOx_WRBUF_AXI_STALL",
+        "",
+        "",
+        "",
+        "TGOx_UTLB_TRANS",
+        "TGOx_UTLB_TRANS_HIT",
+        "TGOx_UTLB_TRANS_STALL",
+        "TGOx_UTLB_TRANS_MISS_DELAY",
+        "TGOx_UTLB_MMU_REQ",
+
+        /* Shader Core */
+        "",
+        "",
+        "",
+        "",
+        "TGOx_FRAG_ACTIVE",
+        "TGOx_FRAG_PRIMITIVES",
+        "TGOx_FRAG_PRIM_RAST",
+        "TGOx_FRAG_FPK_ACTIVE",
+        "TGOx_FRAG_STARVING",
+        "TGOx_FRAG_WARPS",
+        "TGOx_FRAG_PARTIAL_WARPS",
+        "TGOx_FRAG_QUADS_RAST",
+        "TGOx_FRAG_QUADS_EZS_TEST",
+        "TGOx_FRAG_QUADS_EZS_UPDATE",
+        "TGOx_FRAG_QUADS_EZS_KILL",
+        "TGOx_FRAG_LZS_TEST",
+        "TGOx_FRAG_LZS_KILL",
+        "TGOx_WARP_REG_SIZE_64",
+        "TGOx_FRAG_PTILES",
+        "TGOx_FRAG_TRANS_ELIM",
+        "TGOx_QUAD_FPK_KILLER",
+        "TGOx_FULL_QUAD_WARPS",
+        "TGOx_COMPUTE_ACTIVE",
+        "TGOx_COMPUTE_TASKS",
+        "TGOx_COMPUTE_WARPS",
+        "TGOx_COMPUTE_STARVING",
+        "TGOx_EXEC_CORE_ACTIVE",
+        "TGOx_EXEC_ACTIVE",
+        "TGOx_EXEC_INSTR_COUNT",
+        "TGOx_EXEC_INSTR_DIVERGED",
+        "TGOx_EXEC_INSTR_STARVING",
+        "TGOx_ARITH_INSTR_SINGLE_FMA",
+        "TGOx_ARITH_INSTR_DOUBLE",
+        "TGOx_ARITH_INSTR_MSG",
+        "TGOx_ARITH_INSTR_MSG_ONLY",
+        "TGOx_TEX_MSGI_NUM_QUADS",
+        "TGOx_TEX_DFCH_NUM_PASSES",
+        "TGOx_TEX_DFCH_NUM_PASSES_MISS",
+        "TGOx_TEX_DFCH_NUM_PASSES_MIP_MAP",
+        "TGOx_TEX_TIDX_NUM_SPLIT_MIP_MAP",
+        "TGOx_TEX_TFCH_NUM_LINES_FETCHED",
+        "TGOx_TEX_TFCH_NUM_LINES_FETCHED_BLOCK_COMPRESSED",
+        "TGOx_TEX_TFCH_NUM_OPERATIONS",
+        "TGOx_TEX_FILT_NUM_OPERATIONS",
+        "TGOx_LS_MEM_READ_FULL",
+        "TGOx_LS_MEM_READ_SHORT",
+        "TGOx_LS_MEM_WRITE_FULL",
+        "TGOx_LS_MEM_WRITE_SHORT",
+        "TGOx_LS_MEM_ATOMIC",
+        "TGOx_VARY_INSTR",
+        "TGOx_VARY_SLOT_32",
+        "TGOx_VARY_SLOT_16",
+        "TGOx_ATTR_INSTR",
+        "TGOx_ARITH_INSTR_FP_MUL",
+        "TGOx_BEATS_RD_FTC",
+        "TGOx_BEATS_RD_FTC_EXT",
+        "TGOx_BEATS_RD_LSC",
+        "TGOx_BEATS_RD_LSC_EXT",
+        "TGOx_BEATS_RD_TEX",
+        "TGOx_BEATS_RD_TEX_EXT",
+        "TGOx_BEATS_RD_OTHER",
+        "TGOx_BEATS_WR_LSC_WB",
+        "TGOx_BEATS_WR_TIB",
+        "TGOx_BEATS_WR_LSC_OTHER",
+
+        /* L2 and MMU */
+        "",
+        "",
+        "",
+        "",
+        "TGOx_MMU_REQUESTS",
+        "TGOx_MMU_TABLE_READS_L3",
+        "TGOx_MMU_TABLE_READS_L2",
+        "TGOx_MMU_HIT_L3",
+        "TGOx_MMU_HIT_L2",
+        "TGOx_MMU_S2_REQUESTS",
+        "TGOx_MMU_S2_TABLE_READS_L3",
+        "TGOx_MMU_S2_TABLE_READS_L2",
+        "TGOx_MMU_S2_HIT_L3",
+        "TGOx_MMU_S2_HIT_L2",
+        "",
+        "",
+        "TGOx_L2_RD_MSG_IN",
+        "TGOx_L2_RD_MSG_IN_STALL",
+        "TGOx_L2_WR_MSG_IN",
+        "TGOx_L2_WR_MSG_IN_STALL",
+        "TGOx_L2_SNP_MSG_IN",
+        "TGOx_L2_SNP_MSG_IN_STALL",
+        "TGOx_L2_RD_MSG_OUT",
+        "TGOx_L2_RD_MSG_OUT_STALL",
+        "TGOx_L2_WR_MSG_OUT",
+        "TGOx_L2_ANY_LOOKUP",
+        "TGOx_L2_READ_LOOKUP",
+        "TGOx_L2_WRITE_LOOKUP",
+        "TGOx_L2_EXT_SNOOP_LOOKUP",
+        "TGOx_L2_EXT_READ",
+        "TGOx_L2_EXT_READ_NOSNP",
+        "TGOx_L2_EXT_READ_UNIQUE",
+        "TGOx_L2_EXT_READ_BEATS",
+        "TGOx_L2_EXT_AR_STALL",
+        "TGOx_L2_EXT_AR_CNT_Q1",
+        "TGOx_L2_EXT_AR_CNT_Q2",
+        "TGOx_L2_EXT_AR_CNT_Q3",
+        "TGOx_L2_EXT_RRESP_0_127",
+        "TGOx_L2_EXT_RRESP_128_191",
+        "TGOx_L2_EXT_RRESP_192_255",
+        "TGOx_L2_EXT_RRESP_256_319",
+        "TGOx_L2_EXT_RRESP_320_383",
+        "TGOx_L2_EXT_WRITE",
+        "TGOx_L2_EXT_WRITE_NOSNP_FULL",
+        "TGOx_L2_EXT_WRITE_NOSNP_PTL",
+        "TGOx_L2_EXT_WRITE_SNP_FULL",
+        "TGOx_L2_EXT_WRITE_SNP_PTL",
+        "TGOx_L2_EXT_WRITE_BEATS",
+        "TGOx_L2_EXT_W_STALL",
+        "TGOx_L2_EXT_AW_CNT_Q1",
+        "TGOx_L2_EXT_AW_CNT_Q2",
+        "TGOx_L2_EXT_AW_CNT_Q3",
+        "TGOx_L2_EXT_SNOOP",
+        "TGOx_L2_EXT_SNOOP_STALL",
+        "TGOx_L2_EXT_SNOOP_RESP_CLEAN",
+        "TGOx_L2_EXT_SNOOP_RESP_DATA",
+        "TGOx_L2_EXT_SNOOP_INTERNAL",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+    };
+
+    static const char * const hardware_counters_mali_tTRx[] = {
+        /* Job Manager */
+        "",
+        "",
+        "",
+        "",
+        "TTRx_MESSAGES_SENT",
+        "TTRx_MESSAGES_RECEIVED",
+        "TTRx_GPU_ACTIVE",
+        "TTRx_IRQ_ACTIVE",
+        "TTRx_JS0_JOBS",
+        "TTRx_JS0_TASKS",
+        "TTRx_JS0_ACTIVE",
+        "TTRx_JS0_WAIT_FLUSH",
+        "TTRx_JS0_WAIT_READ",
+        "TTRx_JS0_WAIT_ISSUE",
+        "TTRx_JS0_WAIT_DEPEND",
+        "TTRx_JS0_WAIT_FINISH",
+        "TTRx_JS1_JOBS",
+        "TTRx_JS1_TASKS",
+        "TTRx_JS1_ACTIVE",
+        "TTRx_JS1_WAIT_FLUSH",
+        "TTRx_JS1_WAIT_READ",
+        "TTRx_JS1_WAIT_ISSUE",
+        "TTRx_JS1_WAIT_DEPEND",
+        "TTRx_JS1_WAIT_FINISH",
+        "TTRx_JS2_JOBS",
+        "TTRx_JS2_TASKS",
+        "TTRx_JS2_ACTIVE",
+        "TTRx_JS2_WAIT_FLUSH",
+        "TTRx_JS2_WAIT_READ",
+        "TTRx_JS2_WAIT_ISSUE",
+        "TTRx_JS2_WAIT_DEPEND",
+        "TTRx_JS2_WAIT_FINISH",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "TTRx_CACHE_FLUSH",
+
+        /* Tiler */
+        "",
+        "",
+        "",
+        "",
+        "TTRx_TILER_ACTIVE",
+        "TTRx_JOBS_PROCESSED",
+        "TTRx_TRIANGLES",
+        "TTRx_LINES",
+        "TTRx_POINTS",
+        "TTRx_FRONT_FACING",
+        "TTRx_BACK_FACING",
+        "TTRx_PRIM_VISIBLE",
+        "TTRx_PRIM_CULLED",
+        "TTRx_PRIM_CLIPPED",
+        "TTRx_PRIM_SAT_CULLED",
+        "TTRx_BIN_ALLOC_INIT",
+        "TTRx_BIN_ALLOC_OVERFLOW",
+        "TTRx_BUS_READ",
+        "",
+        "TTRx_BUS_WRITE",
+        "TTRx_LOADING_DESC",
+        "TTRx_IDVS_POS_SHAD_REQ",
+        "TTRx_IDVS_POS_SHAD_WAIT",
+        "TTRx_IDVS_POS_SHAD_STALL",
+        "TTRx_IDVS_POS_FIFO_FULL",
+        "TTRx_PREFETCH_STALL",
+        "TTRx_VCACHE_HIT",
+        "TTRx_VCACHE_MISS",
+        "TTRx_VCACHE_LINE_WAIT",
+        "TTRx_VFETCH_POS_READ_WAIT",
+        "TTRx_VFETCH_VERTEX_WAIT",
+        "TTRx_VFETCH_STALL",
+        "TTRx_PRIMASSY_STALL",
+        "TTRx_BBOX_GEN_STALL",
+        "TTRx_IDVS_VBU_HIT",
+        "TTRx_IDVS_VBU_MISS",
+        "TTRx_IDVS_VBU_LINE_DEALLOCATE",
+        "TTRx_IDVS_VAR_SHAD_REQ",
+        "TTRx_IDVS_VAR_SHAD_STALL",
+        "TTRx_BINNER_STALL",
+        "TTRx_ITER_STALL",
+        "TTRx_COMPRESS_MISS",
+        "TTRx_COMPRESS_STALL",
+        "TTRx_PCACHE_HIT",
+        "TTRx_PCACHE_MISS",
+        "TTRx_PCACHE_MISS_STALL",
+        "TTRx_PCACHE_EVICT_STALL",
+        "TTRx_PMGR_PTR_WR_STALL",
+        "TTRx_PMGR_PTR_RD_STALL",
+        "TTRx_PMGR_CMD_WR_STALL",
+        "TTRx_WRBUF_ACTIVE",
+        "TTRx_WRBUF_HIT",
+        "TTRx_WRBUF_MISS",
+        "TTRx_WRBUF_NO_FREE_LINE_STALL",
+        "TTRx_WRBUF_NO_AXI_ID_STALL",
+        "TTRx_WRBUF_AXI_STALL",
+        "",
+        "",
+        "",
+        "TTRx_UTLB_TRANS",
+        "TTRx_UTLB_TRANS_HIT",
+        "TTRx_UTLB_TRANS_STALL",
+        "TTRx_UTLB_TRANS_MISS_DELAY",
+        "TTRx_UTLB_MMU_REQ",
+
+        /* Shader Core */
+        "",
+        "",
+        "",
+        "",
+        "TTRx_FRAG_ACTIVE",
+        "TTRx_FRAG_PRIMITIVES_OUT",
+        "TTRx_FRAG_PRIM_RAST",
+        "TTRx_FRAG_FPK_ACTIVE",
+        "TTRx_FRAG_STARVING",
+        "TTRx_FRAG_WARPS",
+        "TTRx_FRAG_PARTIAL_QUADS_RAST",
+        "TTRx_FRAG_QUADS_RAST",
+        "TTRx_FRAG_QUADS_EZS_TEST",
+        "TTRx_FRAG_QUADS_EZS_UPDATE",
+        "TTRx_FRAG_QUADS_EZS_KILL",
+        "TTRx_FRAG_LZS_TEST",
+        "TTRx_FRAG_LZS_KILL",
+        "TTRx_WARP_REG_SIZE_64",
+        "TTRx_FRAG_PTILES",
+        "TTRx_FRAG_TRANS_ELIM",
+        "TTRx_QUAD_FPK_KILLER",
+        "TTRx_FULL_QUAD_WARPS",
+        "TTRx_COMPUTE_ACTIVE",
+        "TTRx_COMPUTE_TASKS",
+        "TTRx_COMPUTE_WARPS",
+        "TTRx_COMPUTE_STARVING",
+        "TTRx_EXEC_CORE_ACTIVE",
+        "TTRx_EXEC_INSTR_FMA",
+        "TTRx_EXEC_INSTR_CVT",
+        "TTRx_EXEC_INSTR_SFU",
+        "TTRx_EXEC_INSTR_MSG",
+        "TTRx_EXEC_INSTR_DIVERGED",
+        "TTRx_EXEC_ICACHE_MISS",
+        "TTRx_EXEC_STARVE_ARITH",
+        "TTRx_CALL_BLEND_SHADER",
+        "TTRx_TEX_MSGI_NUM_FLITS",
+        "TTRx_TEX_DFCH_CLK_STALLED",
+        "TTRx_TEX_TFCH_CLK_STALLED",
+        "TTRx_TEX_TFCH_STARVED_PENDING_DATA_FETCH",
+        "TTRx_TEX_FILT_NUM_OPERATIONS",
+        "TTRx_TEX_FILT_NUM_FXR_OPERATIONS",
+        "TTRx_TEX_FILT_NUM_FST_OPERATIONS",
+        "TTRx_TEX_MSGO_NUM_MSG",
+        "TTRx_TEX_MSGO_NUM_FLITS",
+        "TTRx_LS_MEM_READ_FULL",
+        "TTRx_LS_MEM_READ_SHORT",
+        "TTRx_LS_MEM_WRITE_FULL",
+        "TTRx_LS_MEM_WRITE_SHORT",
+        "TTRx_LS_MEM_ATOMIC",
+        "TTRx_VARY_INSTR",
+        "TTRx_VARY_SLOT_32",
+        "TTRx_VARY_SLOT_16",
+        "TTRx_ATTR_INSTR",
+        "TTRx_ARITH_INSTR_FP_MUL",
+        "TTRx_BEATS_RD_FTC",
+        "TTRx_BEATS_RD_FTC_EXT",
+        "TTRx_BEATS_RD_LSC",
+        "TTRx_BEATS_RD_LSC_EXT",
+        "TTRx_BEATS_RD_TEX",
+        "TTRx_BEATS_RD_TEX_EXT",
+        "TTRx_BEATS_RD_OTHER",
+        "TTRx_BEATS_WR_LSC_OTHER",
+        "TTRx_BEATS_WR_TIB",
+        "TTRx_BEATS_WR_LSC_WB",
+
+        /* L2 and MMU */
+        "",
+        "",
+        "",
+        "",
+        "TTRx_MMU_REQUESTS",
+        "TTRx_MMU_TABLE_READS_L3",
+        "TTRx_MMU_TABLE_READS_L2",
+        "TTRx_MMU_HIT_L3",
+        "TTRx_MMU_HIT_L2",
+        "TTRx_MMU_S2_REQUESTS",
+        "TTRx_MMU_S2_TABLE_READS_L3",
+        "TTRx_MMU_S2_TABLE_READS_L2",
+        "TTRx_MMU_S2_HIT_L3",
+        "TTRx_MMU_S2_HIT_L2",
+        "",
+        "",
+        "TTRx_L2_RD_MSG_IN",
+        "TTRx_L2_RD_MSG_IN_STALL",
+        "TTRx_L2_WR_MSG_IN",
+        "TTRx_L2_WR_MSG_IN_STALL",
+        "TTRx_L2_SNP_MSG_IN",
+        "TTRx_L2_SNP_MSG_IN_STALL",
+        "TTRx_L2_RD_MSG_OUT",
+        "TTRx_L2_RD_MSG_OUT_STALL",
+        "TTRx_L2_WR_MSG_OUT",
+        "TTRx_L2_ANY_LOOKUP",
+        "TTRx_L2_READ_LOOKUP",
+        "TTRx_L2_WRITE_LOOKUP",
+        "TTRx_L2_EXT_SNOOP_LOOKUP",
+        "TTRx_L2_EXT_READ",
+        "TTRx_L2_EXT_READ_NOSNP",
+        "TTRx_L2_EXT_READ_UNIQUE",
+        "TTRx_L2_EXT_READ_BEATS",
+        "TTRx_L2_EXT_AR_STALL",
+        "TTRx_L2_EXT_AR_CNT_Q1",
+        "TTRx_L2_EXT_AR_CNT_Q2",
+        "TTRx_L2_EXT_AR_CNT_Q3",
+        "TTRx_L2_EXT_RRESP_0_127",
+        "TTRx_L2_EXT_RRESP_128_191",
+        "TTRx_L2_EXT_RRESP_192_255",
+        "TTRx_L2_EXT_RRESP_256_319",
+        "TTRx_L2_EXT_RRESP_320_383",
+        "TTRx_L2_EXT_WRITE",
+        "TTRx_L2_EXT_WRITE_NOSNP_FULL",
+        "TTRx_L2_EXT_WRITE_NOSNP_PTL",
+        "TTRx_L2_EXT_WRITE_SNP_FULL",
+        "TTRx_L2_EXT_WRITE_SNP_PTL",
+        "TTRx_L2_EXT_WRITE_BEATS",
+        "TTRx_L2_EXT_W_STALL",
+        "TTRx_L2_EXT_AW_CNT_Q1",
+        "TTRx_L2_EXT_AW_CNT_Q2",
+        "TTRx_L2_EXT_AW_CNT_Q3",
+        "TTRx_L2_EXT_SNOOP",
+        "TTRx_L2_EXT_SNOOP_STALL",
+        "TTRx_L2_EXT_SNOOP_RESP_CLEAN",
+        "TTRx_L2_EXT_SNOOP_RESP_DATA",
+        "TTRx_L2_EXT_SNOOP_INTERNAL",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+    };
+
+    static const char * const hardware_counters_mali_tNAx[] = {
+        /* Job Manager */
+        "",
+        "",
+        "",
+        "",
+        "TNAx_MESSAGES_SENT",
+        "TNAx_MESSAGES_RECEIVED",
+        "TNAx_GPU_ACTIVE",
+        "TNAx_IRQ_ACTIVE",
+        "TNAx_JS0_JOBS",
+        "TNAx_JS0_TASKS",
+        "TNAx_JS0_ACTIVE",
+        "TNAx_JS0_WAIT_FLUSH",
+        "TNAx_JS0_WAIT_READ",
+        "TNAx_JS0_WAIT_ISSUE",
+        "TNAx_JS0_WAIT_DEPEND",
+        "TNAx_JS0_WAIT_FINISH",
+        "TNAx_JS1_JOBS",
+        "TNAx_JS1_TASKS",
+        "TNAx_JS1_ACTIVE",
+        "TNAx_JS1_WAIT_FLUSH",
+        "TNAx_JS1_WAIT_READ",
+        "TNAx_JS1_WAIT_ISSUE",
+        "TNAx_JS1_WAIT_DEPEND",
+        "TNAx_JS1_WAIT_FINISH",
+        "TNAx_JS2_JOBS",
+        "TNAx_JS2_TASKS",
+        "TNAx_JS2_ACTIVE",
+        "TNAx_JS2_WAIT_FLUSH",
+        "TNAx_JS2_WAIT_READ",
+        "TNAx_JS2_WAIT_ISSUE",
+        "TNAx_JS2_WAIT_DEPEND",
+        "TNAx_JS2_WAIT_FINISH",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "TNAx_CACHE_FLUSH",
+
+        /* Tiler */
+        "",
+        "",
+        "",
+        "",
+        "TNAx_TILER_ACTIVE",
+        "TNAx_JOBS_PROCESSED",
+        "TNAx_TRIANGLES",
+        "TNAx_LINES",
+        "TNAx_POINTS",
+        "TNAx_FRONT_FACING",
+        "TNAx_BACK_FACING",
+        "TNAx_PRIM_VISIBLE",
+        "TNAx_PRIM_CULLED",
+        "TNAx_PRIM_CLIPPED",
+        "TNAx_PRIM_SAT_CULLED",
+        "TNAx_BIN_ALLOC_INIT",
+        "TNAx_BIN_ALLOC_OVERFLOW",
+        "TNAx_BUS_READ",
+        "",
+        "TNAx_BUS_WRITE",
+        "TNAx_LOADING_DESC",
+        "TNAx_IDVS_POS_SHAD_REQ",
+        "TNAx_IDVS_POS_SHAD_WAIT",
+        "TNAx_IDVS_POS_SHAD_STALL",
+        "TNAx_IDVS_POS_FIFO_FULL",
+        "TNAx_PREFETCH_STALL",
+        "TNAx_VCACHE_HIT",
+        "TNAx_VCACHE_MISS",
+        "TNAx_VCACHE_LINE_WAIT",
+        "TNAx_VFETCH_POS_READ_WAIT",
+        "TNAx_VFETCH_VERTEX_WAIT",
+        "TNAx_VFETCH_STALL",
+        "TNAx_PRIMASSY_STALL",
+        "TNAx_BBOX_GEN_STALL",
+        "TNAx_IDVS_VBU_HIT",
+        "TNAx_IDVS_VBU_MISS",
+        "TNAx_IDVS_VBU_LINE_DEALLOCATE",
+        "TNAx_IDVS_VAR_SHAD_REQ",
+        "TNAx_IDVS_VAR_SHAD_STALL",
+        "TNAx_BINNER_STALL",
+        "TNAx_ITER_STALL",
+        "TNAx_COMPRESS_MISS",
+        "TNAx_COMPRESS_STALL",
+        "TNAx_PCACHE_HIT",
+        "TNAx_PCACHE_MISS",
+        "TNAx_PCACHE_MISS_STALL",
+        "TNAx_PCACHE_EVICT_STALL",
+        "TNAx_PMGR_PTR_WR_STALL",
+        "TNAx_PMGR_PTR_RD_STALL",
+        "TNAx_PMGR_CMD_WR_STALL",
+        "TNAx_WRBUF_ACTIVE",
+        "TNAx_WRBUF_HIT",
+        "TNAx_WRBUF_MISS",
+        "TNAx_WRBUF_NO_FREE_LINE_STALL",
+        "TNAx_WRBUF_NO_AXI_ID_STALL",
+        "TNAx_WRBUF_AXI_STALL",
+        "",
+        "",
+        "",
+        "TNAx_UTLB_TRANS",
+        "TNAx_UTLB_TRANS_HIT",
+        "TNAx_UTLB_TRANS_STALL",
+        "TNAx_UTLB_TRANS_MISS_DELAY",
+        "TNAx_UTLB_MMU_REQ",
+
+        /* Shader Core */
+        "",
+        "",
+        "",
+        "",
+        "TNAx_FRAG_ACTIVE",
+        "TNAx_FRAG_PRIMITIVES_OUT",
+        "TNAx_FRAG_PRIM_RAST",
+        "TNAx_FRAG_FPK_ACTIVE",
+        "TNAx_FRAG_STARVING",
+        "TNAx_FRAG_WARPS",
+        "TNAx_FRAG_PARTIAL_QUADS_RAST",
+        "TNAx_FRAG_QUADS_RAST",
+        "TNAx_FRAG_QUADS_EZS_TEST",
+        "TNAx_FRAG_QUADS_EZS_UPDATE",
+        "TNAx_FRAG_QUADS_EZS_KILL",
+        "TNAx_FRAG_LZS_TEST",
+        "TNAx_FRAG_LZS_KILL",
+        "TNAx_WARP_REG_SIZE_64",
+        "TNAx_FRAG_PTILES",
+        "TNAx_FRAG_TRANS_ELIM",
+        "TNAx_QUAD_FPK_KILLER",
+        "TNAx_FULL_QUAD_WARPS",
+        "TNAx_COMPUTE_ACTIVE",
+        "TNAx_COMPUTE_TASKS",
+        "TNAx_COMPUTE_WARPS",
+        "TNAx_COMPUTE_STARVING",
+        "TNAx_EXEC_CORE_ACTIVE",
+        "TNAx_EXEC_INSTR_FMA",
+        "TNAx_EXEC_INSTR_CVT",
+        "TNAx_EXEC_INSTR_SFU",
+        "TNAx_EXEC_INSTR_MSG",
+        "TNAx_EXEC_INSTR_DIVERGED",
+        "TNAx_EXEC_ICACHE_MISS",
+        "TNAx_EXEC_STARVE_ARITH",
+        "TNAx_CALL_BLEND_SHADER",
+        "TNAx_TEX_MSGI_NUM_FLITS",
+        "TNAx_TEX_DFCH_CLK_STALLED",
+        "TNAx_TEX_TFCH_CLK_STALLED",
+        "TNAx_TEX_TFCH_STARVED_PENDING_DATA_FETCH",
+        "TNAx_TEX_FILT_NUM_OPERATIONS",
+        "TNAx_TEX_FILT_NUM_FXR_OPERATIONS",
+        "TNAx_TEX_FILT_NUM_FST_OPERATIONS",
+        "TNAx_TEX_MSGO_NUM_MSG",
+        "TNAx_TEX_MSGO_NUM_FLITS",
+        "TNAx_LS_MEM_READ_FULL",
+        "TNAx_LS_MEM_READ_SHORT",
+        "TNAx_LS_MEM_WRITE_FULL",
+        "TNAx_LS_MEM_WRITE_SHORT",
+        "TNAx_LS_MEM_ATOMIC",
+        "TNAx_VARY_INSTR",
+        "TNAx_VARY_SLOT_32",
+        "TNAx_VARY_SLOT_16",
+        "TNAx_ATTR_INSTR",
+        "TNAx_ARITH_INSTR_FP_MUL",
+        "TNAx_BEATS_RD_FTC",
+        "TNAx_BEATS_RD_FTC_EXT",
+        "TNAx_BEATS_RD_LSC",
+        "TNAx_BEATS_RD_LSC_EXT",
+        "TNAx_BEATS_RD_TEX",
+        "TNAx_BEATS_RD_TEX_EXT",
+        "TNAx_BEATS_RD_OTHER",
+        "TNAx_BEATS_WR_LSC_OTHER",
+        "TNAx_BEATS_WR_TIB",
+        "TNAx_BEATS_WR_LSC_WB",
+
+        /* L2 and MMU */
+        "",
+        "",
+        "",
+        "",
+        "TNAx_MMU_REQUESTS",
+        "TNAx_MMU_TABLE_READS_L3",
+        "TNAx_MMU_TABLE_READS_L2",
+        "TNAx_MMU_HIT_L3",
+        "TNAx_MMU_HIT_L2",
+        "TNAx_MMU_S2_REQUESTS",
+        "TNAx_MMU_S2_TABLE_READS_L3",
+        "TNAx_MMU_S2_TABLE_READS_L2",
+        "TNAx_MMU_S2_HIT_L3",
+        "TNAx_MMU_S2_HIT_L2",
+        "",
+        "",
+        "TNAx_L2_RD_MSG_IN",
+        "TNAx_L2_RD_MSG_IN_STALL",
+        "TNAx_L2_WR_MSG_IN",
+        "TNAx_L2_WR_MSG_IN_STALL",
+        "TNAx_L2_SNP_MSG_IN",
+        "TNAx_L2_SNP_MSG_IN_STALL",
+        "TNAx_L2_RD_MSG_OUT",
+        "TNAx_L2_RD_MSG_OUT_STALL",
+        "TNAx_L2_WR_MSG_OUT",
+        "TNAx_L2_ANY_LOOKUP",
+        "TNAx_L2_READ_LOOKUP",
+        "TNAx_L2_WRITE_LOOKUP",
+        "TNAx_L2_EXT_SNOOP_LOOKUP",
+        "TNAx_L2_EXT_READ",
+        "TNAx_L2_EXT_READ_NOSNP",
+        "TNAx_L2_EXT_READ_UNIQUE",
+        "TNAx_L2_EXT_READ_BEATS",
+        "TNAx_L2_EXT_AR_STALL",
+        "TNAx_L2_EXT_AR_CNT_Q1",
+        "TNAx_L2_EXT_AR_CNT_Q2",
+        "TNAx_L2_EXT_AR_CNT_Q3",
+        "TNAx_L2_EXT_RRESP_0_127",
+        "TNAx_L2_EXT_RRESP_128_191",
+        "TNAx_L2_EXT_RRESP_192_255",
+        "TNAx_L2_EXT_RRESP_256_319",
+        "TNAx_L2_EXT_RRESP_320_383",
+        "TNAx_L2_EXT_WRITE",
+        "TNAx_L2_EXT_WRITE_NOSNP_FULL",
+        "TNAx_L2_EXT_WRITE_NOSNP_PTL",
+        "TNAx_L2_EXT_WRITE_SNP_FULL",
+        "TNAx_L2_EXT_WRITE_SNP_PTL",
+        "TNAx_L2_EXT_WRITE_BEATS",
+        "TNAx_L2_EXT_W_STALL",
+        "TNAx_L2_EXT_AW_CNT_Q1",
+        "TNAx_L2_EXT_AW_CNT_Q2",
+        "TNAx_L2_EXT_AW_CNT_Q3",
+        "TNAx_L2_EXT_SNOOP",
+        "TNAx_L2_EXT_SNOOP_STALL",
+        "TNAx_L2_EXT_SNOOP_RESP_CLEAN",
+        "TNAx_L2_EXT_SNOOP_RESP_DATA",
+        "TNAx_L2_EXT_SNOOP_INTERNAL",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+        "",
+    };
 
 enum
 {
@@ -3263,7 +4319,12 @@
 	PRODUCT_ID_TMIX = 0x6000,
 	PRODUCT_ID_THEX = 0x6001,
 	PRODUCT_ID_TSIX = 0x7000,
-	PRODUCT_ID_TNOX = 0x7001
+	PRODUCT_ID_TNOX = 0x7001,
+	PRODUCT_ID_TGOX = 0x7002,
+	PRODUCT_ID_TDVX = 0x7003,
+	PRODUCT_ID_TTRX = 0x9000,
+	PRODUCT_ID_TNAXa = 0x9001,
+	PRODUCT_ID_TNAXb = 0x9003
 };
 
 struct CounterMapping
@@ -3335,7 +4396,22 @@
             PRODUCT_ID_TNOX,
             hardware_counters_mali_tNOx,
         },
-};
+        {
+            PRODUCT_ID_MASK_NEW,
+            PRODUCT_ID_TNAXa,
+            hardware_counters_mali_tNAx,
+        },
+        {
+            PRODUCT_ID_MASK_NEW,
+            PRODUCT_ID_TNAXb,
+            hardware_counters_mali_tNAx,
+        },
+        {
+            PRODUCT_ID_MASK_NEW,
+            PRODUCT_ID_TTRX,
+            hardware_counters_mali_tTRx,
+        },
+    };
 
 enum
 {
diff --git a/vendor/arm/mali/mali_profiler.cpp b/vendor/arm/mali/mali_profiler.cpp
index 8ae145c..f364930 100644
--- a/vendor/arm/mali/mali_profiler.cpp
+++ b/vendor/arm/mali/mali_profiler.cpp
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019 ARM Limited.
+ * Copyright (c) 2017-2020 ARM Limited.
  *
  * SPDX-License-Identifier: MIT
  *
@@ -221,6 +221,42 @@
 	// Throws if setup fails
 	init();
 
+	const std::unordered_map<GpuCounter, MaliValueGetter, GpuCounterHash> valhall_mappings = {
+	    {GpuCounter::GpuCycles, [this] { return get_counter_value(MALI_NAME_BLOCK_JM, "GPU_ACTIVE"); }},
+	    {GpuCounter::VertexComputeCycles, [this] { return get_counter_value(MALI_NAME_BLOCK_JM, "JS1_ACTIVE"); }},
+	    {GpuCounter::FragmentCycles, [this] { return get_counter_value(MALI_NAME_BLOCK_JM, "JS0_ACTIVE"); }},
+	    {GpuCounter::TilerCycles, [this] { return get_counter_value(MALI_NAME_BLOCK_TILER, "TILER_ACTIVE"); }},
+
+	    {GpuCounter::VertexComputeJobs, [this] { return get_counter_value(MALI_NAME_BLOCK_JM, "JS1_JOBS"); }},
+	    {GpuCounter::FragmentJobs, [this] { return get_counter_value(MALI_NAME_BLOCK_JM, "JS0_JOBS"); }},
+	    {GpuCounter::Pixels, [this] { return get_counter_value(MALI_NAME_BLOCK_JM, "JS0_TASKS") * 1024; }},
+
+	    {GpuCounter::Tiles, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "FRAG_PTILES"); }},
+	    {GpuCounter::TransactionEliminations, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "FRAG_TRANS_ELIM"); }},
+	    {GpuCounter::EarlyZTests, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "FRAG_QUADS_EZS_TEST"); }},
+	    {GpuCounter::EarlyZKilled, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "FRAG_QUADS_EZS_KILL"); }},
+	    {GpuCounter::LateZTests, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "FRAG_LZS_TEST"); }},
+	    {GpuCounter::LateZKilled, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "FRAG_LZS_KILL"); }},
+
+	    {GpuCounter::Instructions, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "EXEC_INSTR_FMA") + get_counter_value(MALI_NAME_BLOCK_SHADER, "EXEC_INSTR_CVT") + get_counter_value(MALI_NAME_BLOCK_SHADER, "EXEC_INSTR_SFU") + get_counter_value(MALI_NAME_BLOCK_SHADER, "EXEC_INSTR_MSG"); }},
+	    {GpuCounter::DivergedInstructions, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "EXEC_INSTR_DIVERGED"); }},
+
+	    {GpuCounter::ShaderCycles, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "EXEC_CORE_ACTIVE"); }},
+	    // The three units run in parallel so we can approximate cycles by taking the largest value. SFU instructions use 4 cycles per warp.
+	    {GpuCounter::ShaderArithmeticCycles, [this] { return std::max(get_counter_value(MALI_NAME_BLOCK_SHADER, "EXEC_INSTR_FMA"), std::max(get_counter_value(MALI_NAME_BLOCK_SHADER, "EXEC_INSTR_CVT"), 4 * get_counter_value(MALI_NAME_BLOCK_SHADER, "EXEC_INSTR_SFU"))); }},
+	    {GpuCounter::ShaderLoadStoreCycles, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "LS_MEM_READ_FULL") + get_counter_value(MALI_NAME_BLOCK_SHADER, "LS_MEM_WRITE_FULL") + get_counter_value(MALI_NAME_BLOCK_SHADER, "LS_MEM_READ_SHORT") + get_counter_value(MALI_NAME_BLOCK_SHADER, "LS_MEM_WRITE_SHORT") + get_counter_value(MALI_NAME_BLOCK_SHADER, "LS_MEM_ATOMIC"); }},
+	    {GpuCounter::ShaderTextureCycles, [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "TEX_FILT_NUM_OPERATIONS"); }},
+
+	    {GpuCounter::CacheReadLookups, [this] { return get_counter_value(MALI_NAME_BLOCK_MMU, "L2_READ_LOOKUP"); }},
+	    {GpuCounter::CacheWriteLookups, [this] { return get_counter_value(MALI_NAME_BLOCK_MMU, "L2_WRITE_LOOKUP"); }},
+	    {GpuCounter::ExternalMemoryReadAccesses, [this] { return get_counter_value(MALI_NAME_BLOCK_MMU, "L2_EXT_READ"); }},
+	    {GpuCounter::ExternalMemoryWriteAccesses, [this] { return get_counter_value(MALI_NAME_BLOCK_MMU, "L2_EXT_WRITE"); }},
+	    {GpuCounter::ExternalMemoryReadStalls, [this] { return get_counter_value(MALI_NAME_BLOCK_MMU, "L2_EXT_AR_STALL"); }},
+	    {GpuCounter::ExternalMemoryWriteStalls, [this] { return get_counter_value(MALI_NAME_BLOCK_MMU, "L2_EXT_W_STALL"); }},
+	    {GpuCounter::ExternalMemoryReadBytes, [this] { return get_counter_value(MALI_NAME_BLOCK_MMU, "L2_EXT_READ_BEATS") * 16; }},
+	    {GpuCounter::ExternalMemoryWriteBytes, [this] { return get_counter_value(MALI_NAME_BLOCK_MMU, "L2_EXT_WRITE_BEATS") * 16; }},
+	};
+
 	const std::unordered_map<GpuCounter, MaliValueGetter, GpuCounterHash> bifrost_mappings = {
 	    {GpuCounter::GpuCycles, [this] { return get_counter_value(MALI_NAME_BLOCK_JM, "GPU_ACTIVE"); }},
 	    {GpuCounter::VertexComputeCycles, [this] { return get_counter_value(MALI_NAME_BLOCK_JM, "JS1_ACTIVE"); }},
@@ -309,8 +345,14 @@
 				mappings_[GpuCounter::ShaderTextureCycles] = [this] { return get_counter_value(MALI_NAME_BLOCK_SHADER, "TEX_COORD_ISSUE"); };
 			case mali_userspace::PRODUCT_ID_TSIX:
 			case mali_userspace::PRODUCT_ID_TNOX:
-			default:
+			case mali_userspace::PRODUCT_ID_TGOX:
+			case mali_userspace::PRODUCT_ID_TDVX:
 				mappings_ = bifrost_mappings;
+			case mali_userspace::PRODUCT_ID_TNAXa:
+			case mali_userspace::PRODUCT_ID_TNAXb:
+			case mali_userspace::PRODUCT_ID_TTRX:
+			default:
+				mappings_ = valhall_mappings;
 				break;
 		}
 	}