)]}'
{
  "commit": "abe7c33b45288b407e6d001aad713183d4bab5c6",
  "tree": "a3dbd4094e3acef74967b4c48d839fba8c726b83",
  "parents": [
    "ee881e5d3312ea5396bddc37e8673b77bf549b4b"
  ],
  "author": {
    "name": "Claudiu Zissulescu",
    "email": "claziss@synopsys.com",
    "time": "Tue Nov 15 15:11:47 2016 +0100"
  },
  "committer": {
    "name": "Claudiu Zissulescu",
    "email": "claziss@synopsys.com",
    "time": "Tue Nov 29 11:29:18 2016 +0100"
  },
  "message": "[ARC] Add checking for LP_COUNT reg usage, improve error reporting.\n\ngas/\n2016-11-29  Claudiu Zissulescu  \u003cclaziss@synopsys.com\u003e\n\n\t* config/tc-arc.c (find_opcode_match): New function argument\n\terrmsg.\n\t(assemble_tokens): Collect and report the eventual error message\n\tfound during opcode matching process.\n\t* testsuite/gas/arc/lpcount-err.s: New file.\n\t* testsuite/gas/arc/add_s-err.s: Update error message.\n\nopcode/\n2016-11-29  Claudiu Zissulescu  \u003cclaziss@synopsys.com\u003e\n\n\t* arc-opc.c (insert_ra_chk): New function.\n\t(insert_rb_chk): Likewise.\n\t(insert_rad): Update text error message.\n\t(insert_rcd): Likewise.\n\t(insert_rhv2): Likewise.\n\t(insert_r0): Likewise.\n\t(insert_r1): Likewise.\n\t(insert_r2): Likewise.\n\t(insert_r3): Likewise.\n\t(insert_sp): Likewise.\n\t(insert_gp): Likewise.\n\t(insert_pcl): Likewise.\n\t(insert_blink): Likewise.\n\t(insert_ilink1): Likewise.\n\t(insert_ilink2): Likewise.\n\t(insert_ras): Likewise.\n\t(insert_rbs): Likewise.\n\t(insert_rcs): Likewise.\n\t(insert_simm3s): Likewise.\n\t(insert_rrange): Likewise.\n\t(insert_fpel): Likewise.\n\t(insert_blinkel): Likewise.\n\t(insert_pcel): Likewise.\n\t(insert_nps_3bit_dst): Likewise.\n\t(insert_nps_3bit_dst_short): Likewise.\n\t(insert_nps_3bit_src2_short): Likewise.\n\t(insert_nps_bitop_size_2b): Likewise.\n\t(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.\n\t(RA_CHK): Define.\n\t(RB): Adjust.\n\t(RB_CHK): Define.\n\t(RC): Adjust.\n\t* arc-dis.c (print_insn_arc): Add LOAD and STORE class.\n\t* arc-tbl.h (div, divu): All instructions are DIVREM class.\n\tChange first insn argument to check for LP_COUNT usage.\n\t(rem): Likewise.\n\t(ld, ldd): All instructions are LOAD class.  Change first insn\n\targument to check for LP_COUNT usage.\n\t(st, std): All instructions are STORE class.\n\t(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.\n\tChange first insn argument to check for LP_COUNT usage.\n\t(mov): All instructions are MOVE class.  Change first insn\n\targument to check for LP_COUNT usage.\n\ninclude/\n2016-11-29  Claudiu Zissulescu  \u003cclaziss@synopsys.com\u003e\n\n\t* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE\n\tinstruction classes.\n",
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