| /* ppc-opc.c -- PowerPC opcode list |
| Copyright (C) 1994-2016 Free Software Foundation, Inc. |
| Written by Ian Lance Taylor, Cygnus Support |
| |
| This file is part of the GNU opcodes library. |
| |
| This library is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| |
| It is distributed in the hope that it will be useful, but WITHOUT |
| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| License for more details. |
| |
| You should have received a copy of the GNU General Public License |
| along with this file; see the file COPYING. If not, write to the |
| Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
| MA 02110-1301, USA. */ |
| |
| #include "sysdep.h" |
| #include <stdio.h> |
| #include "opcode/ppc.h" |
| #include "opintl.h" |
| |
| /* This file holds the PowerPC opcode table. The opcode table |
| includes almost all of the extended instruction mnemonics. This |
| permits the disassembler to use them, and simplifies the assembler |
| logic, at the cost of increasing the table size. The table is |
| strictly constant data, so the compiler should be able to put it in |
| the .text section. |
| |
| This file also holds the operand table. All knowledge about |
| inserting operands into instructions and vice-versa is kept in this |
| file. */ |
| |
| /* Local insertion and extraction functions. */ |
| |
| static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_arx (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_ary (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_bat (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_bba (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_bdm (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_bdm (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_bdp (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_bdp (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_bo (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_bo (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_boe (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_boe (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_esync (unsigned long, long, ppc_cpu_t, const char **); |
| static unsigned long insert_dcmxs (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_dcmxs (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_dxd (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_dxd (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_dxdn (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_fxm (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_li20 (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **); |
| static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_mbe (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_mb6 (unsigned long, ppc_cpu_t, int *); |
| static long extract_nb (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **); |
| static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_nsi (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_oimm (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **); |
| static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **); |
| static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **); |
| static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **); |
| static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_rbs (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **); |
| static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_rx (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_ry (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_sh6 (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_sci8 (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_sci8n (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_sd4h (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_sd4w (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_spr (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_sprg (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_tbr (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_xt6 (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_xtq6 (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_xtq6 (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_xa6 (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_xb6 (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_xb6s (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_xc6 (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_xc6 (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_dm (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_vlesi (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_vlensi (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_vleui (unsigned long, ppc_cpu_t, int *); |
| static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **); |
| static long extract_vleil (unsigned long, ppc_cpu_t, int *); |
| |
| /* The operands table. |
| |
| The fields are bitm, shift, insert, extract, flags. |
| |
| We used to put parens around the various additions, like the one |
| for BA just below. However, that caused trouble with feeble |
| compilers with a limit on depth of a parenthesized expression, like |
| (reportedly) the compiler in Microsoft Developer Studio 5. So we |
| omit the parens, since the macros are never used in a context where |
| the addition will be ambiguous. */ |
| |
| const struct powerpc_operand powerpc_operands[] = |
| { |
| /* The zero index is used to indicate the end of the list of |
| operands. */ |
| #define UNUSED 0 |
| { 0, 0, NULL, NULL, 0 }, |
| |
| /* The BA field in an XL form instruction. */ |
| #define BA UNUSED + 1 |
| /* The BI field in a B form or XL form instruction. */ |
| #define BI BA |
| #define BI_MASK (0x1f << 16) |
| { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, |
| |
| /* The BA field in an XL form instruction when it must be the same |
| as the BT field in the same instruction. */ |
| #define BAT BA + 1 |
| { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, |
| |
| /* The BB field in an XL form instruction. */ |
| #define BB BAT + 1 |
| #define BB_MASK (0x1f << 11) |
| { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, |
| |
| /* The BB field in an XL form instruction when it must be the same |
| as the BA field in the same instruction. */ |
| #define BBA BB + 1 |
| /* The VB field in a VX form instruction when it must be the same |
| as the VA field in the same instruction. */ |
| #define VBA BBA |
| { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, |
| |
| /* The BD field in a B form instruction. The lower two bits are |
| forced to zero. */ |
| #define BD BBA + 1 |
| { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| |
| /* The BD field in a B form instruction when absolute addressing is |
| used. */ |
| #define BDA BD + 1 |
| { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
| |
| /* The BD field in a B form instruction when the - modifier is used. |
| This sets the y bit of the BO field appropriately. */ |
| #define BDM BDA + 1 |
| { 0xfffc, 0, insert_bdm, extract_bdm, |
| PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| |
| /* The BD field in a B form instruction when the - modifier is used |
| and absolute address is used. */ |
| #define BDMA BDM + 1 |
| { 0xfffc, 0, insert_bdm, extract_bdm, |
| PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
| |
| /* The BD field in a B form instruction when the + modifier is used. |
| This sets the y bit of the BO field appropriately. */ |
| #define BDP BDMA + 1 |
| { 0xfffc, 0, insert_bdp, extract_bdp, |
| PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| |
| /* The BD field in a B form instruction when the + modifier is used |
| and absolute addressing is used. */ |
| #define BDPA BDP + 1 |
| { 0xfffc, 0, insert_bdp, extract_bdp, |
| PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
| |
| /* The BF field in an X or XL form instruction. */ |
| #define BF BDPA + 1 |
| /* The CRFD field in an X form instruction. */ |
| #define CRFD BF |
| /* The CRD field in an XL form instruction. */ |
| #define CRD BF |
| { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, |
| |
| /* The BF field in an X or XL form instruction. */ |
| #define BFF BF + 1 |
| { 0x7, 23, NULL, NULL, 0 }, |
| |
| /* An optional BF field. This is used for comparison instructions, |
| in which an omitted BF field is taken as zero. */ |
| #define OBF BFF + 1 |
| { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, |
| |
| /* The BFA field in an X or XL form instruction. */ |
| #define BFA OBF + 1 |
| { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, |
| |
| /* The BO field in a B form instruction. Certain values are |
| illegal. */ |
| #define BO BFA + 1 |
| #define BO_MASK (0x1f << 21) |
| { 0x1f, 21, insert_bo, extract_bo, 0 }, |
| |
| /* The BO field in a B form instruction when the + or - modifier is |
| used. This is like the BO field, but it must be even. */ |
| #define BOE BO + 1 |
| { 0x1e, 21, insert_boe, extract_boe, 0 }, |
| |
| /* The RM field in an X form instruction. */ |
| #define RM BOE + 1 |
| { 0x3, 11, NULL, NULL, 0 }, |
| |
| #define BH RM + 1 |
| { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The BT field in an X or XL form instruction. */ |
| #define BT BH + 1 |
| { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, |
| |
| /* The BI16 field in a BD8 form instruction. */ |
| #define BI16 BT + 1 |
| { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, |
| |
| /* The BI32 field in a BD15 form instruction. */ |
| #define BI32 BI16 + 1 |
| { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, |
| |
| /* The BO32 field in a BD15 form instruction. */ |
| #define BO32 BI32 + 1 |
| { 0x3, 20, NULL, NULL, 0 }, |
| |
| /* The B8 field in a BD8 form instruction. */ |
| #define B8 BO32 + 1 |
| { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| |
| /* The B15 field in a BD15 form instruction. The lowest bit is |
| forced to zero. */ |
| #define B15 B8 + 1 |
| { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| |
| /* The B24 field in a BD24 form instruction. The lowest bit is |
| forced to zero. */ |
| #define B24 B15 + 1 |
| { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| |
| /* The condition register number portion of the BI field in a B form |
| or XL form instruction. This is used for the extended |
| conditional branch mnemonics, which set the lower two bits of the |
| BI field. This field is optional. */ |
| #define CR B24 + 1 |
| { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, |
| |
| /* The CRB field in an X form instruction. */ |
| #define CRB CR + 1 |
| /* The MB field in an M form instruction. */ |
| #define MB CRB |
| #define MB_MASK (0x1f << 6) |
| { 0x1f, 6, NULL, NULL, 0 }, |
| |
| /* The CRD32 field in an XL form instruction. */ |
| #define CRD32 CRB + 1 |
| { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, |
| |
| /* The CRFS field in an X form instruction. */ |
| #define CRFS CRD32 + 1 |
| { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, |
| |
| #define CRS CRFS + 1 |
| { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, |
| |
| /* The CT field in an X form instruction. */ |
| #define CT CRS + 1 |
| /* The MO field in an mbar instruction. */ |
| #define MO CT |
| { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The D field in a D form instruction. This is a displacement off |
| a register, and implies that the next operand is a register in |
| parentheses. */ |
| #define D CT + 1 |
| { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
| |
| /* The D8 field in a D form instruction. This is a displacement off |
| a register, and implies that the next operand is a register in |
| parentheses. */ |
| #define D8 D + 1 |
| { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
| |
| /* The DCMX field in an X form instruction. */ |
| #define DCMX D8 + 1 |
| { 0x7f, 16, NULL, NULL, 0 }, |
| |
| /* The split DCMX field in an X form instruction. */ |
| #define DCMXS DCMX + 1 |
| { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, |
| |
| /* The DQ field in a DQ form instruction. This is like D, but the |
| lower four bits are forced to zero. */ |
| #define DQ DCMXS + 1 |
| { 0xfff0, 0, NULL, NULL, |
| PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, |
| |
| /* The DS field in a DS form instruction. This is like D, but the |
| lower two bits are forced to zero. */ |
| #define DS DQ + 1 |
| { 0xfffc, 0, NULL, NULL, |
| PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, |
| |
| /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits |
| unsigned imediate */ |
| #define DUIS DS + 1 |
| #define BHRBE DUIS |
| { 0x3ff, 11, NULL, NULL, 0 }, |
| |
| /* The split D field in a DX form instruction. */ |
| #define DXD DUIS + 1 |
| { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, |
| PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, |
| |
| /* The split ND field in a DX form instruction. |
| This is the same as the DX field, only negated. */ |
| #define NDXD DXD + 1 |
| { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, |
| PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, |
| |
| /* The E field in a wrteei instruction. */ |
| /* And the W bit in the pair singles instructions. */ |
| /* And the ST field in a VX form instruction. */ |
| #define E NDXD + 1 |
| #define PSW E |
| #define ST E |
| { 0x1, 15, NULL, NULL, 0 }, |
| |
| /* The FL1 field in a POWER SC form instruction. */ |
| #define FL1 E + 1 |
| /* The U field in an X form instruction. */ |
| #define U FL1 |
| { 0xf, 12, NULL, NULL, 0 }, |
| |
| /* The FL2 field in a POWER SC form instruction. */ |
| #define FL2 FL1 + 1 |
| { 0x7, 2, NULL, NULL, 0 }, |
| |
| /* The FLM field in an XFL form instruction. */ |
| #define FLM FL2 + 1 |
| { 0xff, 17, NULL, NULL, 0 }, |
| |
| /* The FRA field in an X or A form instruction. */ |
| #define FRA FLM + 1 |
| #define FRA_MASK (0x1f << 16) |
| { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, |
| |
| /* The FRAp field of DFP instructions. */ |
| #define FRAp FRA + 1 |
| { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, |
| |
| /* The FRB field in an X or A form instruction. */ |
| #define FRB FRAp + 1 |
| #define FRB_MASK (0x1f << 11) |
| { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, |
| |
| /* The FRBp field of DFP instructions. */ |
| #define FRBp FRB + 1 |
| { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, |
| |
| /* The FRC field in an A form instruction. */ |
| #define FRC FRBp + 1 |
| #define FRC_MASK (0x1f << 6) |
| { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, |
| |
| /* The FRS field in an X form instruction or the FRT field in a D, X |
| or A form instruction. */ |
| #define FRS FRC + 1 |
| #define FRT FRS |
| { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, |
| |
| /* The FRSp field of stfdp or the FRTp field of lfdp and DFP |
| instructions. */ |
| #define FRSp FRS + 1 |
| #define FRTp FRSp |
| { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, |
| |
| /* The FXM field in an XFX instruction. */ |
| #define FXM FRSp + 1 |
| { 0xff, 12, insert_fxm, extract_fxm, 0 }, |
| |
| /* Power4 version for mfcr. */ |
| #define FXM4 FXM + 1 |
| { 0xff, 12, insert_fxm, extract_fxm, |
| PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
| /* If the FXM4 operand is ommitted, use the sentinel value -1. */ |
| { -1, -1, NULL, NULL, 0}, |
| |
| /* The IMM20 field in an LI instruction. */ |
| #define IMM20 FXM4 + 2 |
| { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, |
| |
| /* The L field in a D or X form instruction. */ |
| #define L IMM20 + 1 |
| { 0x1, 21, NULL, NULL, 0 }, |
| |
| /* The optional L field in tlbie and tlbiel instructions. */ |
| #define LOPT L + 1 |
| /* The R field in a HTM X form instruction. */ |
| #define HTM_R LOPT |
| { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The optional (for 32-bit) L field in cmp[l][i] instructions. */ |
| #define L32OPT LOPT + 1 |
| { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 }, |
| |
| /* The L field in dcbf instruction. */ |
| #define L2OPT L32OPT + 1 |
| { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The LEV field in a POWER SVC form instruction. */ |
| #define SVC_LEV L2OPT + 1 |
| { 0x7f, 5, NULL, NULL, 0 }, |
| |
| /* The LEV field in an SC form instruction. */ |
| #define LEV SVC_LEV + 1 |
| { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The LI field in an I form instruction. The lower two bits are |
| forced to zero. */ |
| #define LI LEV + 1 |
| { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, |
| |
| /* The LI field in an I form instruction when used as an absolute |
| address. */ |
| #define LIA LI + 1 |
| { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, |
| |
| /* The LS or WC field in an X (sync or wait) form instruction. */ |
| #define LS LIA + 1 |
| #define WC LS |
| { 0x3, 21, insert_ls, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The ME field in an M form instruction. */ |
| #define ME LS + 1 |
| #define ME_MASK (0x1f << 1) |
| { 0x1f, 1, NULL, NULL, 0 }, |
| |
| /* The MB and ME fields in an M form instruction expressed a single |
| operand which is a bitmask indicating which bits to select. This |
| is a two operand form using PPC_OPERAND_NEXT. See the |
| description in opcode/ppc.h for what this means. */ |
| #define MBE ME + 1 |
| { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, |
| { -1, 0, insert_mbe, extract_mbe, 0 }, |
| |
| /* The MB or ME field in an MD or MDS form instruction. The high |
| bit is wrapped to the low end. */ |
| #define MB6 MBE + 2 |
| #define ME6 MB6 |
| #define MB6_MASK (0x3f << 5) |
| { 0x3f, 5, insert_mb6, extract_mb6, 0 }, |
| |
| /* The NB field in an X form instruction. The value 32 is stored as |
| 0. */ |
| #define NB MB6 + 1 |
| { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, |
| |
| /* The NBI field in an lswi instruction, which has special value |
| restrictions. The value 32 is stored as 0. */ |
| #define NBI NB + 1 |
| { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, |
| |
| /* The NSI field in a D form instruction. This is the same as the |
| SI field, only negated. */ |
| #define NSI NBI + 1 |
| { 0xffff, 0, insert_nsi, extract_nsi, |
| PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
| |
| /* The NSI field in a D form instruction when we accept a wide range |
| of positive values. */ |
| #define NSISIGNOPT NSI + 1 |
| { 0xffff, 0, insert_nsi, extract_nsi, |
| PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
| |
| /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ |
| #define RA NSISIGNOPT + 1 |
| #define RA_MASK (0x1f << 16) |
| { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, |
| |
| /* As above, but 0 in the RA field means zero, not r0. */ |
| #define RA0 RA + 1 |
| { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, |
| |
| /* The RA field in the DQ form lq or an lswx instruction, which have special |
| value restrictions. */ |
| #define RAQ RA0 + 1 |
| #define RAX RAQ |
| { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, |
| |
| /* The RA field in a D or X form instruction which is an updating |
| load, which means that the RA field may not be zero and may not |
| equal the RT field. */ |
| #define RAL RAQ + 1 |
| { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, |
| |
| /* The RA field in an lmw instruction, which has special value |
| restrictions. */ |
| #define RAM RAL + 1 |
| { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, |
| |
| /* The RA field in a D or X form instruction which is an updating |
| store or an updating floating point load, which means that the RA |
| field may not be zero. */ |
| #define RAS RAM + 1 |
| { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, |
| |
| /* The RA field of the tlbwe, dccci and iccci instructions, |
| which are optional. */ |
| #define RAOPT RAS + 1 |
| { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
| |
| /* The RB field in an X, XO, M, or MDS form instruction. */ |
| #define RB RAOPT + 1 |
| #define RB_MASK (0x1f << 11) |
| { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, |
| |
| /* The RB field in an X form instruction when it must be the same as |
| the RS field in the instruction. This is used for extended |
| mnemonics like mr. */ |
| #define RBS RB + 1 |
| { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, |
| |
| /* The RB field in an lswx instruction, which has special value |
| restrictions. */ |
| #define RBX RBS + 1 |
| { 0x1f, 11, insert_rbx, NULL, PPC_OPERAND_GPR }, |
| |
| /* The RB field of the dccci and iccci instructions, which are optional. */ |
| #define RBOPT RBX + 1 |
| { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
| |
| /* The RC register field in an maddld, maddhd or maddhdu instruction. */ |
| #define RC RBOPT + 1 |
| { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, |
| |
| /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form |
| instruction or the RT field in a D, DS, X, XFX or XO form |
| instruction. */ |
| #define RS RC + 1 |
| #define RT RS |
| #define RT_MASK (0x1f << 21) |
| #define RD RS |
| { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, |
| |
| /* The RS and RT fields of the DS form stq and DQ form lq instructions, |
| which have special value restrictions. */ |
| #define RSQ RS + 1 |
| #define RTQ RSQ |
| { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, |
| |
| /* The RS field of the tlbwe instruction, which is optional. */ |
| #define RSO RSQ + 1 |
| #define RTO RSO |
| { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, |
| |
| /* The RX field of the SE_RR form instruction. */ |
| #define RX RSO + 1 |
| { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, |
| |
| /* The ARX field of the SE_RR form instruction. */ |
| #define ARX RX + 1 |
| { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, |
| |
| /* The RY field of the SE_RR form instruction. */ |
| #define RY ARX + 1 |
| #define RZ RY |
| { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, |
| |
| /* The ARY field of the SE_RR form instruction. */ |
| #define ARY RY + 1 |
| { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, |
| |
| /* The SCLSCI8 field in a D form instruction. */ |
| #define SCLSCI8 ARY + 1 |
| { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, |
| |
| /* The SCLSCI8N field in a D form instruction. This is the same as the |
| SCLSCI8 field, only negated. */ |
| #define SCLSCI8N SCLSCI8 + 1 |
| { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, |
| PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, |
| |
| /* The SD field of the SD4 form instruction. */ |
| #define SE_SD SCLSCI8N + 1 |
| { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, |
| |
| /* The SD field of the SD4 form instruction, for halfword. */ |
| #define SE_SDH SE_SD + 1 |
| { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS }, |
| |
| /* The SD field of the SD4 form instruction, for word. */ |
| #define SE_SDW SE_SDH + 1 |
| { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS }, |
| |
| /* The SH field in an X or M form instruction. */ |
| #define SH SE_SDW + 1 |
| #define SH_MASK (0x1f << 11) |
| /* The other UIMM field in a EVX form instruction. */ |
| #define EVUIMM SH |
| /* The FC field in an atomic X form instruction. */ |
| #define FC SH |
| { 0x1f, 11, NULL, NULL, 0 }, |
| |
| /* The SI field in a HTM X form instruction. */ |
| #define HTM_SI SH + 1 |
| { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, |
| |
| /* The SH field in an MD form instruction. This is split. */ |
| #define SH6 HTM_SI + 1 |
| #define SH6_MASK ((0x1f << 11) | (1 << 1)) |
| { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, |
| |
| /* The SH field of the tlbwe instruction, which is optional. */ |
| #define SHO SH6 + 1 |
| { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The SI field in a D form instruction. */ |
| #define SI SHO + 1 |
| { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, |
| |
| /* The SI field in a D form instruction when we accept a wide range |
| of positive values. */ |
| #define SISIGNOPT SI + 1 |
| { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
| |
| /* The SI8 field in a D form instruction. */ |
| #define SI8 SISIGNOPT + 1 |
| { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, |
| |
| /* The SPR field in an XFX form instruction. This is flipped--the |
| lower 5 bits are stored in the upper 5 and vice- versa. */ |
| #define SPR SI8 + 1 |
| #define PMR SPR |
| #define TMR SPR |
| #define SPR_MASK (0x3ff << 11) |
| { 0x3ff, 11, insert_spr, extract_spr, 0 }, |
| |
| /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ |
| #define SPRBAT SPR + 1 |
| #define SPRBAT_MASK (0x3 << 17) |
| { 0x3, 17, NULL, NULL, 0 }, |
| |
| /* The SPRG register number in an XFX form m[ft]sprg instruction. */ |
| #define SPRG SPRBAT + 1 |
| { 0x1f, 16, insert_sprg, extract_sprg, 0 }, |
| |
| /* The SR field in an X form instruction. */ |
| #define SR SPRG + 1 |
| /* The 4-bit UIMM field in a VX form instruction. */ |
| #define UIMM4 SR |
| { 0xf, 16, NULL, NULL, 0 }, |
| |
| /* The STRM field in an X AltiVec form instruction. */ |
| #define STRM SR + 1 |
| /* The T field in a tlbilx form instruction. */ |
| #define T STRM |
| /* The L field in wclr instructions. */ |
| #define L2 STRM |
| { 0x3, 21, NULL, NULL, 0 }, |
| |
| /* The ESYNC field in an X (sync) form instruction. */ |
| #define ESYNC STRM + 1 |
| { 0xf, 16, insert_esync, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The SV field in a POWER SC form instruction. */ |
| #define SV ESYNC + 1 |
| { 0x3fff, 2, NULL, NULL, 0 }, |
| |
| /* The TBR field in an XFX form instruction. This is like the SPR |
| field, but it is optional. */ |
| #define TBR SV + 1 |
| { 0x3ff, 11, insert_tbr, extract_tbr, |
| PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
| /* If the TBR operand is ommitted, use the value 268. */ |
| { -1, 268, NULL, NULL, 0}, |
| |
| /* The TO field in a D or X form instruction. */ |
| #define TO TBR + 2 |
| #define DUI TO |
| #define TO_MASK (0x1f << 21) |
| { 0x1f, 21, NULL, NULL, 0 }, |
| |
| /* The UI field in a D form instruction. */ |
| #define UI TO + 1 |
| { 0xffff, 0, NULL, NULL, 0 }, |
| |
| #define UISIGNOPT UI + 1 |
| { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, |
| |
| /* The IMM field in an SE_IM5 instruction. */ |
| #define UI5 UISIGNOPT + 1 |
| { 0x1f, 4, NULL, NULL, 0 }, |
| |
| /* The OIMM field in an SE_OIM5 instruction. */ |
| #define OIMM5 UI5 + 1 |
| { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, |
| |
| /* The UI7 field in an SE_LI instruction. */ |
| #define UI7 OIMM5 + 1 |
| { 0x7f, 4, NULL, NULL, 0 }, |
| |
| /* The VA field in a VA, VX or VXR form instruction. */ |
| #define VA UI7 + 1 |
| { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, |
| |
| /* The VB field in a VA, VX or VXR form instruction. */ |
| #define VB VA + 1 |
| { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, |
| |
| /* The VC field in a VA form instruction. */ |
| #define VC VB + 1 |
| { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, |
| |
| /* The VD or VS field in a VA, VX, VXR or X form instruction. */ |
| #define VD VC + 1 |
| #define VS VD |
| { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, |
| |
| /* The SIMM field in a VX form instruction, and TE in Z form. */ |
| #define SIMM VD + 1 |
| #define TE SIMM |
| { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, |
| |
| /* The UIMM field in a VX form instruction. */ |
| #define UIMM SIMM + 1 |
| #define DCTL UIMM |
| { 0x1f, 16, NULL, NULL, 0 }, |
| |
| /* The 3-bit UIMM field in a VX form instruction. */ |
| #define UIMM3 UIMM + 1 |
| { 0x7, 16, NULL, NULL, 0 }, |
| |
| /* The 6-bit UIM field in a X form instruction. */ |
| #define UIM6 UIMM3 + 1 |
| { 0x3f, 16, NULL, NULL, 0 }, |
| |
| /* The SIX field in a VX form instruction. */ |
| #define SIX UIM6 + 1 |
| { 0xf, 11, NULL, NULL, 0 }, |
| |
| /* The PS field in a VX form instruction. */ |
| #define PS SIX + 1 |
| { 0x1, 9, NULL, NULL, 0 }, |
| |
| /* The SHB field in a VA form instruction. */ |
| #define SHB PS + 1 |
| { 0xf, 6, NULL, NULL, 0 }, |
| |
| /* The other UIMM field in a half word EVX form instruction. */ |
| #define EVUIMM_2 SHB + 1 |
| { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, |
| |
| /* The other UIMM field in a word EVX form instruction. */ |
| #define EVUIMM_4 EVUIMM_2 + 1 |
| { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, |
| |
| /* The other UIMM field in a double EVX form instruction. */ |
| #define EVUIMM_8 EVUIMM_4 + 1 |
| { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, |
| |
| /* The WS or DRM field in an X form instruction. */ |
| #define WS EVUIMM_8 + 1 |
| #define DRM WS |
| { 0x7, 11, NULL, NULL, 0 }, |
| |
| /* PowerPC paired singles extensions. */ |
| /* W bit in the pair singles instructions for x type instructions. */ |
| #define PSWM WS + 1 |
| /* The BO16 field in a BD8 form instruction. */ |
| #define BO16 PSWM |
| { 0x1, 10, 0, 0, 0 }, |
| |
| /* IDX bits for quantization in the pair singles instructions. */ |
| #define PSQ PSWM + 1 |
| { 0x7, 12, 0, 0, 0 }, |
| |
| /* IDX bits for quantization in the pair singles x-type instructions. */ |
| #define PSQM PSQ + 1 |
| { 0x7, 7, 0, 0, 0 }, |
| |
| /* Smaller D field for quantization in the pair singles instructions. */ |
| #define PSD PSQM + 1 |
| { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, |
| |
| /* The L field in an mtmsrd or A form instruction or R or W in an X form. */ |
| #define A_L PSD + 1 |
| #define W A_L |
| #define X_R A_L |
| { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The RMC or CY field in a Z23 form instruction. */ |
| #define RMC A_L + 1 |
| #define CY RMC |
| { 0x3, 9, NULL, NULL, 0 }, |
| |
| #define R RMC + 1 |
| { 0x1, 16, NULL, NULL, 0 }, |
| |
| #define RIC R + 1 |
| { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| #define PRS RIC + 1 |
| { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| #define SP PRS + 1 |
| { 0x3, 19, NULL, NULL, 0 }, |
| |
| #define S SP + 1 |
| { 0x1, 20, NULL, NULL, 0 }, |
| |
| /* The S field in a XL form instruction. */ |
| #define SXL S + 1 |
| { 0x1, 11, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, |
| /* If the SXL operand is ommitted, use the value 1. */ |
| { -1, 1, NULL, NULL, 0}, |
| |
| /* SH field starting at bit position 16. */ |
| #define SH16 SXL + 2 |
| /* The DCM and DGM fields in a Z form instruction. */ |
| #define DCM SH16 |
| #define DGM DCM |
| { 0x3f, 10, NULL, NULL, 0 }, |
| |
| /* The EH field in larx instruction. */ |
| #define EH SH16 + 1 |
| { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The L field in an mtfsf or XFL form instruction. */ |
| /* The A field in a HTM X form instruction. */ |
| #define XFL_L EH + 1 |
| #define HTM_A XFL_L |
| { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, |
| |
| /* Xilinx APU related masks and macros */ |
| #define FCRT XFL_L + 1 |
| #define FCRT_MASK (0x1f << 21) |
| { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, |
| |
| /* Xilinx FSL related masks and macros */ |
| #define FSL FCRT + 1 |
| #define FSL_MASK (0x1f << 11) |
| { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, |
| |
| /* Xilinx UDI related masks and macros */ |
| #define URT FSL + 1 |
| { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, |
| |
| #define URA URT + 1 |
| { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, |
| |
| #define URB URA + 1 |
| { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, |
| |
| #define URC URB + 1 |
| { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, |
| |
| /* The VLESIMM field in a D form instruction. */ |
| #define VLESIMM URC + 1 |
| { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, |
| PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
| |
| /* The VLENSIMM field in a D form instruction. */ |
| #define VLENSIMM VLESIMM + 1 |
| { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, |
| PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, |
| |
| /* The VLEUIMM field in a D form instruction. */ |
| #define VLEUIMM VLENSIMM + 1 |
| { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, |
| |
| /* The VLEUIMML field in a D form instruction. */ |
| #define VLEUIMML VLEUIMM + 1 |
| { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, |
| |
| /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ |
| #define XS6 VLEUIMML + 1 |
| #define XT6 XS6 |
| { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, |
| |
| /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
| #define XSQ6 XT6 + 1 |
| #define XTQ6 XSQ6 |
| { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, |
| |
| /* The XA field in an XX3 form instruction. This is split. */ |
| #define XA6 XTQ6 + 1 |
| { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, |
| |
| /* The XB field in an XX2 or XX3 form instruction. This is split. */ |
| #define XB6 XA6 + 1 |
| { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, |
| |
| /* The XB field in an XX3 form instruction when it must be the same as |
| the XA field in the instruction. This is used in extended mnemonics |
| like xvmovdp. This is split. */ |
| #define XB6S XB6 + 1 |
| { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, |
| |
| /* The XC field in an XX4 form instruction. This is split. */ |
| #define XC6 XB6S + 1 |
| { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, |
| |
| /* The DM or SHW field in an XX3 form instruction. */ |
| #define DM XC6 + 1 |
| #define SHW DM |
| { 0x3, 8, NULL, NULL, 0 }, |
| |
| /* The DM field in an extended mnemonic XX3 form instruction. */ |
| #define DMEX DM + 1 |
| { 0x3, 8, insert_dm, extract_dm, 0 }, |
| |
| /* The UIM field in an XX2 form instruction. */ |
| #define UIM DMEX + 1 |
| /* The 2-bit UIMM field in a VX form instruction. */ |
| #define UIMM2 UIM |
| /* The 2-bit L field in a darn instruction. */ |
| #define LRAND UIM |
| { 0x3, 16, NULL, NULL, 0 }, |
| |
| #define ERAT_T UIM + 1 |
| { 0x7, 21, NULL, NULL, 0 }, |
| |
| #define IH ERAT_T + 1 |
| { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, |
| |
| /* The 8-bit IMM8 field in a XX1 form instruction. */ |
| #define IMM8 IH + 1 |
| { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT }, |
| }; |
| |
| const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) |
| / sizeof (powerpc_operands[0])); |
| |
| /* The functions used to insert and extract complicated operands. */ |
| |
| /* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ |
| |
| static unsigned long |
| insert_arx (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| if (value >= 8 && value < 24) |
| return insn | ((value - 8) & 0xf); |
| else |
| { |
| *errmsg = _("invalid register"); |
| return 0; |
| } |
| } |
| |
| static long |
| extract_arx (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return (insn & 0xf) + 8; |
| } |
| |
| static unsigned long |
| insert_ary (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| if (value >= 8 && value < 24) |
| return insn | (((value - 8) & 0xf) << 4); |
| else |
| { |
| *errmsg = _("invalid register"); |
| return 0; |
| } |
| } |
| |
| static long |
| extract_ary (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn >> 4) & 0xf) + 8; |
| } |
| |
| static unsigned long |
| insert_rx (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| if (value >= 0 && value < 8) |
| return insn | value; |
| else if (value >= 24 && value <= 31) |
| return insn | (value - 16); |
| else |
| { |
| *errmsg = _("invalid register"); |
| return 0; |
| } |
| } |
| |
| static long |
| extract_rx (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| int value = insn & 0xf; |
| if (value >= 0 && value < 8) |
| return value; |
| else |
| return value + 16; |
| } |
| |
| static unsigned long |
| insert_ry (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| if (value >= 0 && value < 8) |
| return insn | (value << 4); |
| else if (value >= 24 && value <= 31) |
| return insn | ((value - 16) << 4); |
| else |
| { |
| *errmsg = _("invalid register"); |
| return 0; |
| } |
| } |
| |
| static long |
| extract_ry (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| int value = (insn >> 4) & 0xf; |
| if (value >= 0 && value < 8) |
| return value; |
| else |
| return value + 16; |
| } |
| |
| /* The BA field in an XL form instruction when it must be the same as |
| the BT field in the same instruction. This operand is marked FAKE. |
| The insertion function just copies the BT field into the BA field, |
| and the extraction function just checks that the fields are the |
| same. */ |
| |
| static unsigned long |
| insert_bat (unsigned long insn, |
| long value ATTRIBUTE_UNUSED, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | (((insn >> 21) & 0x1f) << 16); |
| } |
| |
| static long |
| extract_bat (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid) |
| { |
| if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) |
| *invalid = 1; |
| return 0; |
| } |
| |
| /* The BB field in an XL form instruction when it must be the same as |
| the BA field in the same instruction. This operand is marked FAKE. |
| The insertion function just copies the BA field into the BB field, |
| and the extraction function just checks that the fields are the |
| same. */ |
| |
| static unsigned long |
| insert_bba (unsigned long insn, |
| long value ATTRIBUTE_UNUSED, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | (((insn >> 16) & 0x1f) << 11); |
| } |
| |
| static long |
| extract_bba (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid) |
| { |
| if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) |
| *invalid = 1; |
| return 0; |
| } |
| |
| /* The BD field in a B form instruction when the - modifier is used. |
| This modifier means that the branch is not expected to be taken. |
| For chips built to versions of the architecture prior to version 2 |
| (ie. not Power4 compatible), we set the y bit of the BO field to 1 |
| if the offset is negative. When extracting, we require that the y |
| bit be 1 and that the offset be positive, since if the y bit is 0 |
| we just want to print the normal form of the instruction. |
| Power4 compatible targets use two bits, "a", and "t", instead of |
| the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, |
| "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 |
| in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 |
| for branch on CTR. We only handle the taken/not-taken hint here. |
| Note that we don't relax the conditions tested here when |
| disassembling with -Many because insns using extract_bdm and |
| extract_bdp always occur in pairs. One or the other will always |
| be valid. */ |
| |
| #define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) |
| |
| static unsigned long |
| insert_bdm (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| if ((dialect & ISA_V2) == 0) |
| { |
| if ((value & 0x8000) != 0) |
| insn |= 1 << 21; |
| } |
| else |
| { |
| if ((insn & (0x14 << 21)) == (0x04 << 21)) |
| insn |= 0x02 << 21; |
| else if ((insn & (0x14 << 21)) == (0x10 << 21)) |
| insn |= 0x08 << 21; |
| } |
| return insn | (value & 0xfffc); |
| } |
| |
| static long |
| extract_bdm (unsigned long insn, |
| ppc_cpu_t dialect, |
| int *invalid) |
| { |
| if ((dialect & ISA_V2) == 0) |
| { |
| if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) |
| *invalid = 1; |
| } |
| else |
| { |
| if ((insn & (0x17 << 21)) != (0x06 << 21) |
| && (insn & (0x1d << 21)) != (0x18 << 21)) |
| *invalid = 1; |
| } |
| |
| return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
| } |
| |
| /* The BD field in a B form instruction when the + modifier is used. |
| This is like BDM, above, except that the branch is expected to be |
| taken. */ |
| |
| static unsigned long |
| insert_bdp (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| if ((dialect & ISA_V2) == 0) |
| { |
| if ((value & 0x8000) == 0) |
| insn |= 1 << 21; |
| } |
| else |
| { |
| if ((insn & (0x14 << 21)) == (0x04 << 21)) |
| insn |= 0x03 << 21; |
| else if ((insn & (0x14 << 21)) == (0x10 << 21)) |
| insn |= 0x09 << 21; |
| } |
| return insn | (value & 0xfffc); |
| } |
| |
| static long |
| extract_bdp (unsigned long insn, |
| ppc_cpu_t dialect, |
| int *invalid) |
| { |
| if ((dialect & ISA_V2) == 0) |
| { |
| if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) |
| *invalid = 1; |
| } |
| else |
| { |
| if ((insn & (0x17 << 21)) != (0x07 << 21) |
| && (insn & (0x1d << 21)) != (0x19 << 21)) |
| *invalid = 1; |
| } |
| |
| return ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
| } |
| |
| static inline int |
| valid_bo_pre_v2 (long value) |
| { |
| /* Certain encodings have bits that are required to be zero. |
| These are (z must be zero, y may be anything): |
| 0000y |
| 0001y |
| 001zy |
| 0100y |
| 0101y |
| 011zy |
| 1z00y |
| 1z01y |
| 1z1zz |
| */ |
| if ((value & 0x14) == 0) |
| return 1; |
| else if ((value & 0x14) == 0x4) |
| return (value & 0x2) == 0; |
| else if ((value & 0x14) == 0x10) |
| return (value & 0x8) == 0; |
| else |
| return value == 0x14; |
| } |
| |
| static inline int |
| valid_bo_post_v2 (long value) |
| { |
| /* Certain encodings have bits that are required to be zero. |
| These are (z must be zero, a & t may be anything): |
| 0000z |
| 0001z |
| 001at |
| 0100z |
| 0101z |
| 011at |
| 1a00t |
| 1a01t |
| 1z1zz |
| */ |
| if ((value & 0x14) == 0) |
| return (value & 0x1) == 0; |
| else if ((value & 0x14) == 0x14) |
| return value == 0x14; |
| else |
| return 1; |
| } |
| |
| /* Check for legal values of a BO field. */ |
| |
| static int |
| valid_bo (long value, ppc_cpu_t dialect, int extract) |
| { |
| int valid_y = valid_bo_pre_v2 (value); |
| int valid_at = valid_bo_post_v2 (value); |
| |
| /* When disassembling with -Many, accept either encoding on the |
| second pass through opcodes. */ |
| if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) |
| return valid_y || valid_at; |
| if ((dialect & ISA_V2) == 0) |
| return valid_y; |
| else |
| return valid_at; |
| } |
| |
| /* The BO field in a B form instruction. Warn about attempts to set |
| the field to an illegal value. */ |
| |
| static unsigned long |
| insert_bo (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect, |
| const char **errmsg) |
| { |
| if (!valid_bo (value, dialect, 0)) |
| *errmsg = _("invalid conditional option"); |
| else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) |
| *errmsg = _("invalid counter access"); |
| return insn | ((value & 0x1f) << 21); |
| } |
| |
| static long |
| extract_bo (unsigned long insn, |
| ppc_cpu_t dialect, |
| int *invalid) |
| { |
| long value; |
| |
| value = (insn >> 21) & 0x1f; |
| if (!valid_bo (value, dialect, 1)) |
| *invalid = 1; |
| return value; |
| } |
| |
| /* The BO field in a B form instruction when the + or - modifier is |
| used. This is like the BO field, but it must be even. When |
| extracting it, we force it to be even. */ |
| |
| static unsigned long |
| insert_boe (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect, |
| const char **errmsg) |
| { |
| if (!valid_bo (value, dialect, 0)) |
| *errmsg = _("invalid conditional option"); |
| else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4)) |
| *errmsg = _("invalid counter access"); |
| else if ((value & 1) != 0) |
| *errmsg = _("attempt to set y bit when using + or - modifier"); |
| |
| return insn | ((value & 0x1f) << 21); |
| } |
| |
| static long |
| extract_boe (unsigned long insn, |
| ppc_cpu_t dialect, |
| int *invalid) |
| { |
| long value; |
| |
| value = (insn >> 21) & 0x1f; |
| if (!valid_bo (value, dialect, 1)) |
| *invalid = 1; |
| return value & 0x1e; |
| } |
| |
| /* The DCMX field in a X form instruction when the field is split |
| into separate DC, DM and DX fields. */ |
| |
| static unsigned long |
| insert_dcmxs (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3) | (value & 0x40); |
| } |
| |
| static long |
| extract_dcmxs (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); |
| } |
| |
| /* The D field in a DX form instruction when the field is split |
| into separate D0, D1 and D2 fields. */ |
| |
| static unsigned long |
| insert_dxd (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | (value & 0xffc1) | ((value & 0x3e) << 15); |
| } |
| |
| static long |
| extract_dxd (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| unsigned long dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); |
| return (dxd ^ 0x8000) - 0x8000; |
| } |
| |
| static unsigned long |
| insert_dxdn (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insert_dxd (insn, -value, dialect, errmsg); |
| } |
| |
| static long |
| extract_dxdn (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return -extract_dxd (insn, dialect, invalid); |
| } |
| |
| /* FXM mask in mfcr and mtcrf instructions. */ |
| |
| static unsigned long |
| insert_fxm (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect, |
| const char **errmsg) |
| { |
| /* If we're handling the mfocrf and mtocrf insns ensure that exactly |
| one bit of the mask field is set. */ |
| if ((insn & (1 << 20)) != 0) |
| { |
| if (value == 0 || (value & -value) != value) |
| { |
| *errmsg = _("invalid mask field"); |
| value = 0; |
| } |
| } |
| |
| /* If only one bit of the FXM field is set, we can use the new form |
| of the instruction, which is faster. Unlike the Power4 branch hint |
| encoding, this is not backward compatible. Do not generate the |
| new form unless -mpower4 has been given, or -many and the two |
| operand form of mfcr was used. */ |
| else if (value > 0 |
| && (value & -value) == value |
| && ((dialect & PPC_OPCODE_POWER4) != 0 |
| || ((dialect & PPC_OPCODE_ANY) != 0 |
| && (insn & (0x3ff << 1)) == 19 << 1))) |
| insn |= 1 << 20; |
| |
| /* Any other value on mfcr is an error. */ |
| else if ((insn & (0x3ff << 1)) == 19 << 1) |
| { |
| /* A value of -1 means we used the one operand form of |
| mfcr which is valid. */ |
| if (value != -1) |
| *errmsg = _("invalid mfcr mask"); |
| value = 0; |
| } |
| |
| return insn | ((value & 0xff) << 12); |
| } |
| |
| static long |
| extract_fxm (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid) |
| { |
| long mask = (insn >> 12) & 0xff; |
| |
| /* Is this a Power4 insn? */ |
| if ((insn & (1 << 20)) != 0) |
| { |
| /* Exactly one bit of MASK should be set. */ |
| if (mask == 0 || (mask & -mask) != mask) |
| *invalid = 1; |
| } |
| |
| /* Check that non-power4 form of mfcr has a zero MASK. */ |
| else if ((insn & (0x3ff << 1)) == 19 << 1) |
| { |
| if (mask != 0) |
| *invalid = 1; |
| else |
| mask = -1; |
| } |
| |
| return mask; |
| } |
| |
| static unsigned long |
| insert_li20 (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0xf0000) >> 5) | ((value & 0x0f800) << 5) | (value & 0x7ff); |
| } |
| |
| static long |
| extract_li20 (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000; |
| |
| return ext |
| | (((insn >> 11) & 0xf) << 16) |
| | (((insn >> 17) & 0xf) << 12) |
| | (((insn >> 16) & 0x1) << 11) |
| | (insn & 0x7ff); |
| } |
| |
| /* The 2-bit L field in a SYNC or WC field in a WAIT instruction. |
| For SYNC, some L values are reserved: |
| * Value 3 is reserved on newer server cpus. |
| * Values 2 and 3 are reserved on all other cpus. */ |
| |
| static unsigned long |
| insert_ls (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect, |
| const char **errmsg) |
| { |
| /* For SYNC, some L values are illegal. */ |
| if (((insn >> 1) & 0x3ff) == 598) |
| { |
| long max_lvalue = (dialect & PPC_OPCODE_POWER4) ? 2 : 1; |
| if (value > max_lvalue) |
| { |
| *errmsg = _("illegal L operand value"); |
| return insn; |
| } |
| } |
| |
| return insn | ((value & 0x3) << 21); |
| } |
| |
| /* The 4-bit E field in a sync instruction that accepts 2 operands. |
| If ESYNC is non-zero, then the L field must be either 0 or 1 and |
| the complement of ESYNC-bit2. */ |
| |
| static unsigned long |
| insert_esync (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect, |
| const char **errmsg) |
| { |
| unsigned long ls = (insn >> 21) & 0x03; |
| |
| if (value == 0) |
| { |
| if (((dialect & PPC_OPCODE_E6500) != 0 && ls > 1) |
| || ((dialect & PPC_OPCODE_POWER9) != 0 && ls > 2)) |
| *errmsg = _("illegal L operand value"); |
| return insn; |
| } |
| |
| if ((ls & ~0x1) |
| || (((value >> 1) & 0x1) ^ ls) == 0) |
| *errmsg = _("incompatible L operand value"); |
| |
| return insn | ((value & 0xf) << 16); |
| } |
| |
| /* The MB and ME fields in an M form instruction expressed as a single |
| operand which is itself a bitmask. The extraction function always |
| marks it as invalid, since we never want to recognize an |
| instruction which uses a field of this type. */ |
| |
| static unsigned long |
| insert_mbe (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| unsigned long uval, mask; |
| int mb, me, mx, count, last; |
| |
| uval = value; |
| |
| if (uval == 0) |
| { |
| *errmsg = _("illegal bitmask"); |
| return insn; |
| } |
| |
| mb = 0; |
| me = 32; |
| if ((uval & 1) != 0) |
| last = 1; |
| else |
| last = 0; |
| count = 0; |
| |
| /* mb: location of last 0->1 transition */ |
| /* me: location of last 1->0 transition */ |
| /* count: # transitions */ |
| |
| for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) |
| { |
| if ((uval & mask) && !last) |
| { |
| ++count; |
| mb = mx; |
| last = 1; |
| } |
| else if (!(uval & mask) && last) |
| { |
| ++count; |
| me = mx; |
| last = 0; |
| } |
| } |
| if (me == 0) |
| me = 32; |
| |
| if (count != 2 && (count != 0 || ! last)) |
| *errmsg = _("illegal bitmask"); |
| |
| return insn | (mb << 6) | ((me - 1) << 1); |
| } |
| |
| static long |
| extract_mbe (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid) |
| { |
| long ret; |
| int mb, me; |
| int i; |
| |
| *invalid = 1; |
| |
| mb = (insn >> 6) & 0x1f; |
| me = (insn >> 1) & 0x1f; |
| if (mb < me + 1) |
| { |
| ret = 0; |
| for (i = mb; i <= me; i++) |
| ret |= 1L << (31 - i); |
| } |
| else if (mb == me + 1) |
| ret = ~0; |
| else /* (mb > me + 1) */ |
| { |
| ret = ~0; |
| for (i = me + 1; i < mb; i++) |
| ret &= ~(1L << (31 - i)); |
| } |
| return ret; |
| } |
| |
| /* The MB or ME field in an MD or MDS form instruction. The high bit |
| is wrapped to the low end. */ |
| |
| static unsigned long |
| insert_mb6 (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x1f) << 6) | (value & 0x20); |
| } |
| |
| static long |
| extract_mb6 (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn >> 6) & 0x1f) | (insn & 0x20); |
| } |
| |
| /* The NB field in an X form instruction. The value 32 is stored as |
| 0. */ |
| |
| static long |
| extract_nb (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| long ret; |
| |
| ret = (insn >> 11) & 0x1f; |
| if (ret == 0) |
| ret = 32; |
| return ret; |
| } |
| |
| /* The NB field in an lswi instruction, which has special value |
| restrictions. The value 32 is stored as 0. */ |
| |
| static unsigned long |
| insert_nbi (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| long rtvalue = (insn & RT_MASK) >> 21; |
| long ravalue = (insn & RA_MASK) >> 16; |
| |
| if (value == 0) |
| value = 32; |
| if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 |
| : ravalue)) |
| *errmsg = _("address register in load range"); |
| return insn | ((value & 0x1f) << 11); |
| } |
| |
| /* The NSI field in a D form instruction. This is the same as the SI |
| field, only negated. The extraction function always marks it as |
| invalid, since we never want to recognize an instruction which uses |
| a field of this type. */ |
| |
| static unsigned long |
| insert_nsi (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | (-value & 0xffff); |
| } |
| |
| static long |
| extract_nsi (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid) |
| { |
| *invalid = 1; |
| return -(((insn & 0xffff) ^ 0x8000) - 0x8000); |
| } |
| |
| /* The RA field in a D or X form instruction which is an updating |
| load, which means that the RA field may not be zero and may not |
| equal the RT field. */ |
| |
| static unsigned long |
| insert_ral (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| if (value == 0 |
| || (unsigned long) value == ((insn >> 21) & 0x1f)) |
| *errmsg = "invalid register operand when updating"; |
| return insn | ((value & 0x1f) << 16); |
| } |
| |
| /* The RA field in an lmw instruction, which has special value |
| restrictions. */ |
| |
| static unsigned long |
| insert_ram (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| if ((unsigned long) value >= ((insn >> 21) & 0x1f)) |
| *errmsg = _("index register in load range"); |
| return insn | ((value & 0x1f) << 16); |
| } |
| |
| /* The RA field in the DQ form lq or an lswx instruction, which have special |
| value restrictions. */ |
| |
| static unsigned long |
| insert_raq (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| long rtvalue = (insn & RT_MASK) >> 21; |
| |
| if (value == rtvalue) |
| *errmsg = _("source and target register operands must be different"); |
| return insn | ((value & 0x1f) << 16); |
| } |
| |
| /* The RA field in a D or X form instruction which is an updating |
| store or an updating floating point load, which means that the RA |
| field may not be zero. */ |
| |
| static unsigned long |
| insert_ras (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| if (value == 0) |
| *errmsg = _("invalid register operand when updating"); |
| return insn | ((value & 0x1f) << 16); |
| } |
| |
| /* The RB field in an X form instruction when it must be the same as |
| the RS field in the instruction. This is used for extended |
| mnemonics like mr. This operand is marked FAKE. The insertion |
| function just copies the BT field into the BA field, and the |
| extraction function just checks that the fields are the same. */ |
| |
| static unsigned long |
| insert_rbs (unsigned long insn, |
| long value ATTRIBUTE_UNUSED, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | (((insn >> 21) & 0x1f) << 11); |
| } |
| |
| static long |
| extract_rbs (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid) |
| { |
| if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) |
| *invalid = 1; |
| return 0; |
| } |
| |
| /* The RB field in an lswx instruction, which has special value |
| restrictions. */ |
| |
| static unsigned long |
| insert_rbx (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| long rtvalue = (insn & RT_MASK) >> 21; |
| |
| if (value == rtvalue) |
| *errmsg = _("source and target register operands must be different"); |
| return insn | ((value & 0x1f) << 11); |
| } |
| |
| /* The SCI8 field is made up of SCL and {U,N}I8 fields. */ |
| static unsigned long |
| insert_sci8 (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| unsigned int fill_scale = 0; |
| unsigned long ui8 = value; |
| |
| if ((ui8 & 0xffffff00) == 0) |
| ; |
| else if ((ui8 & 0xffffff00) == 0xffffff00) |
| fill_scale = 0x400; |
| else if ((ui8 & 0xffff00ff) == 0) |
| { |
| fill_scale = 1 << 8; |
| ui8 >>= 8; |
| } |
| else if ((ui8 & 0xffff00ff) == 0xffff00ff) |
| { |
| fill_scale = 0x400 | (1 << 8); |
| ui8 >>= 8; |
| } |
| else if ((ui8 & 0xff00ffff) == 0) |
| { |
| fill_scale = 2 << 8; |
| ui8 >>= 16; |
| } |
| else if ((ui8 & 0xff00ffff) == 0xff00ffff) |
| { |
| fill_scale = 0x400 | (2 << 8); |
| ui8 >>= 16; |
| } |
| else if ((ui8 & 0x00ffffff) == 0) |
| { |
| fill_scale = 3 << 8; |
| ui8 >>= 24; |
| } |
| else if ((ui8 & 0x00ffffff) == 0x00ffffff) |
| { |
| fill_scale = 0x400 | (3 << 8); |
| ui8 >>= 24; |
| } |
| else |
| { |
| *errmsg = _("illegal immediate value"); |
| ui8 = 0; |
| } |
| |
| return insn | fill_scale | (ui8 & 0xff); |
| } |
| |
| static long |
| extract_sci8 (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| int fill = insn & 0x400; |
| int scale_factor = (insn & 0x300) >> 5; |
| long value = (insn & 0xff) << scale_factor; |
| |
| if (fill != 0) |
| value |= ~((long) 0xff << scale_factor); |
| return value; |
| } |
| |
| static unsigned long |
| insert_sci8n (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect, |
| const char **errmsg) |
| { |
| return insert_sci8 (insn, -value, dialect, errmsg); |
| } |
| |
| static long |
| extract_sci8n (unsigned long insn, |
| ppc_cpu_t dialect, |
| int *invalid) |
| { |
| return -extract_sci8 (insn, dialect, invalid); |
| } |
| |
| static unsigned long |
| insert_sd4h (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x1e) << 7); |
| } |
| |
| static long |
| extract_sd4h (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn >> 8) & 0xf) << 1; |
| } |
| |
| static unsigned long |
| insert_sd4w (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x3c) << 6); |
| } |
| |
| static long |
| extract_sd4w (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn >> 8) & 0xf) << 2; |
| } |
| |
| static unsigned long |
| insert_oimm (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | (((value - 1) & 0x1f) << 4); |
| } |
| |
| static long |
| extract_oimm (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn >> 4) & 0x1f) + 1; |
| } |
| |
| /* The SH field in an MD form instruction. This is split. */ |
| |
| static unsigned long |
| insert_sh6 (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| /* SH6 operand in the rldixor instructions. */ |
| if (PPC_OP (insn) == 4) |
| return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 5); |
| else |
| return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
| } |
| |
| static long |
| extract_sh6 (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| /* SH6 operand in the rldixor instructions. */ |
| if (PPC_OP (insn) == 4) |
| return ((insn >> 6) & 0x1f) | ((insn << 5) & 0x20); |
| else |
| return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); |
| } |
| |
| /* The SPR field in an XFX form instruction. This is flipped--the |
| lower 5 bits are stored in the upper 5 and vice- versa. */ |
| |
| static unsigned long |
| insert_spr (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
| } |
| |
| static long |
| extract_spr (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
| } |
| |
| /* Some dialects have 8 SPRG registers instead of the standard 4. */ |
| #define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) |
| |
| static unsigned long |
| insert_sprg (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect, |
| const char **errmsg) |
| { |
| if (value > 7 |
| || (value > 3 && (dialect & ALLOW8_SPRG) == 0)) |
| *errmsg = _("invalid sprg number"); |
| |
| /* If this is mfsprg4..7 then use spr 260..263 which can be read in |
| user mode. Anything else must use spr 272..279. */ |
| if (value <= 3 || (insn & 0x100) != 0) |
| value |= 0x10; |
| |
| return insn | ((value & 0x17) << 16); |
| } |
| |
| static long |
| extract_sprg (unsigned long insn, |
| ppc_cpu_t dialect, |
| int *invalid) |
| { |
| unsigned long val = (insn >> 16) & 0x1f; |
| |
| /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 |
| If not BOOKE, 405 or VLE, then both use only 272..275. */ |
| if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) |
| || (val - 0x10 > 7 && (insn & 0x100) != 0) |
| || val <= 3 |
| || (val & 8) != 0) |
| *invalid = 1; |
| return val & 7; |
| } |
| |
| /* The TBR field in an XFX instruction. This is just like SPR, but it |
| is optional. */ |
| |
| static unsigned long |
| insert_tbr (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| if (value != 268 && value != 269) |
| *errmsg = _("invalid tbr number"); |
| return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); |
| } |
| |
| static long |
| extract_tbr (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid) |
| { |
| long ret; |
| |
| ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); |
| if (ret != 268 && ret != 269) |
| *invalid = 1; |
| return ret; |
| } |
| |
| /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ |
| |
| static unsigned long |
| insert_xt6 (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); |
| } |
| |
| static long |
| extract_xt6 (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); |
| } |
| |
| /* The XT and XS fields in an DQ form VSX instruction. This is split. */ |
| static unsigned long |
| insert_xtq6 (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); |
| } |
| |
| static long |
| extract_xtq6 (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); |
| } |
| |
| /* The XA field in an XX3 form instruction. This is split. */ |
| |
| static unsigned long |
| insert_xa6 (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); |
| } |
| |
| static long |
| extract_xa6 (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); |
| } |
| |
| /* The XB field in an XX3 form instruction. This is split. */ |
| |
| static unsigned long |
| insert_xb6 (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); |
| } |
| |
| static long |
| extract_xb6 (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); |
| } |
| |
| /* The XB field in an XX3 form instruction when it must be the same as |
| the XA field in the instruction. This is used for extended |
| mnemonics like xvmovdp. This operand is marked FAKE. The insertion |
| function just copies the XA field into the XB field, and the |
| extraction function just checks that the fields are the same. */ |
| |
| static unsigned long |
| insert_xb6s (unsigned long insn, |
| long value ATTRIBUTE_UNUSED, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1); |
| } |
| |
| static long |
| extract_xb6s (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid) |
| { |
| if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) |
| || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1))) |
| *invalid = 1; |
| return 0; |
| } |
| |
| /* The XC field in an XX4 form instruction. This is split. */ |
| |
| static unsigned long |
| insert_xc6 (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); |
| } |
| |
| static long |
| extract_xc6 (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); |
| } |
| |
| static unsigned long |
| insert_dm (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg) |
| { |
| if (value != 0 && value != 1) |
| *errmsg = _("invalid constant"); |
| return insn | (((value) ? 3 : 0) << 8); |
| } |
| |
| static long |
| extract_dm (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid) |
| { |
| long value; |
| |
| value = (insn >> 8) & 3; |
| if (value != 0 && value != 3) |
| *invalid = 1; |
| return (value) ? 1 : 0; |
| } |
| |
| /* The VLESIMM field in an I16A form instruction. This is split. */ |
| |
| static unsigned long |
| insert_vlesi (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
| } |
| |
| static long |
| extract_vlesi (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
| value = (value ^ 0x8000) - 0x8000; |
| return value; |
| } |
| |
| static unsigned long |
| insert_vlensi (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| value = -value; |
| return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
| } |
| static long |
| extract_vlensi (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
| value = (value ^ 0x8000) - 0x8000; |
| /* Don't use for disassembly. */ |
| *invalid = 1; |
| return -value; |
| } |
| |
| /* The VLEUIMM field in an I16A form instruction. This is split. */ |
| |
| static unsigned long |
| insert_vleui (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0xf800) << 10) | (value & 0x7ff); |
| } |
| |
| static long |
| extract_vleui (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn >> 10) & 0xf800) | (insn & 0x7ff); |
| } |
| |
| /* The VLEUIMML field in an I16L form instruction. This is split. */ |
| |
| static unsigned long |
| insert_vleil (unsigned long insn, |
| long value, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| const char **errmsg ATTRIBUTE_UNUSED) |
| { |
| return insn | ((value & 0xf800) << 5) | (value & 0x7ff); |
| } |
| |
| static long |
| extract_vleil (unsigned long insn, |
| ppc_cpu_t dialect ATTRIBUTE_UNUSED, |
| int *invalid ATTRIBUTE_UNUSED) |
| { |
| return ((insn >> 5) & 0xf800) | (insn & 0x7ff); |
| } |
| |
| |
| /* Macros used to form opcodes. */ |
| |
| /* The main opcode. */ |
| #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) |
| #define OP_MASK OP (0x3f) |
| |
| /* The main opcode combined with a trap code in the TO field of a D |
| form instruction. Used for extended mnemonics for the trap |
| instructions. */ |
| #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) |
| #define OPTO_MASK (OP_MASK | TO_MASK) |
| |
| /* The main opcode combined with a comparison size bit in the L field |
| of a D form or X form instruction. Used for extended mnemonics for |
| the comparison instructions. */ |
| #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) |
| #define OPL_MASK OPL (0x3f,1) |
| |
| /* The main opcode combined with an update code in D form instruction. |
| Used for extended mnemonics for VLE memory instructions. */ |
| #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8)) |
| #define OPVUP_MASK OPVUP (0x3f, 0xff) |
| |
| /* The main opcode combined with an update code and the RT fields specified in |
| D form instruction. Used for VLE volatile context save/restore |
| instructions. */ |
| #define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21)) |
| #define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f) |
| |
| /* An A form instruction. */ |
| #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) |
| #define A_MASK A (0x3f, 0x1f, 1) |
| |
| /* An A_MASK with the FRB field fixed. */ |
| #define AFRB_MASK (A_MASK | FRB_MASK) |
| |
| /* An A_MASK with the FRC field fixed. */ |
| #define AFRC_MASK (A_MASK | FRC_MASK) |
| |
| /* An A_MASK with the FRA and FRC fields fixed. */ |
| #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) |
| |
| /* An AFRAFRC_MASK, but with L bit clear. */ |
| #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) |
| |
| /* A B form instruction. */ |
| #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) |
| #define B_MASK B (0x3f, 1, 1) |
| |
| /* A BD8 form instruction. This is a 16-bit instruction. */ |
| #define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8)) |
| #define BD8_MASK BD8 (0x3f, 1, 1) |
| |
| /* Another BD8 form instruction. This is a 16-bit instruction. */ |
| #define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11) |
| #define BD8IO_MASK BD8IO (0x1f) |
| |
| /* A BD8 form instruction for simplified mnemonics. */ |
| #define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) |
| /* A mask that excludes BO32 and BI32. */ |
| #define EBD8IO1_MASK 0xf800 |
| /* A mask that includes BO32 and excludes BI32. */ |
| #define EBD8IO2_MASK 0xfc00 |
| /* A mask that include BO32 AND BI32. */ |
| #define EBD8IO3_MASK 0xff00 |
| |
| /* A BD15 form instruction. */ |
| #define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1)) |
| #define BD15_MASK BD15 (0x3f, 0xf, 1) |
| |
| /* A BD15 form instruction for extended conditional branch mnemonics. */ |
| #define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1) |
| #define EBD15_MASK 0xfff00001 |
| |
| /* A BD15 form instruction for extended conditional branch mnemonics with BI. */ |
| #define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \ |
| | (((aa) & 0xf) << 22) \ |
| | (((bo) & 0x3) << 20) \ |
| | (((bi) & 0x3) << 16) \ |
| | ((lk) & 1) |
| #define EBD15BI_MASK 0xfff30001 |
| |
| /* A BD24 form instruction. */ |
| #define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1)) |
| #define BD24_MASK BD24 (0x3f, 1, 1) |
| |
| /* A B form instruction setting the BO field. */ |
| #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) |
| #define BBO_MASK BBO (0x3f, 0x1f, 1, 1) |
| |
| /* A BBO_MASK with the y bit of the BO field removed. This permits |
| matching a conditional branch regardless of the setting of the y |
| bit. Similarly for the 'at' bits used for power4 branch hints. */ |
| #define Y_MASK (((unsigned long) 1) << 21) |
| #define AT1_MASK (((unsigned long) 3) << 21) |
| #define AT2_MASK (((unsigned long) 9) << 21) |
| #define BBOY_MASK (BBO_MASK &~ Y_MASK) |
| #define BBOAT_MASK (BBO_MASK &~ AT1_MASK) |
| |
| /* A B form instruction setting the BO field and the condition bits of |
| the BI field. */ |
| #define BBOCB(op, bo, cb, aa, lk) \ |
| (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) |
| #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) |
| |
| /* A BBOCB_MASK with the y bit of the BO field removed. */ |
| #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) |
| #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) |
| #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) |
| |
| /* A BBOYCB_MASK in which the BI field is fixed. */ |
| #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) |
| #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) |
| |
| /* A VLE C form instruction. */ |
| #define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1)) |
| #define C_LK_MASK C_LK(0x7fff, 1) |
| #define C(x) ((((unsigned long)(x)) & 0xffff)) |
| #define C_MASK C(0xffff) |
| |
| /* An Context form instruction. */ |
| #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) |
| #define CTX_MASK CTX(0x3f, 0x7) |
| |
| /* An User Context form instruction. */ |
| #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) |
| #define UCTX_MASK UCTX(0x3f, 0x1f) |
| |
| /* The main opcode mask with the RA field clear. */ |
| #define DRA_MASK (OP_MASK | RA_MASK) |
| |
| /* A DQ form VSX instruction. */ |
| #define DQX(op, xop) (OP (op) | ((xop) & 0x7)) |
| #define DQX_MASK DQX (0x3f, 7) |
| |
| /* A DS form instruction. */ |
| #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) |
| #define DS_MASK DSO (0x3f, 3) |
| |
| /* An DX form instruction. */ |
| #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
| #define DX_MASK DX (0x3f, 0x1f) |
| |
| /* An EVSEL form instruction. */ |
| #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) |
| #define EVSEL_MASK EVSEL(0x3f, 0xff) |
| |
| /* An IA16 form instruction. */ |
| #define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) |
| #define IA16_MASK IA16(0x3f, 0x1f) |
| |
| /* An I16A form instruction. */ |
| #define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) |
| #define I16A_MASK I16A(0x3f, 0x1f) |
| |
| /* An I16L form instruction. */ |
| #define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11) |
| #define I16L_MASK I16L(0x3f, 0x1f) |
| |
| /* An IM7 form instruction. */ |
| #define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11) |
| #define IM7_MASK IM7(0x1f) |
| |
| /* An M form instruction. */ |
| #define M(op, rc) (OP (op) | ((rc) & 1)) |
| #define M_MASK M (0x3f, 1) |
| |
| /* An LI20 form instruction. */ |
| #define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15) |
| #define LI20_MASK LI20(0x3f, 0x1) |
| |
| /* An M form instruction with the ME field specified. */ |
| #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) |
| |
| /* An M_MASK with the MB and ME fields fixed. */ |
| #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) |
| |
| /* An M_MASK with the SH and ME fields fixed. */ |
| #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) |
| |
| /* An MD form instruction. */ |
| #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) |
| #define MD_MASK MD (0x3f, 0x7, 1) |
| |
| /* An MD_MASK with the MB field fixed. */ |
| #define MDMB_MASK (MD_MASK | MB6_MASK) |
| |
| /* An MD_MASK with the SH field fixed. */ |
| #define MDSH_MASK (MD_MASK | SH6_MASK) |
| |
| /* An MDS form instruction. */ |
| #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) |
| #define MDS_MASK MDS (0x3f, 0xf, 1) |
| |
| /* An MDS_MASK with the MB field fixed. */ |
| #define MDSMB_MASK (MDS_MASK | MB6_MASK) |
| |
| /* An SC form instruction. */ |
| #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) |
| #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) |
| |
| /* An SCI8 form instruction. */ |
| #define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11)) |
| #define SCI8_MASK SCI8(0x3f, 0x1f) |
| |
| /* An SCI8 form instruction. */ |
| #define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23)) |
| #define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) |
| |
| /* An SD4 form instruction. This is a 16-bit instruction. */ |
| #define SD4(op) ((((unsigned long)(op)) & 0xf) << 12) |
| #define SD4_MASK SD4(0xf) |
| |
| /* An SE_IM5 form instruction. This is a 16-bit instruction. */ |
| #define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9)) |
| #define SE_IM5_MASK SE_IM5(0x3f, 1) |
| |
| /* An SE_R form instruction. This is a 16-bit instruction. */ |
| #define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4)) |
| #define SE_R_MASK SE_R(0x3f, 0x3f) |
| |
| /* An SE_RR form instruction. This is a 16-bit instruction. */ |
| #define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8)) |
| #define SE_RR_MASK SE_RR(0x3f, 3) |
| |
| /* A VX form instruction. */ |
| #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) |
| |
| /* The mask for an VX form instruction. */ |
| #define VX_MASK VX(0x3f, 0x7ff) |
| |
| /* A VX_MASK with the VA field fixed. */ |
| #define VXVA_MASK (VX_MASK | (0x1f << 16)) |
| |
| /* A VX_MASK with the VB field fixed. */ |
| #define VXVB_MASK (VX_MASK | (0x1f << 11)) |
| |
| /* A VX_MASK with the VA and VB fields fixed. */ |
| #define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) |
| |
| /* A VX_MASK with the VD and VA fields fixed. */ |
| #define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) |
| |
| /* A VX_MASK with a UIMM4 field. */ |
| #define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) |
| |
| /* A VX_MASK with a UIMM3 field. */ |
| #define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) |
| |
| /* A VX_MASK with a UIMM2 field. */ |
| #define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) |
| |
| /* A VX_MASK with a PS field. */ |
| #define VXPS_MASK (VX_MASK & ~(0x1 << 9)) |
| |
| /* A VX_MASK with the VA field fixed with a PS field. */ |
| #define VXVAPS_MASK ((VX_MASK | (0x1f << 16)) & ~(0x1 << 9)) |
| |
| /* A VA form instruction. */ |
| #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) |
| |
| /* The mask for an VA form instruction. */ |
| #define VXA_MASK VXA(0x3f, 0x3f) |
| |
| /* A VXA_MASK with a SHB field. */ |
| #define VXASHB_MASK (VXA_MASK | (1 << 10)) |
| |
| /* A VXR form instruction. */ |
| #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) |
| |
| /* The mask for a VXR form instruction. */ |
| #define VXR_MASK VXR(0x3f, 0x3ff, 1) |
| |
| /* A VX form instruction with a VA tertiary opcode. */ |
| #define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) |
| |
| #define VXASH(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) |
| #define VXASH_MASK VXASH (0x3f, 0x1f) |
| |
| /* An X form instruction. */ |
| #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) |
| |
| /* A X form instruction for Quad-Precision FP Instructions. */ |
| #define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) |
| |
| /* An EX form instruction. */ |
| #define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) |
| |
| /* The mask for an EX form instruction. */ |
| #define EX_MASK EX (0x3f, 0x7ff) |
| |
| /* An XX2 form instruction. */ |
| #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2)) |
| |
| /* A XX2 form instruction with the VA bits specified. */ |
| #define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) |
| |
| /* An XX3 form instruction. */ |
| #define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) |
| |
| /* An XX3 form instruction with the RC bit specified. */ |
| #define XX3RC(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | ((((unsigned long)(xop)) & 0x7f) << 3)) |
| |
| /* An XX4 form instruction. */ |
| #define XX4(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3) << 4)) |
| |
| /* A Z form instruction. */ |
| #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) |
| |
| /* An X form instruction with the RC bit specified. */ |
| #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) |
| |
| /* A X form instruction for Quad-Precision FP Instructions with RC bit. */ |
| #define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) |
| |
| /* An X form instruction with the RA bits specified as two ops. */ |
| #define XMMF(op, xop, mop0, mop1) (X ((op), (xop)) | ((mop0) & 3) << 19 | ((mop1) & 7) << 16) |
| |
| /* A Z form instruction with the RC bit specified. */ |
| #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) |
| |
| /* The mask for an X form instruction. */ |
| #define X_MASK XRC (0x3f, 0x3ff, 1) |
| |
| /* The mask for an X form instruction with the BF bits specified. */ |
| #define XBF_MASK (X_MASK | (3 << 21)) |
| |
| /* An X form wait instruction with everything filled in except the WC field. */ |
| #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
| |
| /* The mask for an XX1 form instruction. */ |
| #define XX1_MASK X (0x3f, 0x3ff) |
| |
| /* An XX1_MASK with the RB field fixed. */ |
| #define XX1RB_MASK (XX1_MASK | RB_MASK) |
| |
| /* The mask for an XX2 form instruction. */ |
| #define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) |
| |
| /* The mask for an XX2 form instruction with the UIM bits specified. */ |
| #define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) |
| |
| /* The mask for an XX2 form instruction with the 4 UIM bits specified. */ |
| #define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) |
| |
| /* The mask for an XX2 form instruction with the BF bits specified. */ |
| #define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) |
| |
| /* The mask for an XX2 form instruction with the BF and DCMX bits specified. */ |
| #define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) |
| |
| /* The mask for an XX2 form instruction with a split DCMX bits specified. */ |
| #define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) |
| |
| /* The mask for an XX3 form instruction. */ |
| #define XX3_MASK XX3 (0x3f, 0xff) |
| |
| /* The mask for an XX3 form instruction with the BF bits specified. */ |
| #define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) |
| |
| /* The mask for an XX3 form instruction with the DM or SHW bits specified. */ |
| #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) |
| #define XX3SHW_MASK XX3DM_MASK |
| |
| /* The mask for an XX4 form instruction. */ |
| #define XX4_MASK XX4 (0x3f, 0x3) |
| |
| /* An X form wait instruction with everything filled in except the WC field. */ |
| #define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) |
| |
| /* The mask for an XMMF form instruction. */ |
| #define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) |
| |
| /* The mask for a Z form instruction. */ |
| #define Z_MASK ZRC (0x3f, 0x1ff, 1) |
| #define Z2_MASK ZRC (0x3f, 0xff, 1) |
| |
| /* An X_MASK with the RA/VA field fixed. */ |
| #define XRA_MASK (X_MASK | RA_MASK) |
| #define XVA_MASK XRA_MASK |
| |
| /* An XRA_MASK with the A_L/W field clear. */ |
| #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16)) |
| #define XRLA_MASK XWRA_MASK |
| |
| /* An X_MASK with the RB field fixed. */ |
| #define XRB_MASK (X_MASK | RB_MASK) |
| |
| /* An X_MASK with the RT field fixed. */ |
| #define XRT_MASK (X_MASK | RT_MASK) |
| |
| /* An XRT_MASK mask with the L bits clear. */ |
| #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) |
| |
| /* An X_MASK with the RA and RB fields fixed. */ |
| #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) |
| |
| /* An XBF_MASK with the RA and RB fields fixed. */ |
| #define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) |
| |
| /* An XRARB_MASK, but with the L bit clear. */ |
| #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) |
| |
| /* An XRARB_MASK, but with the L bits in a darn instruction clear. */ |
| #define XLRAND_MASK (XRARB_MASK & ~((unsigned long) 3 << 16)) |
| |
| /* An X_MASK with the RT and RA fields fixed. */ |
| #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) |
| |
| /* An X_MASK with the RT and RB fields fixed. */ |
| #define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) |
| |
| /* An XRTRA_MASK, but with L bit clear. */ |
| #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) |
| |
| /* An X_MASK with the RT, RA and RB fields fixed. */ |
| #define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) |
| |
| /* An XRTRARB_MASK, but with L bit clear. */ |
| #define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21)) |
| |
| /* An XRTRARB_MASK, but with A bit clear. */ |
| #define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25)) |
| |
| /* An XRTRARB_MASK, but with BF bits clear. */ |
| #define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23)) |
| |
| /* An X form instruction with the L bit specified. */ |
| #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) |
| |
| /* An X form instruction with the L bits specified. */ |
| #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) |
| |
| /* An X form instruction with the L bit and RC bit specified. */ |
| #define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21)) |
| |
| /* An X form instruction with RT fields specified */ |
| #define XRT(op, xop, rt) (X ((op), (xop)) \ |
| | ((((unsigned long)(rt)) & 0x1f) << 21)) |
| |
| /* An X form instruction with RT and RA fields specified */ |
| #define XRTRA(op, xop, rt, ra) (X ((op), (xop)) \ |
| | ((((unsigned long)(rt)) & 0x1f) << 21) \ |
| | ((((unsigned long)(ra)) & 0x1f) << 16)) |
| |
| /* The mask for an X form comparison instruction. */ |
| #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) |
| |
| /* The mask for an X form comparison instruction with the L field |
| fixed. */ |
| #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) |
| |
| /* An X form trap instruction with the TO field specified. */ |
| #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) |
| #define XTO_MASK (X_MASK | TO_MASK) |
| |
| /* An X form tlb instruction with the SH field specified. */ |
| #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) |
| #define XTLB_MASK (X_MASK | SH_MASK) |
| |
| /* An X form sync instruction. */ |
| #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) |
| |
| /* An X form sync instruction with everything filled in except the LS field. */ |
| #define XSYNC_MASK (0xff9fffff) |
| |
| /* An X form sync instruction with everything filled in except the L and E fields. */ |
| #define XSYNCLE_MASK (0xff90ffff) |
| |
| /* An X_MASK, but with the EH bit clear. */ |
| #define XEH_MASK (X_MASK & ~((unsigned long )1)) |
| |
| /* An X form AltiVec dss instruction. */ |
| |