diff --git a/src/Makefile.am b/src/Makefile.am
index e1914bd..6a3060f 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -10,7 +10,7 @@
 
 EXTRA_LIBRARIES = libshared.a
 
-libshared_a_SOURCES = drm_setup.c gpu_code.c write_bmp.c etna_fb.c etnaviv_tiling.c
+libshared_a_SOURCES = drm_setup.c gpu_code.c write_bmp.c etna_fb.c etnaviv_tiling.c etnaviv_blt.c
 libshared_a_CFLAGS = $(LIBDRM_CFLAGS) $(LIBDRM_ETNAVIV_CFLAGS)
 
 etnaviv_cl_test_gc2000_SOURCES = etnaviv_cl_test_gc2000.c
diff --git a/src/bltdemo_gc7000.c b/src/bltdemo_gc7000.c
index f587eef..17a463b 100644
--- a/src/bltdemo_gc7000.c
+++ b/src/bltdemo_gc7000.c
@@ -6,7 +6,7 @@
 
 #include "write_bmp.h"
 #include "memutil.h"
-
+#include "etnaviv_blt.h"
 #include "drm_setup.h"
 #include "cmdstream.h"
 #include "etna_fb.h"
@@ -117,79 +117,6 @@
     etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
 }
 
-struct blt_clear_op
-{
-    struct etna_reloc addr;
-    struct etna_reloc ts_addr;
-    uint32_t bpp; /* bytes per pixel */
-    uint32_t stride;
-    bool compressed;
-    uint32_t compress_fmt;
-    uint32_t tiling;
-    uint16_t rect_x;
-    uint16_t rect_y;
-    uint16_t rect_w;
-    uint16_t rect_h;
-    uint32_t clear_value[2];
-    bool use_ts;
-    uint32_t ts_clear_value[2];
-};
-
-void emit_blt_clear(struct etna_cmd_stream *stream, const struct blt_clear_op *op)
-{
-    /* TODO figure out tilings */
-    uint32_t stride_bits =
-        VIVS_BLT_DEST_STRIDE_TILING(3) |
-        VIVS_BLT_DEST_STRIDE_FORMAT(BLT_FORMAT_A4R4G4B4) |
-        VIVS_BLT_DEST_STRIDE_STRIDE(op->stride);
-    uint32_t img_config_bits =
-        BLT_IMAGE_CONFIG_CACHE_MODE(TS_CACHE_MODE_256) |
-        COND(op->use_ts, BLT_IMAGE_CONFIG_TS) |
-        COND(op->compressed, BLT_IMAGE_CONFIG_COMPRESSION) |
-        BLT_IMAGE_CONFIG_COMPRESSION_FORMAT(op->compress_fmt);
-
-    etna_cmd_stream_reserve(stream, 64*2); /* Make sure BLT op doesn't get broken up */
-
-    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
-    etna_set_state(stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
-
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
-    assert(op->bpp);
-    etna_set_state(stream, VIVS_BLT_CONFIG, VIVS_BLT_CONFIG_CLEAR_BPP(op->bpp-1));
-    etna_set_state(stream, VIVS_BLT_DEST_STRIDE, stride_bits);
-    etna_set_state(stream, VIVS_BLT_DEST_CONFIG, img_config_bits | BLT_IMAGE_CONFIG_TO_SUPER_TILED);
-    etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->addr);
-    etna_set_state(stream, VIVS_BLT_SRC_STRIDE, stride_bits);
-    etna_set_state(stream, VIVS_BLT_SRC_CONFIG, img_config_bits | BLT_IMAGE_CONFIG_FROM_SUPER_TILED);
-    etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->addr);
-    etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->rect_x) | VIVS_BLT_DEST_POS_Y(op->rect_y));
-    etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
-    etna_set_state(stream, VIVS_BLT_CLEAR_COLOR0, op->clear_value[0]);
-    etna_set_state(stream, VIVS_BLT_CLEAR_COLOR1, op->clear_value[1]);
-    etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, 0xffffffff);
-    etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, 0xffffffff);
-    if (op->use_ts) {
-        etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->ts_addr);
-        etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->ts_addr);
-        etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->ts_clear_value[0]);
-        etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->ts_clear_value[1]);
-        etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->ts_clear_value[0]);
-        etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->ts_clear_value[1]);
-    }
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_CLEAR_IMAGE);
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
-#if 0
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
-    etna_set_state(stream, VIVS_GL_SEMAPHORE_TOKEN, 0x00001005); /* Make RA wait for BLT */
-    etna_set_state(stream, VIVS_GL_STALL_TOKEN, 0x00001005);
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
-#endif
-    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000002);
-    etna_set_state(stream, VIVS_DUMMY_DUMMY, 0x00000000);
-}
-
 #define NUM_BOGEYS 40
 struct bogey {
     int iw;
@@ -297,35 +224,46 @@
 
         /* Clear framebuffer */
         struct blt_clear_op clr = {};
-        clr.addr = tinfo->ADDR_RENDER_TARGET_A;
-        clr.ts_addr = tinfo->ADDR_TILE_STATUS_B;
-        clr.bpp = 4;
-        clr.stride = 0x1e00;
-        clr.compressed = 1;
-        clr.compress_fmt = 3;
-        clr.tiling = 123; /* TODO */
+        clr.dest.addr = tinfo->ADDR_RENDER_TARGET_A;
+        clr.dest.ts_addr = tinfo->ADDR_TILE_STATUS_B;
+        clr.dest.bpp = 4;
+        clr.dest.stride = 0x1e00;
+        clr.dest.compressed = 1;
+        clr.dest.compress_fmt = 3;
+        clr.dest.tiling = ETNA_LAYOUT_SUPER_TILED;
+        clr.dest.use_ts = 1;
+        clr.dest.ts_clear_value[0] = tinfo->ts_clear_value[0];
+        clr.dest.ts_clear_value[1] = tinfo->ts_clear_value[1];
+        clr.dest.cache_mode = TS_CACHE_MODE_256;
+
+        clr.clear_value[0] = background;
+        clr.clear_value[1] = background;
+        clr.clear_bits[0] = 0xffffffff;
+        clr.clear_bits[1] = 0xffffffff;
         clr.rect_x = 0;
         clr.rect_y = 0;
         clr.rect_w = WIDTH;
         clr.rect_h = HEIGHT;
-        clr.clear_value[0] = background;
-        clr.clear_value[1] = background;
-        clr.use_ts = 1;
-        clr.ts_clear_value[0] = tinfo->ts_clear_value[0];
-        clr.ts_clear_value[1] = tinfo->ts_clear_value[1];
-        emit_blt_clear(info->stream, &clr);
+        emit_blt_clearimage(info->stream, &clr);
 
         /* Draw bouncing squares */
         for (unsigned i=0; i<NUM_BOGEYS; ++i) {
             struct blt_clear_op clr = {};
             struct bogey *b = &bogeys[i];
-            clr.addr = tinfo->ADDR_RENDER_TARGET_A;
-            clr.ts_addr = tinfo->ADDR_TILE_STATUS_B;
-            clr.bpp = 4;
-            clr.stride = 0x1e00;
-            clr.compressed = 1;
-            clr.compress_fmt = 3;
-            clr.tiling = 123; /* TODO */
+            clr.dest.addr = tinfo->ADDR_RENDER_TARGET_A;
+            clr.dest.ts_addr = tinfo->ADDR_TILE_STATUS_B;
+            clr.dest.bpp = 4;
+            clr.dest.stride = 0x1e00;
+            clr.dest.compressed = 1;
+            clr.dest.compress_fmt = 3;
+            clr.dest.tiling = ETNA_LAYOUT_SUPER_TILED;
+            clr.dest.use_ts = 1;
+            clr.dest.ts_clear_value[0] = tinfo->ts_clear_value[0];
+            clr.dest.ts_clear_value[1] = tinfo->ts_clear_value[1];
+            clr.dest.cache_mode = TS_CACHE_MODE_256;
+
+            clr.clear_value[0] = clr.clear_value[1] = b->color;
+            clr.clear_bits[0] = 0xffffffff; clr.clear_bits[1] = 0xffffffff;
             clr.rect_x = b->iposx;
             clr.rect_y = b->iposy;
             clr.rect_w = b->iw;
@@ -336,12 +274,8 @@
             assert(clr.rect_h > 0);
             assert((clr.rect_x + clr.rect_w) <= WIDTH);
             assert((clr.rect_y + clr.rect_h) <= HEIGHT);
-            clr.clear_value[0] = clr.clear_value[1] = b->color;
-            clr.use_ts = 1;
-            clr.ts_clear_value[0] = tinfo->ts_clear_value[0];
-            clr.ts_clear_value[1] = tinfo->ts_clear_value[1];
 
-            emit_blt_clear(info->stream, &clr);
+            emit_blt_clearimage(info->stream, &clr);
         }
 
         /* Copy framebuffer to screen */
diff --git a/src/blttest2_gc7000.c b/src/blttest2_gc7000.c
index 6c3be90..4235915 100644
--- a/src/blttest2_gc7000.c
+++ b/src/blttest2_gc7000.c
@@ -6,12 +6,12 @@
 
 #include "write_bmp.h"
 #include "memutil.h"
-
 #include "drm_setup.h"
 #include "cmdstream.h"
 #include "etna_util.h"
 #include "color.h"
 #include "etnaviv_tiling.h"
+#include "etnaviv_blt.h"
 
 #include "hw/state.xml.h"
 #include "hw/common_3d.xml.h"
@@ -167,204 +167,6 @@
     etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
 }
 
-/* src/dest info for imgcopy */
-struct blt_imginfo
-{
-    struct etna_reloc addr;
-    struct etna_reloc ts_addr;
-    uint32_t format;
-    uint32_t stride;
-    bool compressed;
-    uint32_t compress_fmt;
-    enum etna_surface_layout tiling;
-    uint32_t cache_mode;
-    bool use_ts;
-    uint32_t ts_clear_value[2];
-    uint8_t swizzle[4];
-    uint8_t endian_mode;
-};
-
-/** Copy image operation.
- */
-struct blt_imgcopy_op
-{
-    struct blt_imginfo src;
-    struct blt_imginfo dest;
-    uint16_t src_x;
-    uint16_t src_y;
-    uint16_t dest_x;
-    uint16_t dest_y;
-    uint16_t rect_w;
-    uint16_t rect_h;
-};
-
-/** Resolve-in-place operation.
- * Fill unfilled tiles.
- */
-struct blt_inplace_op
-{
-    struct etna_reloc addr;
-    struct etna_reloc ts_addr;
-    uint32_t ts_clear_value[2];
-    uint32_t num_tiles;
-};
-
-/** Generate a whole series of mipmaps for a texture.
- */
-struct blt_genmipmaps_op
-{
-    struct blt_imginfo src;
-    struct blt_imginfo dest; /* address is not used, stride must be equal to src stride */
-    uint16_t rect_w;
-    uint16_t rect_h;
-    uint32_t num_mips;
-    struct etna_reloc mip_addr[16];
-    uint32_t mip_stride[16];
-};
-
-static inline uint32_t blt_compute_stride_bits(const struct blt_imginfo *img)
-{
-    return VIVS_BLT_DEST_STRIDE_TILING(img->tiling == ETNA_LAYOUT_LINEAR ? 0 : 3) |
-           VIVS_BLT_DEST_STRIDE_FORMAT(img->format) |
-           VIVS_BLT_DEST_STRIDE_STRIDE(img->stride);
-}
-
-static inline uint32_t blt_compute_img_config_bits(const struct blt_imginfo *img, bool for_dest)
-{
-    uint32_t tiling_bits = 0;
-    if (img->tiling == ETNA_LAYOUT_SUPER_TILED) {
-        tiling_bits |= for_dest ? BLT_IMAGE_CONFIG_TO_SUPER_TILED : BLT_IMAGE_CONFIG_FROM_SUPER_TILED;
-    }
-
-    return COND(img->cache_mode, BLT_IMAGE_CONFIG_CACHE_MODE(TS_CACHE_MODE_256)) |
-           COND(img->use_ts, BLT_IMAGE_CONFIG_TS) |
-           COND(img->compressed, BLT_IMAGE_CONFIG_COMPRESSION) |
-           BLT_IMAGE_CONFIG_COMPRESSION_FORMAT(img->compress_fmt) |
-           COND(for_dest, BLT_IMAGE_CONFIG_UNK22) |
-           BLT_IMAGE_CONFIG_SWIZ_R(0) | /* not used? */
-           BLT_IMAGE_CONFIG_SWIZ_G(1) |
-           BLT_IMAGE_CONFIG_SWIZ_B(2) |
-           BLT_IMAGE_CONFIG_SWIZ_A(3) |
-           tiling_bits;
-}
-
-static inline uint32_t blt_compute_swizzle_bits(const struct blt_imginfo *img, bool for_dest)
-{
-    uint32_t swiz = VIVS_BLT_SWIZZLE_SRC_R(img->swizzle[0]) |
-                    VIVS_BLT_SWIZZLE_SRC_G(img->swizzle[1]) |
-                    VIVS_BLT_SWIZZLE_SRC_B(img->swizzle[2]) |
-                    VIVS_BLT_SWIZZLE_SRC_A(img->swizzle[3]);
-    return for_dest ? (swiz << 12) : swiz;
-}
-
-void emit_blt_copyimage(struct etna_cmd_stream *stream, const struct blt_imgcopy_op *op)
-{
-    etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
-    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
-    etna_set_state(stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
-
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
-    etna_set_state(stream, VIVS_BLT_CONFIG,
-            VIVS_BLT_CONFIG_SRC_ENDIAN(op->src.endian_mode) |
-            VIVS_BLT_CONFIG_DEST_ENDIAN(op->dest.endian_mode));
-    etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->src));
-    etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->src, false));
-    etna_set_state(stream, VIVS_BLT_SWIZZLE,
-            blt_compute_swizzle_bits(&op->src, false) |
-            blt_compute_swizzle_bits(&op->dest, true));
-    etna_set_state(stream, VIVS_BLT_UNK140A0, 0x00040004);
-    etna_set_state(stream, VIVS_BLT_UNK1409C, 0x00400040);
-    if (op->src.use_ts) {
-        etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->src.ts_addr);
-        etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->src.ts_clear_value[0]);
-        etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->src.ts_clear_value[1]);
-    }
-    etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->src.addr);
-    etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
-    etna_set_state(stream, VIVS_BLT_DEST_CONFIG, blt_compute_img_config_bits(&op->dest, true));
-    if (op->dest.use_ts) {
-        etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
-        etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
-        etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
-    }
-    etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
-    etna_set_state(stream, VIVS_BLT_SRC_POS, VIVS_BLT_DEST_POS_X(op->src_x) | VIVS_BLT_DEST_POS_Y(op->src_y));
-    etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->dest_x) | VIVS_BLT_DEST_POS_Y(op->dest_y));
-    etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
-    etna_set_state(stream, VIVS_BLT_UNK14058, 0xffffffff);
-    etna_set_state(stream, VIVS_BLT_UNK1405C, 0xffffffff);
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_COPY_IMAGE);
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
-}
-
-/** Make frontend wait for BLT operation.
- */
-void emit_blt_sync_fe(struct etna_cmd_stream *stream)
-{
-    etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
-    etna_set_state(stream, VIVS_GL_SEMAPHORE_TOKEN, 0x00001001);
-    etna_cmd_stream_emit(stream, 0x48000000); /* command STALL (9) OP=STALL */
-    etna_cmd_stream_emit(stream, 0x00001001); /* command   TOKEN FROM=FE,TO=BLT,UNK28=0x0 */
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
-    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
-}
-
-/** Emit in-place resolve using BLT.
- */
-void emit_blt_inplace(struct etna_cmd_stream *stream, const struct blt_inplace_op *op)
-{
-    etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
-    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
-    etna_set_state(stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
-
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
-    etna_set_state(stream, VIVS_BLT_CONFIG, (1<<10) | (1<<11) | (1<<15));
-    etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->ts_clear_value[0]);
-    etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->ts_clear_value[1]);
-    etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->addr);
-    etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->ts_addr);
-    etna_set_state(stream, 0x14068, op->num_tiles);
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_COMMAND, 0x00000004);
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
-}
-
-/**
- * Emit command to generate mipmap chain using BLT.
- */
-void emit_blt_genmipmaps(struct etna_cmd_stream *stream, const struct blt_genmipmaps_op *op)
-{
-    etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
-    etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->src));
-    etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->src, false));
-    etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->src.addr);
-    etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
-    etna_set_state(stream, VIVS_BLT_DEST_CONFIG, blt_compute_img_config_bits(&op->dest, true));
-    etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
-    etna_set_state(stream, VIVS_BLT_SWIZZLE,
-            blt_compute_swizzle_bits(&op->src, false) |
-            blt_compute_swizzle_bits(&op->dest, true));
-    for (unsigned level=0; level<op->num_mips; ++level) {
-        etna_set_state_reloc(stream, VIVS_BLT_MIP_ADDR(level), &op->mip_addr[level]);
-        etna_set_state(stream, VIVS_BLT_MIP_STRIDE(level), op->mip_stride[level]);
-    }
-    etna_set_state(stream, VIVS_BLT_MIPMAP_CONFIG, VIVS_BLT_MIPMAP_CONFIG_UNK5 |
-            VIVS_BLT_MIPMAP_CONFIG_NUM(op->num_mips+1));
-    etna_set_state(stream, VIVS_BLT_CONFIG,
-            VIVS_BLT_CONFIG_SRC_ENDIAN(op->src.endian_mode) |
-            VIVS_BLT_CONFIG_DEST_ENDIAN(op->dest.endian_mode));
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_GEN_MIPMAPS);
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
-}
-
 /* Create a demo texture */
 void create_linear_argb_image(uint32_t *dest, unsigned width, unsigned height, unsigned stride)
 {
diff --git a/src/blttest_gc7000.c b/src/blttest_gc7000.c
index c44c947..dabba0b 100644
--- a/src/blttest_gc7000.c
+++ b/src/blttest_gc7000.c
@@ -6,7 +6,7 @@
 
 #include "write_bmp.h"
 #include "memutil.h"
-
+#include "etnaviv_blt.h"
 #include "drm_setup.h"
 #include "cmdstream.h"
 #include "etna_util.h"
@@ -58,27 +58,6 @@
     free(info);
 }
 
-void emit_blt_copybuffer(struct etna_cmd_stream *stream, struct etna_reloc *dest, struct etna_reloc *src, uint32_t size)
-{
-    etna_cmd_stream_reserve(stream, 64*2); /* Make sure BLT op doesn't get broken up */
-
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
-    etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, src);
-    etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, dest);
-    etna_set_state(stream, VIVS_BLT_BUFFER_SIZE, size);
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_COPY_BUFFER);
-    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
-
-    /* Synchronize FE with BLT, because we want to see result after finishing command buffer */
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
-    etna_set_state(stream, VIVS_GL_SEMAPHORE_TOKEN, 0x30001001);
-    etna_cmd_stream_emit(stream, 0x48000000); /* command STALL (9) OP=STALL */
-    etna_cmd_stream_emit(stream, 0x30001001); /* command   TOKEN FROM=FE,TO=BLT,UNK28=0x3 */
-    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
-}
-
 int main(int argc, char **argv)
 {
     struct drm_test_info *info;
diff --git a/src/etnaviv_blt.c b/src/etnaviv_blt.c
new file mode 100644
index 0000000..379e87c
--- /dev/null
+++ b/src/etnaviv_blt.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2017 Etnaviv Project
+ * Copyright (C) 2017 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Wladimir J. van der Laan <laanwj@gmail.com>
+ */
+#include "etnaviv_blt.h"
+
+#include "cmdstream.h"
+#include "etna_util.h"
+
+#include "hw/state.xml.h"
+#include "hw/common_3d.xml.h"
+#include "hw/state_3d.xml.h"
+#include "hw/state_blt.xml.h"
+
+#include <assert.h>
+
+static inline uint32_t blt_compute_stride_bits(const struct blt_imginfo *img)
+{
+    return VIVS_BLT_DEST_STRIDE_TILING(img->tiling == ETNA_LAYOUT_LINEAR ? 0 : 3) |
+           VIVS_BLT_DEST_STRIDE_FORMAT(img->format) |
+           VIVS_BLT_DEST_STRIDE_STRIDE(img->stride);
+}
+
+static inline uint32_t blt_compute_img_config_bits(const struct blt_imginfo *img, bool for_dest)
+{
+    uint32_t tiling_bits = 0;
+    if (img->tiling == ETNA_LAYOUT_SUPER_TILED) {
+        tiling_bits |= for_dest ? BLT_IMAGE_CONFIG_TO_SUPER_TILED : BLT_IMAGE_CONFIG_FROM_SUPER_TILED;
+    }
+
+    return BLT_IMAGE_CONFIG_CACHE_MODE(img->cache_mode) |
+           COND(img->use_ts, BLT_IMAGE_CONFIG_TS) |
+           COND(img->compressed, BLT_IMAGE_CONFIG_COMPRESSION) |
+           BLT_IMAGE_CONFIG_COMPRESSION_FORMAT(img->compress_fmt) |
+           COND(for_dest, BLT_IMAGE_CONFIG_UNK22) |
+           BLT_IMAGE_CONFIG_SWIZ_R(0) | /* not used? */
+           BLT_IMAGE_CONFIG_SWIZ_G(1) |
+           BLT_IMAGE_CONFIG_SWIZ_B(2) |
+           BLT_IMAGE_CONFIG_SWIZ_A(3) |
+           tiling_bits;
+}
+
+static inline uint32_t blt_compute_swizzle_bits(const struct blt_imginfo *img, bool for_dest)
+{
+    uint32_t swiz = VIVS_BLT_SWIZZLE_SRC_R(img->swizzle[0]) |
+                    VIVS_BLT_SWIZZLE_SRC_G(img->swizzle[1]) |
+                    VIVS_BLT_SWIZZLE_SRC_B(img->swizzle[2]) |
+                    VIVS_BLT_SWIZZLE_SRC_A(img->swizzle[3]);
+    return for_dest ? (swiz << 12) : swiz;
+}
+
+void emit_blt_clearimage(struct etna_cmd_stream *stream, const struct blt_clear_op *op)
+{
+    etna_cmd_stream_reserve(stream, 64*2); /* Make sure BLT op doesn't get broken up */
+
+    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
+    etna_set_state(stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
+
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
+    assert(op->dest.bpp);
+    etna_set_state(stream, VIVS_BLT_CONFIG, VIVS_BLT_CONFIG_CLEAR_BPP(op->dest.bpp-1));
+    /* NB: blob sets format to 1 in dest/src config for clear, and the swizzle to RRRR.
+     * does this matter? It seems to just be ignored. But if we run into issues with BLT
+     * behaving stragely, it's something to look at.
+     */
+    etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
+    etna_set_state(stream, VIVS_BLT_DEST_CONFIG, blt_compute_img_config_bits(&op->dest, true));
+    etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
+    etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->dest));
+    etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->dest, false));
+    etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->dest.addr);
+    etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->rect_x) | VIVS_BLT_DEST_POS_Y(op->rect_y));
+    etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
+    etna_set_state(stream, VIVS_BLT_CLEAR_COLOR0, op->clear_value[0]);
+    etna_set_state(stream, VIVS_BLT_CLEAR_COLOR1, op->clear_value[1]);
+    etna_set_state(stream, VIVS_BLT_CLEAR_BITS0, op->clear_bits[0]);
+    etna_set_state(stream, VIVS_BLT_CLEAR_BITS1, op->clear_bits[1]);
+    if (op->dest.use_ts) {
+        etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
+        etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->dest.ts_addr);
+        etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
+        etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
+        etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
+        etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
+    }
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_CLEAR_IMAGE);
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
+}
+
+void emit_blt_copybuffer(struct etna_cmd_stream *stream, struct etna_reloc *dest, struct etna_reloc *src, uint32_t size)
+{
+    etna_cmd_stream_reserve(stream, 64*2); /* Make sure BLT op doesn't get broken up */
+
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
+    etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, src);
+    etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, dest);
+    etna_set_state(stream, VIVS_BLT_BUFFER_SIZE, size);
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_COPY_BUFFER);
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
+
+    /* Synchronize FE with BLT, because we want to see result after finishing command buffer */
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
+    etna_set_state(stream, VIVS_GL_SEMAPHORE_TOKEN, 0x30001001);
+    etna_cmd_stream_emit(stream, 0x48000000); /* command STALL (9) OP=STALL */
+    etna_cmd_stream_emit(stream, 0x30001001); /* command   TOKEN FROM=FE,TO=BLT,UNK28=0x3 */
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
+}
+
+void emit_blt_copyimage(struct etna_cmd_stream *stream, const struct blt_imgcopy_op *op)
+{
+    etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
+    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
+    etna_set_state(stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
+
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
+    etna_set_state(stream, VIVS_BLT_CONFIG,
+            VIVS_BLT_CONFIG_SRC_ENDIAN(op->src.endian_mode) |
+            VIVS_BLT_CONFIG_DEST_ENDIAN(op->dest.endian_mode));
+    etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->src));
+    etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->src, false));
+    etna_set_state(stream, VIVS_BLT_SWIZZLE,
+            blt_compute_swizzle_bits(&op->src, false) |
+            blt_compute_swizzle_bits(&op->dest, true));
+    etna_set_state(stream, VIVS_BLT_UNK140A0, 0x00040004);
+    etna_set_state(stream, VIVS_BLT_UNK1409C, 0x00400040);
+    if (op->src.use_ts) {
+        etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->src.ts_addr);
+        etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->src.ts_clear_value[0]);
+        etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->src.ts_clear_value[1]);
+    }
+    etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->src.addr);
+    etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
+    etna_set_state(stream, VIVS_BLT_DEST_CONFIG, blt_compute_img_config_bits(&op->dest, true));
+    assert(op->dest.use_ts); /* Dest TS path doesn't work for copies? */
+    if (op->dest.use_ts) {
+        etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
+        etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
+        etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
+    }
+    etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
+    etna_set_state(stream, VIVS_BLT_SRC_POS, VIVS_BLT_DEST_POS_X(op->src_x) | VIVS_BLT_DEST_POS_Y(op->src_y));
+    etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->dest_x) | VIVS_BLT_DEST_POS_Y(op->dest_y));
+    etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
+    etna_set_state(stream, VIVS_BLT_UNK14058, 0xffffffff);
+    etna_set_state(stream, VIVS_BLT_UNK1405C, 0xffffffff);
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_COPY_IMAGE);
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
+}
+
+void emit_blt_inplace(struct etna_cmd_stream *stream, const struct blt_inplace_op *op)
+{
+    etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
+    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
+    etna_set_state(stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
+
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
+    etna_set_state(stream, VIVS_BLT_CONFIG, (1<<10) | (1<<11) | (1<<15));
+    etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->ts_clear_value[0]);
+    etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->ts_clear_value[1]);
+    etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->addr);
+    etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->ts_addr);
+    etna_set_state(stream, 0x14068, op->num_tiles);
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_COMMAND, 0x00000004);
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
+}
+
+void emit_blt_genmipmaps(struct etna_cmd_stream *stream, const struct blt_genmipmaps_op *op)
+{
+    etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
+    etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->src));
+    etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->src, false));
+    etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->src.addr);
+    etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
+    etna_set_state(stream, VIVS_BLT_DEST_CONFIG, blt_compute_img_config_bits(&op->dest, true));
+    etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
+    etna_set_state(stream, VIVS_BLT_SWIZZLE,
+            blt_compute_swizzle_bits(&op->src, false) |
+            blt_compute_swizzle_bits(&op->dest, true));
+    for (unsigned level=0; level<op->num_mips; ++level) {
+        etna_set_state_reloc(stream, VIVS_BLT_MIP_ADDR(level), &op->mip_addr[level]);
+        etna_set_state(stream, VIVS_BLT_MIP_STRIDE(level), op->mip_stride[level]);
+    }
+    etna_set_state(stream, VIVS_BLT_MIPMAP_CONFIG, VIVS_BLT_MIPMAP_CONFIG_UNK5 |
+            VIVS_BLT_MIPMAP_CONFIG_NUM(op->num_mips+1));
+    etna_set_state(stream, VIVS_BLT_CONFIG,
+            VIVS_BLT_CONFIG_SRC_ENDIAN(op->src.endian_mode) |
+            VIVS_BLT_CONFIG_DEST_ENDIAN(op->dest.endian_mode));
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_GEN_MIPMAPS);
+    etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
+}
+
+void emit_blt_sync_fe(struct etna_cmd_stream *stream)
+{
+    etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
+    etna_set_state(stream, VIVS_GL_SEMAPHORE_TOKEN, 0x00001001);
+    etna_cmd_stream_emit(stream, 0x48000000); /* command STALL (9) OP=STALL */
+    etna_cmd_stream_emit(stream, 0x00001001); /* command   TOKEN FROM=FE,TO=BLT,UNK28=0x0 */
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
+
+    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
+}
+
+void emit_blt_sync_ra(struct etna_cmd_stream *stream)
+{
+    etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
+    etna_set_state(stream, VIVS_GL_SEMAPHORE_TOKEN, 0x00001005); /* Make RA wait for BLT */
+    etna_set_state(stream, VIVS_GL_STALL_TOKEN, 0x00001005);
+    etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
+
+    etna_set_state(stream, VIVS_GL_FLUSH_CACHE, 0x00000002);
+    etna_set_state(stream, VIVS_DUMMY_DUMMY, 0x00000000);
+}
+
+
diff --git a/src/etnaviv_blt.h b/src/etnaviv_blt.h
new file mode 100644
index 0000000..c8eb187
--- /dev/null
+++ b/src/etnaviv_blt.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2017 Etnaviv Project
+ * Copyright (C) 2017 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Wladimir J. van der Laan <laanwj@gmail.com>
+ */
+#ifndef H_ETNAVIV_BLT
+#define H_ETNAVIV_BLT
+
+#include "etnaviv_tiling.h"
+
+#include <stdbool.h>
+#include <etnaviv_drmif.h>
+
+/* src/dest info for image operations */
+struct blt_imginfo
+{
+    unsigned compressed:1;
+    unsigned use_ts:1;
+    struct etna_reloc addr;
+    struct etna_reloc ts_addr;
+    uint32_t format; /* BLT_FORMAT_* */
+    uint32_t stride;
+    uint32_t compress_fmt; /* COLOR_COMPRESSION_FORMAT_* */
+    enum etna_surface_layout tiling; /* ETNA_LAYOUT_* */
+    uint32_t ts_clear_value[2];
+    uint8_t swizzle[4]; /* TEXTURE_SWIZZLE_* */
+    uint8_t cache_mode; /* TS_CACHE_MODE_* */
+    uint8_t endian_mode; /* ENDIAN_MODE_* */
+    uint8_t bpp; /* # bytes per pixel 1/2/4/8 - only used for CLEAR_IMAGE */
+};
+
+/** (Partial) image clear operation.
+ */
+struct blt_clear_op
+{
+    struct blt_imginfo dest;
+    uint32_t clear_value[2];
+    uint32_t clear_bits[2]; /* bit mask of bits to clear */
+    uint16_t rect_x;
+    uint16_t rect_y;
+    uint16_t rect_w;
+    uint16_t rect_h;
+};
+
+/** Copy image operation.
+ */
+struct blt_imgcopy_op
+{
+    struct blt_imginfo src;
+    struct blt_imginfo dest;
+    uint16_t src_x;
+    uint16_t src_y;
+    uint16_t dest_x;
+    uint16_t dest_y;
+    uint16_t rect_w;
+    uint16_t rect_h;
+};
+
+/** Resolve-in-place operation.
+ * Fills unfilled tiles.
+ */
+struct blt_inplace_op
+{
+    struct etna_reloc addr;
+    struct etna_reloc ts_addr;
+    uint32_t ts_clear_value[2];
+    uint32_t num_tiles;
+};
+
+/** Generate a series of mipmaps for a texture.
+ */
+struct blt_genmipmaps_op
+{
+    struct blt_imginfo src;
+    struct blt_imginfo dest; /* address is not used, stride must be equal to src stride */
+    uint16_t rect_w; /* width of source image */
+    uint16_t rect_h; /* height of source image */
+    uint32_t num_mips; /* number of mipmaps to generate */
+    struct etna_reloc mip_addr[16];
+    uint32_t mip_stride[16];
+};
+
+/** Clear (part of) an image.
+ */
+void emit_blt_clearimage(struct etna_cmd_stream *stream, const struct blt_clear_op *op);
+
+/** Copy (a subset of) a linear buffer to another buffer.
+ */
+void emit_blt_copybuffer(struct etna_cmd_stream *stream, struct etna_reloc *dest, struct etna_reloc *src, uint32_t size);
+
+/** Copy (a subset of) an image to another image.
+ */
+void emit_blt_copyimage(struct etna_cmd_stream *stream, const struct blt_imgcopy_op *op);
+
+/** Emit in-place resolve using BLT.
+ */
+void emit_blt_inplace(struct etna_cmd_stream *stream, const struct blt_inplace_op *op);
+
+/**
+ * Emit command to generate mipmap chain using BLT.
+ */
+void emit_blt_genmipmaps(struct etna_cmd_stream *stream, const struct blt_genmipmaps_op *op);
+
+/** Make frontend wait for BLT operation.
+ */
+void emit_blt_sync_fe(struct etna_cmd_stream *stream);
+
+/** Make rasterizer wait for BLT operation.
+ */
+void emit_blt_sync_ra(struct etna_cmd_stream *stream);
+
+#endif