tree e1052ca09da8564ba7d36f3ebbef411547a90b95
parent c5cf7f69c98baed40754ca4a821cb504fd5423cd
author Ard Biesheuvel <ardb@kernel.org> 1684532652 +0200
committer mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> 1684802601 +0000

ArmPkg/ArmMmuLib AARCH64: Add missing ISB after page table update

The helper that updates live page table entries writes a zero entry,
invalidates the covered address range from the TLBs, and finally writes
the actual entry. This ensures that no TLB conflicts can occur.

Writing the final entry needs to complete before any translations can be
performed, as otherwise, the zero entry, which describes an invalid
translation, may be observed by the page table walker, resulting in a
translation fault. For this reason, the final write is followed by a DSB
barrier instruction.

However, this barrier will not stall the pipeline, and instruction
fetches may still hit this invalid translation, as has been observed and
reported by Oliver. To ensure that the new translation is fully active
before returning from this helper, we have to insert an ISB barrier as
well.

Reported-by: Oliver Steffen <osteffen@redhat.com>
Tested-by: Oliver Steffen <osteffen@redhat.com>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Acked-by: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>