tegra: spi: Wait for the DMA to finish emptying the RX FIFO.
When using DMA to do a SPI transfer, we were waiting for the actual transfer
to finish but weren't waiting for the DMA engine to empty the RX FIFO within
the SPI controller. We were then stopping the DMA and loosing that part of the
data. This change replaces the "stop" function of the DMA channel structures
with a "finish" function which does the same thing as stop but also makes sure
the transfer is finished first.
BUG=None
TEST=Before this change, doing an RW boot failed because the data was
incompletely loaded from flash. After this change, RW booting worked.
BRANCH=None
Change-Id: I46ddc0ee2752448aad5193b7bf40796ffd177194
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/174918
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
3 files changed
