| # CS_ARCH_AARCH64, 0, None | |
| 0x20,0x12,0x18,0xd5 == msr TRFCR_EL1, x0 | |
| 0x20,0x12,0x1c,0xd5 == msr TRFCR_EL2, x0 | |
| 0x20,0x12,0x1d,0xd5 == msr TRFCR_EL12, x0 | |
| 0x20,0x12,0x38,0xd5 == mrs x0, TRFCR_EL1 | |
| 0x20,0x12,0x3c,0xd5 == mrs x0, TRFCR_EL2 | |
| 0x20,0x12,0x3d,0xd5 == mrs x0, TRFCR_EL12 | |
| 0x5f,0x22,0x03,0xd5 == tsb csync |