Undefined shifts (#1154)
* Fix undefined shifts
uint8 gets promoted to signed integer
in ARM, MIPS, Sparc
in AArch64, PPC and Xcore
* fix undefined shift in powerpc
* Fix undefined shift in Mips
use mulitply instead
diff --git a/LEB128.h b/LEB128.h
index da4140c..4fbc2cd 100644
--- a/LEB128.h
+++ b/LEB128.h
@@ -27,7 +27,7 @@
uint64_t Value = 0;
unsigned Shift = 0;
do {
- Value += (*p & 0x7f) << Shift;
+ Value += (uint64_t)(*p & 0x7f) << Shift;
Shift += 7;
} while (*p++ >= 128);
if (n)
diff --git a/arch/AArch64/AArch64AddressingModes.h b/arch/AArch64/AArch64AddressingModes.h
index 8378902..4de6f10 100644
--- a/arch/AArch64/AArch64AddressingModes.h
+++ b/arch/AArch64/AArch64AddressingModes.h
@@ -198,7 +198,7 @@
// where B = NOT(b);
FPUnion.I = 0;
- FPUnion.I |= Sign << 31;
+ FPUnion.I |= (uint32_t) Sign << 31;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
FPUnion.I |= (Exp & 0x3) << 23;
diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c
index 9ec7880..fbba80f 100644
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@@ -240,9 +240,9 @@
if (ud->big_endian)
insn = (code[3] << 0) | (code[2] << 8) |
- (code[1] << 16) | (code[0] << 24);
+ (code[1] << 16) | ((uint32_t) code[0] << 24);
else
- insn = (code[3] << 24) | (code[2] << 16) |
+ insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
(code[1] << 8) | (code[0] << 0);
// Calling the auto-generated decoder function.
diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h
index d4540bb..f61bead 100644
--- a/arch/ARM/ARMAddressingModes.h
+++ b/arch/ARM/ARMAddressingModes.h
@@ -658,7 +658,7 @@
// where B = NOT(b);
FPUnion.I = 0;
- FPUnion.I |= Sign << 31;
+ FPUnion.I |= (uint32_t) Sign << 31;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
FPUnion.I |= (Exp & 0x3) << 23;
diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c
index aeda429..30a699f 100644
--- a/arch/ARM/ARMDisassembler.c
+++ b/arch/ARM/ARMDisassembler.c
@@ -486,9 +486,9 @@
insn = (code[3] << 0) |
(code[2] << 8) |
(code[1] << 16) |
- (code[0] << 24);
+ ((uint32_t) code[0] << 24);
else
- insn = (code[3] << 24) |
+ insn = ((uint32_t) code[3] << 24) |
(code[2] << 16) |
(code[1] << 8) |
(code[0] << 0);
@@ -780,11 +780,11 @@
insn32 = (code[3] << 0) |
(code[2] << 8) |
(code[1] << 16) |
- (code[0] << 24);
+ ((uint32_t) code[0] << 24);
else
insn32 = (code[3] << 8) |
(code[2] << 0) |
- (code[1] << 24) |
+ ((uint32_t) code[1] << 24) |
(code[0] << 16);
MCInst_clear(MI);
diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c
index 561f522..0b7d90e 100644
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@@ -391,14 +391,14 @@
if (isBigEndian) {
// Encoded as a big-endian 32-bit word in the stream.
*insn =
- (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | (code[0] << 24);
+ (code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24);
} else {
if (isMicroMips) {
*insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) |
- (code[1] << 24);
+ ((uint32_t) code[1] << 24);
} else {
*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) |
- (code[3] << 24);
+ ((uint32_t) code[3] << 24);
}
}
}
@@ -1786,7 +1786,7 @@
static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn,
uint64_t Address, MCRegisterInfo *Decoder)
{
- MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) << 2);
+ MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4);
return MCDisassembler_Success;
}
diff --git a/arch/PowerPC/PPCDisassembler.c b/arch/PowerPC/PPCDisassembler.c
index ffe2326..dde43b6 100644
--- a/arch/PowerPC/PPCDisassembler.c
+++ b/arch/PowerPC/PPCDisassembler.c
@@ -364,10 +364,10 @@
// The instruction is big-endian encoded.
if (MI->csh->mode & CS_MODE_BIG_ENDIAN)
- insn = (code[0] << 24) | (code[1] << 16) |
+ insn = ((uint32_t) code[0] << 24) | (code[1] << 16) |
(code[2] << 8) | (code[3] << 0);
else
- insn = (code[3] << 24) | (code[2] << 16) |
+ insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
(code[1] << 8) | (code[0] << 0);
if (MI->flat_insn->detail) {
diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c
index 473651e..be1f95b 100644
--- a/arch/PowerPC/PPCInstPrinter.c
+++ b/arch/PowerPC/PPCInstPrinter.c
@@ -567,7 +567,7 @@
return;
}
- imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) << 2;
+ imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) {
imm = MI->address + imm;
diff --git a/arch/Sparc/SparcDisassembler.c b/arch/Sparc/SparcDisassembler.c
index 78d9333..e5e8f1d 100644
--- a/arch/Sparc/SparcDisassembler.c
+++ b/arch/Sparc/SparcDisassembler.c
@@ -212,7 +212,7 @@
*Insn = (code[3] << 0) |
(code[2] << 8) |
(code[1] << 16) |
- (code[0] << 24);
+ ((uint32_t) code[0] << 24);
return MCDisassembler_Success;
}
diff --git a/arch/XCore/XCoreDisassembler.c b/arch/XCore/XCoreDisassembler.c
index 1bcf141..1d983f8 100644
--- a/arch/XCore/XCoreDisassembler.c
+++ b/arch/XCore/XCoreDisassembler.c
@@ -50,7 +50,7 @@
return false;
// Encoded as a little-endian 32-bit word in the stream.
- *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | (code[3] << 24);
+ *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24);
return true;
}
