blob: 7ccaf5407d06801bc00c2f9aca725c95f3ad1404 [file] [log] [blame]
// This is auto-gen data for Capstone engine (www.capstone-engine.org)
// By Nguyen Anh Quynh <aquynh@gmail.com>
{
Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ABSQ_S_W, MIPS_INS_ABSQ_S,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_ADD, MIPS_INS_ADD,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
#endif
},
{
Mips_ADDIUPC, MIPS_INS_ADDIUPC,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_ADDIUPC_MM, MIPS_INS_ADDIUPC,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDIUR1SP_MM, MIPS_INS_ADDIUR1SP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDIUR2_MM, MIPS_INS_ADDIUR2,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDIUS5_MM, MIPS_INS_ADDIUS5,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDIUSP_MM, MIPS_INS_ADDIUSP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDQH_PH, MIPS_INS_ADDQH,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ADDQH_R_W, MIPS_INS_ADDQH_R,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ADDQH_W, MIPS_INS_ADDQH,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ADDQ_PH, MIPS_INS_ADDQ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_ADDQ_S_W, MIPS_INS_ADDQ_S,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_ADDSC, MIPS_INS_ADDSC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_ADDS_A_B, MIPS_INS_ADDS_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_A_D, MIPS_INS_ADDS_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_A_H, MIPS_INS_ADDS_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_A_W, MIPS_INS_ADDS_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_S_B, MIPS_INS_ADDS_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_S_D, MIPS_INS_ADDS_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_S_H, MIPS_INS_ADDS_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_S_W, MIPS_INS_ADDS_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_U_B, MIPS_INS_ADDS_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_U_D, MIPS_INS_ADDS_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_U_H, MIPS_INS_ADDS_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDS_U_W, MIPS_INS_ADDS_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDU16_MM, MIPS_INS_ADDU16,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDUH_QB, MIPS_INS_ADDUH,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ADDU_PH, MIPS_INS_ADDU,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ADDU_QB, MIPS_INS_ADDU,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_ADDU_S_PH, MIPS_INS_ADDU_S,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ADDU_S_QB, MIPS_INS_ADDU_S,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_ADDVI_B, MIPS_INS_ADDVI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDVI_D, MIPS_INS_ADDVI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDVI_H, MIPS_INS_ADDVI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDVI_W, MIPS_INS_ADDVI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDV_B, MIPS_INS_ADDV,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDV_D, MIPS_INS_ADDV,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDV_H, MIPS_INS_ADDV,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDV_W, MIPS_INS_ADDV,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADDWC, MIPS_INS_ADDWC,
#ifndef CAPSTONE_DIET
{ MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_ADD_A_B, MIPS_INS_ADD_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADD_A_D, MIPS_INS_ADD_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADD_A_H, MIPS_INS_ADD_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADD_A_W, MIPS_INS_ADD_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ADD_MM, MIPS_INS_ADD,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDi, MIPS_INS_ADDI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_ADDi_MM, MIPS_INS_ADDI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDiu, MIPS_INS_ADDIU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDiu_MM, MIPS_INS_ADDIU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ADDu, MIPS_INS_ADDU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
#endif
},
{
Mips_ADDu_MM, MIPS_INS_ADDU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ALIGN, MIPS_INS_ALIGN,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_ALUIPC, MIPS_INS_ALUIPC,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_AND, MIPS_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_AND16_MM, MIPS_INS_AND16,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_AND64, MIPS_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
#endif
},
{
Mips_ANDI16_MM, MIPS_INS_ANDI16,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ANDI_B, MIPS_INS_ANDI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AND_MM, MIPS_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_AND_V, MIPS_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ANDi, MIPS_INS_ANDI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_ANDi64, MIPS_INS_ANDI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
#endif
},
{
Mips_ANDi_MM, MIPS_INS_ANDI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_APPEND, MIPS_INS_APPEND,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_ASUB_S_B, MIPS_INS_ASUB_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ASUB_S_D, MIPS_INS_ASUB_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ASUB_S_H, MIPS_INS_ASUB_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ASUB_S_W, MIPS_INS_ASUB_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ASUB_U_B, MIPS_INS_ASUB_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ASUB_U_D, MIPS_INS_ASUB_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ASUB_U_H, MIPS_INS_ASUB_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_ASUB_U_W, MIPS_INS_ASUB_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AUI, MIPS_INS_AUI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_AUIPC, MIPS_INS_AUIPC,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_AVER_S_B, MIPS_INS_AVER_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVER_S_D, MIPS_INS_AVER_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVER_S_H, MIPS_INS_AVER_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVER_S_W, MIPS_INS_AVER_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVER_U_B, MIPS_INS_AVER_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVER_U_D, MIPS_INS_AVER_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVER_U_H, MIPS_INS_AVER_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVER_U_W, MIPS_INS_AVER_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVE_S_B, MIPS_INS_AVE_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVE_S_D, MIPS_INS_AVE_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVE_S_H, MIPS_INS_AVE_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVE_S_W, MIPS_INS_AVE_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVE_U_B, MIPS_INS_AVE_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVE_U_D, MIPS_INS_AVE_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVE_U_H, MIPS_INS_AVE_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AVE_U_W, MIPS_INS_AVE_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_AddiuRxImmX16, MIPS_INS_ADDIU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_AddiuRxRxImm16, MIPS_INS_ADDIU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_AddiuSpImm16, MIPS_INS_ADDIU,
#ifndef CAPSTONE_DIET
{ MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_AddiuSpImmX16, MIPS_INS_ADDIU,
#ifndef CAPSTONE_DIET
{ MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_AdduRxRyRz16, MIPS_INS_ADDU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_AndRxRxRy16, MIPS_INS_AND,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_B16_MM, MIPS_INS_B16,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BADDu, MIPS_INS_BADDU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
#endif
},
{
Mips_BAL, MIPS_INS_BAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BALC, MIPS_INS_BALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BALIGN, MIPS_INS_BALIGN,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_BBIT0, MIPS_INS_BBIT0,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_CNMIPS, 0 }, 1, 0
#endif
},
{
Mips_BBIT032, MIPS_INS_BBIT032,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_CNMIPS, 0 }, 1, 0
#endif
},
{
Mips_BBIT1, MIPS_INS_BBIT1,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_CNMIPS, 0 }, 1, 0
#endif
},
{
Mips_BBIT132, MIPS_INS_BBIT132,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_CNMIPS, 0 }, 1, 0
#endif
},
{
Mips_BC, MIPS_INS_BC,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC0F, MIPS_INS_BC0F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC0FL, MIPS_INS_BC0FL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC0T, MIPS_INS_BC0T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC0TL, MIPS_INS_BC0TL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1EQZ, MIPS_INS_BC1EQZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC1F, MIPS_INS_BC1F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1FL, MIPS_INS_BC1FL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1F_MM, MIPS_INS_BC1F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BC1NEZ, MIPS_INS_BC1NEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC1T, MIPS_INS_BC1T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1TL, MIPS_INS_BC1TL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1T_MM, MIPS_INS_BC1T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BC2EQZ, MIPS_INS_BC2EQZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC2F, MIPS_INS_BC2F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC2FL, MIPS_INS_BC2FL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC2NEZ, MIPS_INS_BC2NEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC2T, MIPS_INS_BC2T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC2TL, MIPS_INS_BC2TL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC3F, MIPS_INS_BC3F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC3FL, MIPS_INS_BC3FL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC3T, MIPS_INS_BC3T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC3TL, MIPS_INS_BC3TL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BCLRI_B, MIPS_INS_BCLRI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BCLRI_D, MIPS_INS_BCLRI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BCLRI_H, MIPS_INS_BCLRI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BCLRI_W, MIPS_INS_BCLRI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BCLR_B, MIPS_INS_BCLR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BCLR_D, MIPS_INS_BCLR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BCLR_H, MIPS_INS_BCLR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BCLR_W, MIPS_INS_BCLR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BEQ, MIPS_INS_BEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BEQ64, MIPS_INS_BEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BEQC, MIPS_INS_BEQC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BEQL, MIPS_INS_BEQL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BEQZ16_MM, MIPS_INS_BEQZ16,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BEQZALC, MIPS_INS_BEQZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BEQZC, MIPS_INS_BEQZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BEQZC_MM, MIPS_INS_BEQZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BEQ_MM, MIPS_INS_BEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BGEC, MIPS_INS_BGEC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGEUC, MIPS_INS_BGEUC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGEZ, MIPS_INS_BGEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BGEZ64, MIPS_INS_BGEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BGEZAL, MIPS_INS_BGEZAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_BGEZALC, MIPS_INS_BGEZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGEZALL, MIPS_INS_BGEZALL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_BGEZALS_MM, MIPS_INS_BGEZALS,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BGEZAL_MM, MIPS_INS_BGEZAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BGEZC, MIPS_INS_BGEZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGEZL, MIPS_INS_BGEZL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BGEZ_MM, MIPS_INS_BGEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BGTZ, MIPS_INS_BGTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BGTZ64, MIPS_INS_BGTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BGTZALC, MIPS_INS_BGTZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGTZC, MIPS_INS_BGTZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGTZL, MIPS_INS_BGTZL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BGTZ_MM, MIPS_INS_BGTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BINSLI_B, MIPS_INS_BINSLI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSLI_D, MIPS_INS_BINSLI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSLI_H, MIPS_INS_BINSLI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSLI_W, MIPS_INS_BINSLI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSL_B, MIPS_INS_BINSL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSL_D, MIPS_INS_BINSL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSL_H, MIPS_INS_BINSL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSL_W, MIPS_INS_BINSL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSRI_B, MIPS_INS_BINSRI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSRI_D, MIPS_INS_BINSRI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSRI_H, MIPS_INS_BINSRI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSRI_W, MIPS_INS_BINSRI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSR_B, MIPS_INS_BINSR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSR_D, MIPS_INS_BINSR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSR_H, MIPS_INS_BINSR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BINSR_W, MIPS_INS_BINSR,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BITREV, MIPS_INS_BITREV,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_BITSWAP, MIPS_INS_BITSWAP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_BLEZ, MIPS_INS_BLEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BLEZ64, MIPS_INS_BLEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BLEZALC, MIPS_INS_BLEZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLEZC, MIPS_INS_BLEZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLEZL, MIPS_INS_BLEZL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BLEZ_MM, MIPS_INS_BLEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BLTC, MIPS_INS_BLTC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLTUC, MIPS_INS_BLTUC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLTZ, MIPS_INS_BLTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BLTZ64, MIPS_INS_BLTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BLTZAL, MIPS_INS_BLTZAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_BLTZALC, MIPS_INS_BLTZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLTZALL, MIPS_INS_BLTZALL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_BLTZALS_MM, MIPS_INS_BLTZALS,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BLTZAL_MM, MIPS_INS_BLTZAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BLTZC, MIPS_INS_BLTZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLTZL, MIPS_INS_BLTZL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BLTZ_MM, MIPS_INS_BLTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BMNZI_B, MIPS_INS_BMNZI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BMNZ_V, MIPS_INS_BMNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BMZI_B, MIPS_INS_BMZI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BMZ_V, MIPS_INS_BMZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BNE, MIPS_INS_BNE,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BNE64, MIPS_INS_BNE,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BNEC, MIPS_INS_BNEC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BNEGI_B, MIPS_INS_BNEGI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BNEGI_D, MIPS_INS_BNEGI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BNEGI_H, MIPS_INS_BNEGI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BNEGI_W, MIPS_INS_BNEGI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BNEG_B, MIPS_INS_BNEG,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BNEG_D, MIPS_INS_BNEG,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BNEG_H, MIPS_INS_BNEG,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BNEG_W, MIPS_INS_BNEG,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BNEL, MIPS_INS_BNEL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BNEZ16_MM, MIPS_INS_BNEZ16,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BNEZALC, MIPS_INS_BNEZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BNEZC, MIPS_INS_BNEZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BNEZC_MM, MIPS_INS_BNEZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BNE_MM, MIPS_INS_BNE,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BNVC, MIPS_INS_BNVC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BNZ_B, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BNZ_D, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BNZ_H, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BNZ_V, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BNZ_W, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BOVC, MIPS_INS_BOVC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BPOSGE32, MIPS_INS_BPOSGE32,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 1, 0
#endif
},
{
Mips_BREAK, MIPS_INS_BREAK,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
#endif
},
{
Mips_BREAK16_MM, MIPS_INS_BREAK16,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BREAK_MM, MIPS_INS_BREAK,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BSELI_B, MIPS_INS_BSELI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BSEL_V, MIPS_INS_BSEL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BSETI_B, MIPS_INS_BSETI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BSETI_D, MIPS_INS_BSETI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BSETI_H, MIPS_INS_BSETI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BSETI_W, MIPS_INS_BSETI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BSET_B, MIPS_INS_BSET,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BSET_D, MIPS_INS_BSET,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BSET_H, MIPS_INS_BSET,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BSET_W, MIPS_INS_BSET,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_BZ_B, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BZ_D, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BZ_H, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BZ_V, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BZ_W, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BeqzRxImm16, MIPS_INS_BEQZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BeqzRxImmX16, MIPS_INS_BEQZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_Bimm16, MIPS_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BimmX16, MIPS_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BnezRxImm16, MIPS_INS_BNEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BnezRxImmX16, MIPS_INS_BNEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_Break16, MIPS_INS_BREAK,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_Bteqz16, MIPS_INS_BTEQZ,
#ifndef CAPSTONE_DIET
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BteqzX16, MIPS_INS_BTEQZ,
#ifndef CAPSTONE_DIET
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_Btnez16, MIPS_INS_BTNEZ,
#ifndef CAPSTONE_DIET
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BtnezX16, MIPS_INS_BTNEZ,
#ifndef CAPSTONE_DIET
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_CACHE, MIPS_INS_CACHE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_CACHE_MM, MIPS_INS_CACHE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CACHE_R6, MIPS_INS_CACHE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CEIL_L_D64, MIPS_INS_CEIL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CEIL_L_S, MIPS_INS_CEIL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CEIL_W_D32, MIPS_INS_CEIL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CEIL_W_D64, MIPS_INS_CEIL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CEIL_W_MM, MIPS_INS_CEIL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CEIL_W_S, MIPS_INS_CEIL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
#endif
},
{
Mips_CEIL_W_S_MM, MIPS_INS_CEIL,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CEQI_B, MIPS_INS_CEQI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CEQI_D, MIPS_INS_CEQI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CEQI_H, MIPS_INS_CEQI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CEQI_W, MIPS_INS_CEQI,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CEQ_B, MIPS_INS_CEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CEQ_D, MIPS_INS_CEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CEQ_H, MIPS_INS_CEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CEQ_W, MIPS_INS_CEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CFC1, MIPS_INS_CFC1,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
#endif
},
{
Mips_CFC1_MM, MIPS_INS_CFC1,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CFCMSA, MIPS_INS_CFCMSA,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CINS, MIPS_INS_CINS,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
#endif
},
{
Mips_CINS32, MIPS_INS_CINS32,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
#endif
},
{
Mips_CLASS_D, MIPS_INS_CLASS,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CLASS_S, MIPS_INS_CLASS,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CLEI_S_B, MIPS_INS_CLEI_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLEI_S_D, MIPS_INS_CLEI_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLEI_S_H, MIPS_INS_CLEI_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLEI_S_W, MIPS_INS_CLEI_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLEI_U_B, MIPS_INS_CLEI_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLEI_U_D, MIPS_INS_CLEI_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLEI_U_H, MIPS_INS_CLEI_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLEI_U_W, MIPS_INS_CLEI_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLE_S_B, MIPS_INS_CLE_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLE_S_D, MIPS_INS_CLE_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLE_S_H, MIPS_INS_CLE_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLE_S_W, MIPS_INS_CLE_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLE_U_B, MIPS_INS_CLE_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLE_U_D, MIPS_INS_CLE_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLE_U_H, MIPS_INS_CLE_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLE_U_W, MIPS_INS_CLE_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLO, MIPS_INS_CLO,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_CLO_MM, MIPS_INS_CLO,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CLO_R6, MIPS_INS_CLO,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CLTI_S_B, MIPS_INS_CLTI_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLTI_S_D, MIPS_INS_CLTI_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLTI_S_H, MIPS_INS_CLTI_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLTI_S_W, MIPS_INS_CLTI_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLTI_U_B, MIPS_INS_CLTI_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLTI_U_D, MIPS_INS_CLTI_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLTI_U_H, MIPS_INS_CLTI_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLTI_U_W, MIPS_INS_CLTI_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLT_S_B, MIPS_INS_CLT_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLT_S_D, MIPS_INS_CLT_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLT_S_H, MIPS_INS_CLT_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLT_S_W, MIPS_INS_CLT_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLT_U_B, MIPS_INS_CLT_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLT_U_D, MIPS_INS_CLT_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLT_U_H, MIPS_INS_CLT_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLT_U_W, MIPS_INS_CLT_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CLZ, MIPS_INS_CLZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_CLZ_MM, MIPS_INS_CLZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CLZ_R6, MIPS_INS_CLZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
#endif
},
{
Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_CMPGU_LE_QB, MIPS_INS_CMPGU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_CMPGU_LT_QB, MIPS_INS_CMPGU,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_CMPU_EQ_QB, MIPS_INS_CMPU,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_CMPU_LE_QB, MIPS_INS_CMPU,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_CMPU_LT_QB, MIPS_INS_CMPU,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_CMP_EQ_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_EQ_PH, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_CMP_EQ_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_F_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_F_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_LE_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_LE_PH, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_CMP_LE_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_LT_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_LT_PH, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif
},
{
Mips_CMP_LT_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SAF_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SAF_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SEQ_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SEQ_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SLE_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SLE_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SLT_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SLT_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SUEQ_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SUEQ_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SULE_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SULE_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SULT_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SULT_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SUN_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_SUN_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_UEQ_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_UEQ_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_ULE_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_ULE_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_ULT_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_ULT_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_UN_D, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_CMP_UN_S, MIPS_INS_CMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
#endif
},
{
Mips_COPY_S_B, MIPS_INS_COPY_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_COPY_S_D, MIPS_INS_COPY_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
#endif
},
{
Mips_COPY_S_H, MIPS_INS_COPY_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_COPY_S_W, MIPS_INS_COPY_S,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_COPY_U_B, MIPS_INS_COPY_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_COPY_U_D, MIPS_INS_COPY_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
#endif
},
{
Mips_COPY_U_H, MIPS_INS_COPY_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_COPY_U_W, MIPS_INS_COPY_U,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CTC1, MIPS_INS_CTC1,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
#endif
},
{
Mips_CTC1_MM, MIPS_INS_CTC1,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CTCMSA, MIPS_INS_CTCMSA,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
#endif
},
{
Mips_CVT_D32_S, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_D32_W, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_D32_W_MM, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CVT_D64_L, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_D64_S, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_D64_W, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_D_S_MM, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CVT_L_D64, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0
#endif
},
{
Mips_CVT_L_D64_MM, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CVT_L_S, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0
#endif
},
{
Mips_CVT_L_S_MM, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CVT_S_D32, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_S_D32_MM, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CVT_S_D64, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_S_L, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_S_W, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
#endif
},
{
Mips_CVT_S_W_MM, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CVT_W_D32, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_W_D64, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_CVT_W_MM, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_CVT_W_S, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
#endif
},
{
Mips_CVT_W_S_MM, MIPS_INS_CVT,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_C_EQ_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_EQ_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_EQ_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_F_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_F_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_F_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_LE_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_LE_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_LE_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_LT_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_LT_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_LT_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_NGE_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_NGE_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_NGE_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_NGLE_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_NGLE_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_NGLE_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_NGL_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_NGL_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_NGL_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_NGT_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_NGT_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_NGT_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_OLE_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_OLE_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_OLE_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_OLT_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_OLT_D64, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
#endif
},
{
Mips_C_OLT_S, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_C_SEQ_D32, MIPS_INS_C,
#ifndef CAPSTONE_DIET
{