| // This is auto-gen data for Capstone engine (www.capstone-engine.org) |
| // By Nguyen Anh Quynh <aquynh@gmail.com> |
| |
| { |
| ARM_ADCri, ARM_INS_ADC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ADCrr, ARM_INS_ADC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ADCrsi, ARM_INS_ADC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ADCrsr, ARM_INS_ADC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ADDri, ARM_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ADDrr, ARM_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ADDrsi, ARM_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ADDrsr, ARM_INS_ADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ADR, ARM_INS_ADR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_AESD, ARM_INS_AESD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_AESE, ARM_INS_AESE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_AESIMC, ARM_INS_AESIMC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_AESMC, ARM_INS_AESMC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ANDri, ARM_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ANDrr, ARM_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ANDrsi, ARM_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ANDrsr, ARM_INS_AND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_BFC, ARM_INS_BFC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_BFI, ARM_INS_BFI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_BICri, ARM_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_BICrr, ARM_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_BICrsi, ARM_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_BICrsr, ARM_INS_BIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_BKPT, ARM_INS_BKPT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_BL, ARM_INS_BL, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| ARM_BLX, ARM_INS_BLX, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_V5T, 0 }, 0, 1 |
| #endif |
| }, |
| { |
| ARM_BLX_pred, ARM_INS_BLX, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 1 |
| #endif |
| }, |
| { |
| ARM_BLXi, ARM_INS_BLX, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| ARM_BL_pred, ARM_INS_BL, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| ARM_BX, ARM_INS_BX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 |
| #endif |
| }, |
| { |
| ARM_BXJ, ARM_INS_BXJ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, 0 }, 0, 1 |
| #endif |
| }, |
| { |
| ARM_BX_RET, ARM_INS_BX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 |
| #endif |
| }, |
| { |
| ARM_BX_pred, ARM_INS_BX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_V4T, 0 }, 0, 1 |
| #endif |
| }, |
| { |
| ARM_Bcc, ARM_INS_B, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_PC, 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0 |
| #endif |
| }, |
| { |
| ARM_CDP, ARM_INS_CDP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CDP2, ARM_INS_CDP2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CLREX, ARM_INS_CLREX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CLZ, ARM_INS_CLZ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CMNri, ARM_INS_CMN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CMNzrr, ARM_INS_CMN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CMNzrsi, ARM_INS_CMN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CMNzrsr, ARM_INS_CMN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CMPri, ARM_INS_CMP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CMPrr, ARM_INS_CMP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CMPrsi, ARM_INS_CMP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CMPrsr, ARM_INS_CMP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CPS1p, ARM_INS_CPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CPS2p, ARM_INS_CPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CPS3p, ARM_INS_CPS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CRC32B, ARM_INS_CRC32B, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CRC32CB, ARM_INS_CRC32CB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CRC32CH, ARM_INS_CRC32CH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CRC32CW, ARM_INS_CRC32CW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CRC32H, ARM_INS_CRC32H, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_CRC32W, ARM_INS_CRC32W, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, ARM_GRP_CRC, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_DBG, ARM_INS_DBG, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_DMB, ARM_INS_DMB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_DSB, ARM_INS_DSB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_EORri, ARM_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_EORrr, ARM_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_EORrsi, ARM_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_EORrsr, ARM_INS_EOR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ERET, ARM_INS_ERET, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_FCONSTD, ARM_INS_VMOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP3, ARM_GRP_DPVFP, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_FCONSTS, ARM_INS_VMOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP3, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_FLDMXIA, ARM_INS_FLDMIAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_FMSTAT, ARM_INS_VMRS, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_FSTMXIA, ARM_INS_FSTMIAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_HINT, ARM_INS_HINT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_HLT, ARM_INS_HLT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_HVC, ARM_INS_HVC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ISB, ARM_INS_ISB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_DATABARRIER, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDA, ARM_INS_LDA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDAB, ARM_INS_LDAB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDAEX, ARM_INS_LDAEX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDAEXB, ARM_INS_LDAEXB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDAEXD, ARM_INS_LDAEXD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDAEXH, ARM_INS_LDAEXH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDAH, ARM_INS_LDAH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC2L_OFFSET, ARM_INS_LDC2L, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC2L_OPTION, ARM_INS_LDC2L, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC2L_POST, ARM_INS_LDC2L, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC2L_PRE, ARM_INS_LDC2L, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC2_OFFSET, ARM_INS_LDC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC2_OPTION, ARM_INS_LDC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC2_POST, ARM_INS_LDC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC2_PRE, ARM_INS_LDC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDCL_OFFSET, ARM_INS_LDCL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDCL_OPTION, ARM_INS_LDCL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDCL_POST, ARM_INS_LDCL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDCL_PRE, ARM_INS_LDCL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC_OFFSET, ARM_INS_LDC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC_OPTION, ARM_INS_LDC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC_POST, ARM_INS_LDC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDC_PRE, ARM_INS_LDC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDMDA, ARM_INS_LDMDA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDMDA_UPD, ARM_INS_LDMDA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDMDB, ARM_INS_LDMDB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDMDB_UPD, ARM_INS_LDMDB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDMIA, ARM_INS_LDM, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDMIA_UPD, ARM_INS_LDM, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDMIB, ARM_INS_LDMIB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDMIB_UPD, ARM_INS_LDMIB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRBT_POST_IMM, ARM_INS_LDRBT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRBT_POST_REG, ARM_INS_LDRBT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRB_POST_IMM, ARM_INS_LDRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRB_POST_REG, ARM_INS_LDRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRB_PRE_IMM, ARM_INS_LDRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRB_PRE_REG, ARM_INS_LDRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRBi12, ARM_INS_LDRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRBrs, ARM_INS_LDRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRD, ARM_INS_LDRD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRD_POST, ARM_INS_LDRD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRD_PRE, ARM_INS_LDRD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDREX, ARM_INS_LDREX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDREXB, ARM_INS_LDREXB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDREXD, ARM_INS_LDREXD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDREXH, ARM_INS_LDREXH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRH, ARM_INS_LDRH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRHTi, ARM_INS_LDRHT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRHTr, ARM_INS_LDRHT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRH_POST, ARM_INS_LDRH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRH_PRE, ARM_INS_LDRH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSB, ARM_INS_LDRSB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSBTi, ARM_INS_LDRSBT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSBTr, ARM_INS_LDRSBT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSB_POST, ARM_INS_LDRSB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSB_PRE, ARM_INS_LDRSB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSH, ARM_INS_LDRSH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSHTi, ARM_INS_LDRSHT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSHTr, ARM_INS_LDRSHT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSH_POST, ARM_INS_LDRSH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRSH_PRE, ARM_INS_LDRSH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRT_POST_IMM, ARM_INS_LDRT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRT_POST_REG, ARM_INS_LDRT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDR_POST_IMM, ARM_INS_LDR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDR_POST_REG, ARM_INS_LDR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDR_PRE_IMM, ARM_INS_LDR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDR_PRE_REG, ARM_INS_LDR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRcp, ARM_INS_LDR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRi12, ARM_INS_LDR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_LDRrs, ARM_INS_LDR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MCR, ARM_INS_MCR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MCR2, ARM_INS_MCR2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MCRR, ARM_INS_MCRR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MCRR2, ARM_INS_MCRR2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MLA, ARM_INS_MLA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MLS, ARM_INS_MLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MOVPCLR, ARM_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MOVTi16, ARM_INS_MOVT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MOVi, ARM_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MOVi16, ARM_INS_MOVW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MOVr, ARM_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MOVr_TC, ARM_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MOVsi, ARM_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MOVsr, ARM_INS_MOV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MRC, ARM_INS_MRC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MRC2, ARM_INS_MRC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MRRC, ARM_INS_MRRC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MRRC2, ARM_INS_MRRC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MRS, ARM_INS_MRS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MRSbanked, ARM_INS_MRS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MRSsys, ARM_INS_MRS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MSR, ARM_INS_MSR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MSRbanked, ARM_INS_MSR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_VIRTUALIZATION, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MSRi, ARM_INS_MSR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MUL, ARM_INS_MUL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MVNi, ARM_INS_MVN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MVNr, ARM_INS_MVN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MVNsi, ARM_INS_MVN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_MVNsr, ARM_INS_MVN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ORRri, ARM_INS_ORR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ORRrr, ARM_INS_ORR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ORRrsi, ARM_INS_ORR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_ORRrsr, ARM_INS_ORR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_PKHBT, ARM_INS_PKHBT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_PKHTB, ARM_INS_PKHTB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_PLDWi12, ARM_INS_PLDW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_PLDWrs, ARM_INS_PLDW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, ARM_GRP_MULTPRO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_PLDi12, ARM_INS_PLD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_PLDrs, ARM_INS_PLD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_PLIi12, ARM_INS_PLI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_PLIrs, ARM_INS_PLI, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V7, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QADD, ARM_INS_QADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QADD16, ARM_INS_QADD16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QADD8, ARM_INS_QADD8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QASX, ARM_INS_QASX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QDADD, ARM_INS_QDADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QDSUB, ARM_INS_QDSUB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QSAX, ARM_INS_QSAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QSUB, ARM_INS_QSUB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QSUB16, ARM_INS_QSUB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_QSUB8, ARM_INS_QSUB8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RBIT, ARM_INS_RBIT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_REV, ARM_INS_REV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_REV16, ARM_INS_REV16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_REVSH, ARM_INS_REVSH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RFEDA, ARM_INS_RFEDA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RFEDA_UPD, ARM_INS_RFEDA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RFEDB, ARM_INS_RFEDB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RFEDB_UPD, ARM_INS_RFEDB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RFEIA, ARM_INS_RFEIA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RFEIA_UPD, ARM_INS_RFEIA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RFEIB, ARM_INS_RFEIB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RFEIB_UPD, ARM_INS_RFEIB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RSBri, ARM_INS_RSB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RSBrr, ARM_INS_RSB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RSBrsi, ARM_INS_RSB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RSBrsr, ARM_INS_RSB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RSCri, ARM_INS_RSC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RSCrr, ARM_INS_RSC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RSCrsi, ARM_INS_RSC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_RSCrsr, ARM_INS_RSC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SADD16, ARM_INS_SADD16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SADD8, ARM_INS_SADD8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SASX, ARM_INS_SASX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SBCri, ARM_INS_SBC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SBCrr, ARM_INS_SBC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SBCrsi, ARM_INS_SBC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SBCrsr, ARM_INS_SBC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SBFX, ARM_INS_SBFX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SDIV, ARM_INS_SDIV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SEL, ARM_INS_SEL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SETEND, ARM_INS_SETEND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA1C, ARM_INS_SHA1C, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA1H, ARM_INS_SHA1H, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA1M, ARM_INS_SHA1M, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA1P, ARM_INS_SHA1P, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA1SU0, ARM_INS_SHA1SU0, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA1SU1, ARM_INS_SHA1SU1, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA256H, ARM_INS_SHA256H, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA256H2, ARM_INS_SHA256H2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA256SU0, ARM_INS_SHA256SU0, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHA256SU1, ARM_INS_SHA256SU1, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_V8, ARM_GRP_CRYPTO, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHADD16, ARM_INS_SHADD16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHADD8, ARM_INS_SHADD8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHASX, ARM_INS_SHASX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHSAX, ARM_INS_SHSAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHSUB16, ARM_INS_SHSUB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SHSUB8, ARM_INS_SHSUB8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMC, ARM_INS_SMC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PRIVILEGE, ARM_GRP_ARM, ARM_GRP_TRUSTZONE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLABB, ARM_INS_SMLABB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLABT, ARM_INS_SMLABT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLAD, ARM_INS_SMLAD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLADX, ARM_INS_SMLADX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLAL, ARM_INS_SMLAL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLALBB, ARM_INS_SMLALBB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLALBT, ARM_INS_SMLALBT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLALD, ARM_INS_SMLALD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLALDX, ARM_INS_SMLALDX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLALTB, ARM_INS_SMLALTB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLALTT, ARM_INS_SMLALTT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLATB, ARM_INS_SMLATB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLATT, ARM_INS_SMLATT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLAWB, ARM_INS_SMLAWB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLAWT, ARM_INS_SMLAWT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLSD, ARM_INS_SMLSD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLSDX, ARM_INS_SMLSDX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLSLD, ARM_INS_SMLSLD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMLSLDX, ARM_INS_SMLSLDX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMMLA, ARM_INS_SMMLA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMMLAR, ARM_INS_SMMLAR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMMLS, ARM_INS_SMMLS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, ARM_GRP_MULOPS, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMMLSR, ARM_INS_SMMLSR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMMUL, ARM_INS_SMMUL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMMULR, ARM_INS_SMMULR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMUAD, ARM_INS_SMUAD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMUADX, ARM_INS_SMUADX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMULBB, ARM_INS_SMULBB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMULBT, ARM_INS_SMULBT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMULL, ARM_INS_SMULL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMULTB, ARM_INS_SMULTB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMULTT, ARM_INS_SMULTT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMULWB, ARM_INS_SMULWB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMULWT, ARM_INS_SMULWT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMUSD, ARM_INS_SMUSD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SMUSDX, ARM_INS_SMUSDX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SRSDA, ARM_INS_SRSDA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SRSDA_UPD, ARM_INS_SRSDA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SRSDB, ARM_INS_SRSDB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SRSDB_UPD, ARM_INS_SRSDB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SRSIA, ARM_INS_SRSIA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SRSIA_UPD, ARM_INS_SRSIA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SRSIB, ARM_INS_SRSIB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SRSIB_UPD, ARM_INS_SRSIB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SSAT, ARM_INS_SSAT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SSAT16, ARM_INS_SSAT16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SSAX, ARM_INS_SSAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SSUB16, ARM_INS_SSUB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SSUB8, ARM_INS_SSUB8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC2L_OFFSET, ARM_INS_STC2L, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC2L_OPTION, ARM_INS_STC2L, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC2L_POST, ARM_INS_STC2L, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC2L_PRE, ARM_INS_STC2L, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC2_OFFSET, ARM_INS_STC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC2_OPTION, ARM_INS_STC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC2_POST, ARM_INS_STC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC2_PRE, ARM_INS_STC2, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STCL_OFFSET, ARM_INS_STCL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STCL_OPTION, ARM_INS_STCL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STCL_POST, ARM_INS_STCL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STCL_PRE, ARM_INS_STCL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC_OFFSET, ARM_INS_STC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC_OPTION, ARM_INS_STC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC_POST, ARM_INS_STC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STC_PRE, ARM_INS_STC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STL, ARM_INS_STL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STLB, ARM_INS_STLB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STLEX, ARM_INS_STLEX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STLEXB, ARM_INS_STLEXB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STLEXD, ARM_INS_STLEXD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STLEXH, ARM_INS_STLEXH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STLH, ARM_INS_STLH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STMDA, ARM_INS_STMDA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STMDA_UPD, ARM_INS_STMDA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STMDB, ARM_INS_STMDB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STMDB_UPD, ARM_INS_STMDB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STMIA, ARM_INS_STM, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STMIA_UPD, ARM_INS_STM, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STMIB, ARM_INS_STMIB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STMIB_UPD, ARM_INS_STMIB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRBT_POST_IMM, ARM_INS_STRBT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRBT_POST_REG, ARM_INS_STRBT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRB_POST_IMM, ARM_INS_STRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRB_POST_REG, ARM_INS_STRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRB_PRE_IMM, ARM_INS_STRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRB_PRE_REG, ARM_INS_STRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRBi12, ARM_INS_STRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRBrs, ARM_INS_STRB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRD, ARM_INS_STRD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRD_POST, ARM_INS_STRD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRD_PRE, ARM_INS_STRD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STREX, ARM_INS_STREX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STREXB, ARM_INS_STREXB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STREXD, ARM_INS_STREXD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STREXH, ARM_INS_STREXH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRH, ARM_INS_STRH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRHTi, ARM_INS_STRHT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRHTr, ARM_INS_STRHT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRH_POST, ARM_INS_STRH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRH_PRE, ARM_INS_STRH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRT_POST_IMM, ARM_INS_STRT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRT_POST_REG, ARM_INS_STRT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STR_POST_IMM, ARM_INS_STR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STR_POST_REG, ARM_INS_STR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STR_PRE_IMM, ARM_INS_STR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STR_PRE_REG, ARM_INS_STR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRi12, ARM_INS_STR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_STRrs, ARM_INS_STR, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SUBri, ARM_INS_SUB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SUBrr, ARM_INS_SUB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SUBrsi, ARM_INS_SUB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SUBrsr, ARM_INS_SUB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SVC, ARM_INS_SVC, |
| #ifndef CAPSTONE_DIET |
| { ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_ARM, ARM_GRP_INT, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SWP, ARM_INS_SWP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SWPB, ARM_INS_SWPB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SXTAB, ARM_INS_SXTAB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SXTAB16, ARM_INS_SXTAB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SXTAH, ARM_INS_SXTAH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SXTB, ARM_INS_SXTB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SXTB16, ARM_INS_SXTB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_SXTH, ARM_INS_SXTH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TEQri, ARM_INS_TEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TEQrr, ARM_INS_TEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TEQrsi, ARM_INS_TEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TEQrsr, ARM_INS_TEQ, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TRAP, ARM_INS_TRAP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TRAPNaCl, ARM_INS_TRAP, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TSTri, ARM_INS_TST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TSTrr, ARM_INS_TST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TSTrsi, ARM_INS_TST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_TSTrsr, ARM_INS_TST, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UADD16, ARM_INS_UADD16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UADD8, ARM_INS_UADD8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UASX, ARM_INS_UASX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UBFX, ARM_INS_UBFX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UDF, ARM_INS_UDF, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UDIV, ARM_INS_UDIV, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UHADD16, ARM_INS_UHADD16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UHADD8, ARM_INS_UHADD8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UHASX, ARM_INS_UHASX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UHSAX, ARM_INS_UHSAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UHSUB16, ARM_INS_UHSUB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UHSUB8, ARM_INS_UHSUB8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UMAAL, ARM_INS_UMAAL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UMLAL, ARM_INS_UMLAL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UMULL, ARM_INS_UMULL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UQADD16, ARM_INS_UQADD16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UQADD8, ARM_INS_UQADD8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UQASX, ARM_INS_UQASX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UQSAX, ARM_INS_UQSAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UQSUB16, ARM_INS_UQSUB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UQSUB8, ARM_INS_UQSUB8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_USAD8, ARM_INS_USAD8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_USADA8, ARM_INS_USADA8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_USAT, ARM_INS_USAT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_USAT16, ARM_INS_USAT16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_USAX, ARM_INS_USAX, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_USUB16, ARM_INS_USUB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_USUB8, ARM_INS_USUB8, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UXTAB, ARM_INS_UXTAB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UXTAB16, ARM_INS_UXTAB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UXTAH, ARM_INS_UXTAH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UXTB, ARM_INS_UXTB, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UXTB16, ARM_INS_UXTB16, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_UXTH, ARM_INS_UXTH, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABALsv2i64, ARM_INS_VABAL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABALsv4i32, ARM_INS_VABAL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABALsv8i16, ARM_INS_VABAL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABALuv2i64, ARM_INS_VABAL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABALuv4i32, ARM_INS_VABAL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABALuv8i16, ARM_INS_VABAL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAsv16i8, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAsv2i32, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAsv4i16, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAsv4i32, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAsv8i16, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAsv8i8, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAuv16i8, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAuv2i32, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAuv4i16, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAuv4i32, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAuv8i16, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABAuv8i8, ARM_INS_VABA, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDLsv2i64, ARM_INS_VABDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDLsv4i32, ARM_INS_VABDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDLsv8i16, ARM_INS_VABDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDLuv2i64, ARM_INS_VABDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDLuv4i32, ARM_INS_VABDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDLuv8i16, ARM_INS_VABDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDfd, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDfq, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDsv16i8, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDsv2i32, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDsv4i16, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDsv4i32, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDsv8i16, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDsv8i8, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDuv16i8, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDuv2i32, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDuv4i16, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDuv4i32, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDuv8i16, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABDuv8i8, ARM_INS_VABD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSD, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSS, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSfd, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSfq, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSv16i8, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSv2i32, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSv4i16, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSv4i32, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSv8i16, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VABSv8i8, ARM_INS_VABS, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VACGEd, ARM_INS_VACGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VACGEq, ARM_INS_VACGE, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VACGTd, ARM_INS_VACGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VACGTq, ARM_INS_VACGT, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDD, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, ARM_GRP_DPVFP, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDHNv2i32, ARM_INS_VADDHN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDHNv4i16, ARM_INS_VADDHN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDHNv8i8, ARM_INS_VADDHN, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDLsv2i64, ARM_INS_VADDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDLsv4i32, ARM_INS_VADDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDLsv8i16, ARM_INS_VADDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDLuv2i64, ARM_INS_VADDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDLuv4i32, ARM_INS_VADDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDLuv8i16, ARM_INS_VADDL, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDS, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_VFP2, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDWsv2i64, ARM_INS_VADDW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDWsv4i32, ARM_INS_VADDW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDWsv8i16, ARM_INS_VADDW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDWuv2i64, ARM_INS_VADDW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDWuv4i32, ARM_INS_VADDW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDWuv8i16, ARM_INS_VADDW, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDfd, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDfq, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDv16i8, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDv1i64, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDv2i32, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDv2i64, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDv4i16, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDv4i32, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDv8i16, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VADDv8i8, ARM_INS_VADD, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VANDd, ARM_INS_VAND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VANDq, ARM_INS_VAND, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VBICd, ARM_INS_VBIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VBICiv2i32, ARM_INS_VBIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VBICiv4i16, ARM_INS_VBIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VBICiv4i32, ARM_INS_VBIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VBICiv8i16, ARM_INS_VBIC, |
| #ifndef CAPSTONE_DIET |
| { 0 }, { 0 }, { ARM_GRP_NEON, 0 }, 0, 0 |
| #endif |
| }, |
| { |
| ARM_VBICq, ARM_INS_VBIC, |
| #ifndef CAPSTONE_DIET |
|
