blob: e432dfc8b45e93ba8e2e9ddfdb1b047f55a572be [file] [log] [blame]
/* CPU data for mep.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996-2016 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include "sysdep.h"
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "mep-desc.h"
#include "mep-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
/* Attributes. */
static const CGEN_ATTR_ENTRY bool_attr[] =
{
{ "#f", 0 },
{ "#t", 1 },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
{
{ "base", MACH_BASE },
{ "mep", MACH_MEP },
{ "h1", MACH_H1 },
{ "c5", MACH_C5 },
{ "max", MACH_MAX },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
{
{ "mep", ISA_MEP },
{ "ext_core1", ISA_EXT_CORE1 },
{ "ext_cop1_16", ISA_EXT_COP1_16 },
{ "ext_cop1_32", ISA_EXT_COP1_32 },
{ "ext_cop1_48", ISA_EXT_COP1_48 },
{ "ext_cop1_64", ISA_EXT_COP1_64 },
{ "max", ISA_MAX },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY CDATA_attr[] ATTRIBUTE_UNUSED =
{
{ "LABEL", CDATA_LABEL },
{ "REGNUM", CDATA_REGNUM },
{ "FMAX_FLOAT", CDATA_FMAX_FLOAT },
{ "FMAX_INT", CDATA_FMAX_INT },
{ "POINTER", CDATA_POINTER },
{ "LONG", CDATA_LONG },
{ "ULONG", CDATA_ULONG },
{ "SHORT", CDATA_SHORT },
{ "USHORT", CDATA_USHORT },
{ "CHAR", CDATA_CHAR },
{ "UCHAR", CDATA_UCHAR },
{ "CP_DATA_BUS_INT", CDATA_CP_DATA_BUS_INT },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY CPTYPE_attr[] ATTRIBUTE_UNUSED =
{
{ "CP_DATA_BUS_INT", CPTYPE_CP_DATA_BUS_INT },
{ "VECT", CPTYPE_VECT },
{ "V2SI", CPTYPE_V2SI },
{ "V4HI", CPTYPE_V4HI },
{ "V8QI", CPTYPE_V8QI },
{ "V2USI", CPTYPE_V2USI },
{ "V4UHI", CPTYPE_V4UHI },
{ "V8UQI", CPTYPE_V8UQI },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY CRET_attr[] ATTRIBUTE_UNUSED =
{
{ "VOID", CRET_VOID },
{ "FIRST", CRET_FIRST },
{ "FIRSTCOPY", CRET_FIRSTCOPY },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
{
{"integer", 1},
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY LATENCY_attr [] ATTRIBUTE_UNUSED =
{
{"integer", 0},
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY CONFIG_attr[] ATTRIBUTE_UNUSED =
{
{ "NONE", CONFIG_NONE },
{ "default", CONFIG_DEFAULT },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY SLOTS_attr[] ATTRIBUTE_UNUSED =
{
{ "CORE", SLOTS_CORE },
{ "C3", SLOTS_C3 },
{ "P0S", SLOTS_P0S },
{ "P0", SLOTS_P0 },
{ "P1", SLOTS_P1 },
{ 0, 0 }
};
const CGEN_ATTR_TABLE mep_cgen_ifield_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "ISA", & ISA_attr[0], & ISA_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
{ "RESERVED", &bool_attr[0], &bool_attr[0] },
{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
{ "SIGNED", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
const CGEN_ATTR_TABLE mep_cgen_hardware_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "ISA", & ISA_attr[0], & ISA_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
{ "PC", &bool_attr[0], &bool_attr[0] },
{ "PROFILE", &bool_attr[0], &bool_attr[0] },
{ "IS_FLOAT", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
const CGEN_ATTR_TABLE mep_cgen_operand_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "ISA", & ISA_attr[0], & ISA_attr[0] },
{ "CDATA", & CDATA_attr[0], & CDATA_attr[0] },
{ "ALIGN", & ALIGN_attr[0], & ALIGN_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
{ "SIGNED", &bool_attr[0], &bool_attr[0] },
{ "NEGATIVE", &bool_attr[0], &bool_attr[0] },
{ "RELAX", &bool_attr[0], &bool_attr[0] },
{ "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
{ "RELOC_IMPLIES_OVERFLOW", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
const CGEN_ATTR_TABLE mep_cgen_insn_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "ISA", & ISA_attr[0], & ISA_attr[0] },
{ "CPTYPE", & CPTYPE_attr[0], & CPTYPE_attr[0] },
{ "CRET", & CRET_attr[0], & CRET_attr[0] },
{ "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] },
{ "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] },
{ "SLOTS", & SLOTS_attr[0], & SLOTS_attr[0] },
{ "ALIAS", &bool_attr[0], &bool_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
{ "COND-CTI", &bool_attr[0], &bool_attr[0] },
{ "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
{ "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
{ "RELAXABLE", &bool_attr[0], &bool_attr[0] },
{ "RELAXED", &bool_attr[0], &bool_attr[0] },
{ "NO-DIS", &bool_attr[0], &bool_attr[0] },
{ "PBB", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_BIT_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_MUL_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_DIV_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_DEBUG_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_LDZ_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_ABS_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_AVE_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_MINMAX_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_CLIP_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_SAT_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_UCI_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_DSP_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_CP_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_CP64_INSN", &bool_attr[0], &bool_attr[0] },
{ "OPTIONAL_VLIW64", &bool_attr[0], &bool_attr[0] },
{ "MAY_TRAP", &bool_attr[0], &bool_attr[0] },
{ "VLIW_ALONE", &bool_attr[0], &bool_attr[0] },
{ "VLIW_NO_CORE_NOP", &bool_attr[0], &bool_attr[0] },
{ "VLIW_NO_COP_NOP", &bool_attr[0], &bool_attr[0] },
{ "VLIW64_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
{ "VLIW32_NO_MATCHING_NOP", &bool_attr[0], &bool_attr[0] },
{ "VOLATILE", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
/* Instruction set variants. */
static const CGEN_ISA mep_cgen_isa_table[] = {
{ "mep", 32, 32, 16, 32 },
{ "ext_core1", 32, 32, 16, 32 },
{ "ext_cop1_16", 32, 32, 32, 32 },
{ "ext_cop1_32", 32, 32, 32, 32 },
{ "ext_cop1_48", 32, 32, 32, 32 },
{ "ext_cop1_64", 32, 32, 32, 32 },
{ 0, 0, 0, 0, 0 }
};
/* Machine variants. */
static const CGEN_MACH mep_cgen_mach_table[] = {
{ "mep", "mep", MACH_MEP, 16 },
{ "h1", "h1", MACH_H1, 16 },
{ "c5", "c5", MACH_C5, 16 },
{ 0, 0, 0, 0 }
};
static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_gpr_entries[] =
{
{ "$0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "$1", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "$2", 2, {0, {{{0, 0}}}}, 0, 0 },
{ "$3", 3, {0, {{{0, 0}}}}, 0, 0 },
{ "$4", 4, {0, {{{0, 0}}}}, 0, 0 },
{ "$5", 5, {0, {{{0, 0}}}}, 0, 0 },
{ "$6", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "$7", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "$8", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "$9", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "$10", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "$11", 11, {0, {{{0, 0}}}}, 0, 0 },
{ "$fp", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "$tp", 13, {0, {{{0, 0}}}}, 0, 0 },
{ "$gp", 14, {0, {{{0, 0}}}}, 0, 0 },
{ "$sp", 15, {0, {{{0, 0}}}}, 0, 0 },
{ "$12", 12, {0, {{{0, 0}}}}, 0, 0 },
{ "$13", 13, {0, {{{0, 0}}}}, 0, 0 },
{ "$14", 14, {0, {{{0, 0}}}}, 0, 0 },
{ "$15", 15, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD mep_cgen_opval_h_gpr =
{
& mep_cgen_opval_h_gpr_entries[0],
20,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_csr_entries[] =
{
{ "$pc", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "$lp", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "$sar", 2, {0, {{{0, 0}}}}, 0, 0 },
{ "$rpb", 4, {0, {{{0, 0}}}}, 0, 0 },
{ "$rpe", 5, {0, {{{0, 0}}}}, 0, 0 },
{ "$rpc", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "$hi", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "$lo", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "$mb0", 12, {0, {{{0, 0}}}}, 0, 0 },
{ "$me0", 13, {0, {{{0, 0}}}}, 0, 0 },
{ "$mb1", 14, {0, {{{0, 0}}}}, 0, 0 },
{ "$me1", 15, {0, {{{0, 0}}}}, 0, 0 },
{ "$psw", 16, {0, {{{0, 0}}}}, 0, 0 },
{ "$id", 17, {0, {{{0, 0}}}}, 0, 0 },
{ "$tmp", 18, {0, {{{0, 0}}}}, 0, 0 },
{ "$epc", 19, {0, {{{0, 0}}}}, 0, 0 },
{ "$exc", 20, {0, {{{0, 0}}}}, 0, 0 },
{ "$cfg", 21, {0, {{{0, 0}}}}, 0, 0 },
{ "$npc", 23, {0, {{{0, 0}}}}, 0, 0 },
{ "$dbg", 24, {0, {{{0, 0}}}}, 0, 0 },
{ "$depc", 25, {0, {{{0, 0}}}}, 0, 0 },
{ "$opt", 26, {0, {{{0, 0}}}}, 0, 0 },
{ "$rcfg", 27, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccfg", 28, {0, {{{0, 0}}}}, 0, 0 },
{ "$vid", 22, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD mep_cgen_opval_h_csr =
{
& mep_cgen_opval_h_csr_entries[0],
25,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr64_entries[] =
{
{ "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
{ "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
{ "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
{ "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
{ "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
{ "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
{ "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
{ "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
{ "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
{ "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
{ "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
{ "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
{ "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
{ "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
{ "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
{ "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
{ "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
{ "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
{ "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
{ "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
{ "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
{ "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
{ "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
{ "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
{ "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD mep_cgen_opval_h_cr64 =
{
& mep_cgen_opval_h_cr64_entries[0],
32,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_entries[] =
{
{ "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
{ "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
{ "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
{ "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
{ "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "$c7", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "$c8", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "$c9", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "$c10", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "$c11", 11, {0, {{{0, 0}}}}, 0, 0 },
{ "$c12", 12, {0, {{{0, 0}}}}, 0, 0 },
{ "$c13", 13, {0, {{{0, 0}}}}, 0, 0 },
{ "$c14", 14, {0, {{{0, 0}}}}, 0, 0 },
{ "$c15", 15, {0, {{{0, 0}}}}, 0, 0 },
{ "$c16", 16, {0, {{{0, 0}}}}, 0, 0 },
{ "$c17", 17, {0, {{{0, 0}}}}, 0, 0 },
{ "$c18", 18, {0, {{{0, 0}}}}, 0, 0 },
{ "$c19", 19, {0, {{{0, 0}}}}, 0, 0 },
{ "$c20", 20, {0, {{{0, 0}}}}, 0, 0 },
{ "$c21", 21, {0, {{{0, 0}}}}, 0, 0 },
{ "$c22", 22, {0, {{{0, 0}}}}, 0, 0 },
{ "$c23", 23, {0, {{{0, 0}}}}, 0, 0 },
{ "$c24", 24, {0, {{{0, 0}}}}, 0, 0 },
{ "$c25", 25, {0, {{{0, 0}}}}, 0, 0 },
{ "$c26", 26, {0, {{{0, 0}}}}, 0, 0 },
{ "$c27", 27, {0, {{{0, 0}}}}, 0, 0 },
{ "$c28", 28, {0, {{{0, 0}}}}, 0, 0 },
{ "$c29", 29, {0, {{{0, 0}}}}, 0, 0 },
{ "$c30", 30, {0, {{{0, 0}}}}, 0, 0 },
{ "$c31", 31, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD mep_cgen_opval_h_cr =
{
& mep_cgen_opval_h_cr_entries[0],
32,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_entries[] =
{
{ "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr32", 32, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr33", 33, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr34", 34, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr35", 35, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr36", 36, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr37", 37, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr38", 38, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr39", 39, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr40", 40, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr41", 41, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr42", 42, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr43", 43, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr44", 44, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr45", 45, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr46", 46, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr47", 47, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr48", 48, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr49", 49, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr50", 50, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr51", 51, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr52", 52, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr53", 53, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr54", 54, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr55", 55, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr56", 56, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr57", 57, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr58", 58, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr59", 59, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr60", 60, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr61", 61, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr62", 62, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr63", 63, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD mep_cgen_opval_h_ccr =
{
& mep_cgen_opval_h_ccr_entries[0],
64,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_cr_ivc2_entries[] =
{
{ "$c0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "$c1", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "$c2", 2, {0, {{{0, 0}}}}, 0, 0 },
{ "$c3", 3, {0, {{{0, 0}}}}, 0, 0 },
{ "$c4", 4, {0, {{{0, 0}}}}, 0, 0 },
{ "$c5", 5, {0, {{{0, 0}}}}, 0, 0 },
{ "$c6", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "$c7", 7, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD mep_cgen_opval_h_cr_ivc2 =
{
& mep_cgen_opval_h_cr_ivc2_entries[0],
8,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY mep_cgen_opval_h_ccr_ivc2_entries[] =
{
{ "$csar0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "$cc", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "$cofr0", 4, {0, {{{0, 0}}}}, 0, 0 },
{ "$cofr1", 5, {0, {{{0, 0}}}}, 0, 0 },
{ "$cofa0", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "$cofa1", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "$csar1", 15, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc0_0", 16, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc0_1", 17, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc0_2", 18, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc0_3", 19, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc0_4", 20, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc0_5", 21, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc0_6", 22, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc0_7", 23, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc1_0", 24, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc1_1", 25, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc1_2", 26, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc1_3", 27, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc1_4", 28, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc1_5", 29, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc1_6", 30, {0, {{{0, 0}}}}, 0, 0 },
{ "$acc1_7", 31, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr0", 0, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr1", 1, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr2", 2, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr3", 3, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr4", 4, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr5", 5, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr6", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr7", 7, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr8", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr9", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr10", 10, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr11", 11, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr12", 12, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr13", 13, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr14", 14, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr15", 15, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr16", 16, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr17", 17, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr18", 18, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr19", 19, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr20", 20, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr21", 21, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr22", 22, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr23", 23, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr24", 24, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr25", 25, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr26", 26, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr27", 27, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr28", 28, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr29", 29, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr30", 30, {0, {{{0, 0}}}}, 0, 0 },
{ "$ccr31", 31, {0, {{{0, 0}}}}, 0, 0 }
};
CGEN_KEYWORD mep_cgen_opval_h_ccr_ivc2 =
{
& mep_cgen_opval_h_ccr_ivc2_entries[0],
55,
0, 0, 0, 0, ""
};
/* The hardware table. */
#define A(a) (1 << CGEN_HW_##a)
const CGEN_HW_ENTRY mep_cgen_hw_table[] =
{
{ "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr64", HW_H_CR64, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr64, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr64-w", HW_H_CR64_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-ccr", HW_H_CCR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-ccr-w", HW_H_CCR_W, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ "h-cr-ivc2", HW_H_CR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ "h-ccr-ivc2", HW_H_CCR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_ivc2, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
};
#undef A
/* The instruction field table. */
#define A(a) (1 << CGEN_IFLD_##a)
const CGEN_IFLD mep_cgen_ifld_table[] =
{
{ MEP_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_MAJOR, "f-major", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_RN, "f-rn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_RN3, "f-rn3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_RM, "f-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_RL, "f-rl", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_SUB2, "f-sub2", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_SUB3, "f-sub3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_SUB4, "f-sub4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_EXT, "f-ext", 0, 32, 16, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_EXT4, "f-ext4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_EXT62, "f-ext62", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CRN, "f-crn", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CSRN_HI, "f-csrn-hi", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CSRN_LO, "f-csrn-lo", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CRNX_HI, "f-crnx-hi", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CRNX_LO, "f-crnx-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CRNX, "f-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_0, "f-0", 0, 32, 0, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_1, "f-1", 0, 32, 1, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_2, "f-2", 0, 32, 2, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_3, "f-3", 0, 32, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_4, "f-4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_6, "f-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_7, "f-7", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_8, "f-8", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_9, "f-9", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_11, "f-11", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_12, "f-12", 0, 32, 12, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_13, "f-13", 0, 32, 13, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_14, "f-14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_15, "f-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_16, "f-16", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_17, "f-17", 0, 32, 17, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_18, "f-18", 0, 32, 18, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_19, "f-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_20, "f-20", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_21, "f-21", 0, 32, 21, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_22, "f-22", 0, 32, 22, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_23, "f-23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_24, "f-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_26, "f-26", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_27, "f-27", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_28, "f-28", 0, 32, 28, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_29, "f-29", 0, 32, 29, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_30, "f-30", 0, 32, 30, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_31, "f-31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_8S8A2, "f-8s8a2", 0, 32, 8, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_12S4A2, "f-12s4a2", 0, 32, 4, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_17S16A2, "f-17s16a2", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24S5A2N_HI, "f-24s5a2n-hi", 0, 32, 16, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24S5A2N_LO, "f-24s5a2n-lo", 0, 32, 5, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24S5A2N, "f-24s5a2n", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U5A2N_HI, "f-24u5a2n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U5A2N_LO, "f-24u5a2n-lo", 0, 32, 5, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U5A2N, "f-24u5a2n", 0, 0, 0, 0,{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_2U6, "f-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_7U9, "f-7u9", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_7U9A2, "f-7u9a2", 0, 32, 9, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_7U9A4, "f-7u9a4", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_16S16, "f-16s16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_2U10, "f-2u10", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_3U5, "f-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_4U8, "f-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_5U8, "f-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_5U24, "f-5u24", 0, 32, 24, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_6S8, "f-6s8", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_8S8, "f-8s8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_16U16, "f-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_12U16, "f-12u16", 0, 32, 16, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_3U29, "f-3u29", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CDISP10, "f-cdisp10", 0, 32, 22, 10, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U8A4N_HI, "f-24u8a4n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U8A4N_LO, "f-24u8a4n-lo", 0, 32, 8, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U8A4N, "f-24u8a4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U8N_HI, "f-24u8n-hi", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U8N_LO, "f-24u8n-lo", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U8N, "f-24u8n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U4N_HI, "f-24u4n-hi", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U4N_LO, "f-24u4n-lo", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_24U4N, "f-24u4n", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CALLNUM, "f-callnum", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CCRN_HI, "f-ccrn-hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CCRN_LO, "f-ccrn-lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_CCRN, "f-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_C5N4, "f-c5n4", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_C5N5, "f-c5n5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_C5N6, "f-c5n6", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_C5N7, "f-c5n7", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_RL5, "f-rl5", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_12S20, "f-12s20", 0, 32, 20, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } } } },
{ MEP_F_C5_RNM, "f-c5-rnm", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_C5_RM, "f-c5-rm", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_C5_16U16, "f-c5-16u16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_C5_RMUIMM20, "f-c5-rmuimm20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_C5_RNMUIMM24, "f-c5-rnmuimm24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_2U4, "f-ivc2-2u4", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_3U4, "f-ivc2-3u4", 0, 32, 4, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_8U4, "f-ivc2-8u4", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_8S4, "f-ivc2-8s4", 0, 32, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_1U6, "f-ivc2-1u6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_2U6, "f-ivc2-2u6", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_3U6, "f-ivc2-3u6", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_6U6, "f-ivc2-6u6", 0, 32, 6, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U7, "f-ivc2-5u7", 0, 32, 7, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_4U8, "f-ivc2-4u8", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_3U9, "f-ivc2-3u9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U16, "f-ivc2-5u16", 0, 32, 16, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U21, "f-ivc2-5u21", 0, 32, 21, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U26, "f-ivc2-5u26", 0, 32, 26, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_1U31, "f-ivc2-1u31", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_4U16, "f-ivc2-4u16", 0, 32, 16, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_4U20, "f-ivc2-4u20", 0, 32, 20, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_4U24, "f-ivc2-4u24", 0, 32, 24, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_4U28, "f-ivc2-4u28", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_2U0, "f-ivc2-2u0", 0, 32, 0, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_3U0, "f-ivc2-3u0", 0, 32, 0, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_4U0, "f-ivc2-4u0", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U0, "f-ivc2-5u0", 0, 32, 0, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_8U0, "f-ivc2-8u0", 0, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_8S0, "f-ivc2-8s0", 0, 32, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_6U2, "f-ivc2-6u2", 0, 32, 2, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U3, "f-ivc2-5u3", 0, 32, 3, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_4U4, "f-ivc2-4u4", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_3U5, "f-ivc2-3u5", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U8, "f-ivc2-5u8", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_4U10, "f-ivc2-4u10", 0, 32, 10, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_3U12, "f-ivc2-3u12", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U13, "f-ivc2-5u13", 0, 32, 13, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_2U18, "f-ivc2-2u18", 0, 32, 18, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U18, "f-ivc2-5u18", 0, 32, 18, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_8U20, "f-ivc2-8u20", 0, 32, 20, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_8S20, "f-ivc2-8s20", 0, 32, 20, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_5U23, "f-ivc2-5u23", 0, 32, 23, 5, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_2U23, "f-ivc2-2u23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_3U25, "f-ivc2-3u25", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_IMM16P0, "f-ivc2-imm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_SIMM16P0, "f-ivc2-simm16p0", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CCRN_C3HI, "f-ivc2-ccrn-c3hi", 0, 32, 28, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CCRN_C3LO, "f-ivc2-ccrn-c3lo", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CRN, "f-ivc2-crn", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CRM, "f-ivc2-crm", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CCRN_H1, "f-ivc2-ccrn-h1", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CCRN_H2, "f-ivc2-ccrn-h2", 0, 32, 20, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CCRN_LO, "f-ivc2-ccrn-lo", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CMOV1, "f-ivc2-cmov1", 0, 32, 8, 12, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CMOV2, "f-ivc2-cmov2", 0, 32, 22, 6, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CMOV3, "f-ivc2-cmov3", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CCRN_C3, "f-ivc2-ccrn-c3", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CCRN, "f-ivc2-ccrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ MEP_F_IVC2_CRNX, "f-ivc2-crnx", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
{ 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
};
#undef A
/* multi ifield declarations */
const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_C3_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [];
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [];
/* multi ifield definitions */
const CGEN_MAYBE_MULTI_IFLD MEP_F_CSRN_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CSRN_LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_CRNX_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRNX_LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24S5A2N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24S5A2N_LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U5A2N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U5A2N_LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8A4N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8A4N_LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U8N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U8N_LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_24U4N_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_24U4N_LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_CALLNUM_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_11] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_CCRN_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CCRN_LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RMUIMM20_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RM] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_C5_RNMUIMM24_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_RNM] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_C5_16U16] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_IMM16P0_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_SIMM16P0_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U0] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_8U20] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_C3_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3HI] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_C3LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CCRN_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H2] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
{ 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD MEP_F_IVC2_CRNX_MULTI_IFIELD [] =
{
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_H1] } },
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_CCRN_LO] } },
{ 0, { (const PTR) 0 } }
};
/* The operand table. */
#define A(a) (1 << CGEN_OPERAND_##a)
#define OPERAND(op) MEP_OPERAND_##op
const CGEN_OPERAND mep_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* r0: register 0 */
{ "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn: register Rn */
{ "rn", MEP_OPERAND_RN, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rm: register Rm */
{ "rm", MEP_OPERAND_RM, HW_H_GPR, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rl: register Rl */
{ "rl", MEP_OPERAND_RL, HW_H_GPR, 12, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RL] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3: register 0-7 */
{ "rn3", MEP_OPERAND_RN3, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rma: register Rm holding pointer */
{ "rma", MEP_OPERAND_RMA, HW_H_GPR, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_POINTER, 0 } }, { { 1, 0 } } } } },
/* rnc: register Rn holding char */
{ "rnc", MEP_OPERAND_RNC, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnuc: register Rn holding unsigned char */
{ "rnuc", MEP_OPERAND_RNUC, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rns: register Rn holding short */
{ "rns", MEP_OPERAND_RNS, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnus: register Rn holding unsigned short */
{ "rnus", MEP_OPERAND_RNUS, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnl: register Rn holding long */
{ "rnl", MEP_OPERAND_RNL, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rnul: register Rn holding unsigned long */
{ "rnul", MEP_OPERAND_RNUL, HW_H_GPR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
/* rn3c: register 0-7 holding unsigned char */
{ "rn3c", MEP_OPERAND_RN3C, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3uc: register 0-7 holding byte */
{ "rn3uc", MEP_OPERAND_RN3UC, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3s: register 0-7 holding unsigned short */
{ "rn3s", MEP_OPERAND_RN3S, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3us: register 0-7 holding short */
{ "rn3us", MEP_OPERAND_RN3US, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3l: register 0-7 holding unsigned long */
{ "rn3l", MEP_OPERAND_RN3L, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* rn3ul: register 0-7 holding long */
{ "rn3ul", MEP_OPERAND_RN3UL, HW_H_GPR, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN3] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_ULONG, 0 } }, { { 1, 0 } } } } },
/* lp: link pointer */
{ "lp", MEP_OPERAND_LP, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* sar: shift amount register */
{ "sar", MEP_OPERAND_SAR, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* hi: high result */
{ "hi", MEP_OPERAND_HI, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* lo: low result */
{ "lo", MEP_OPERAND_LO, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* mb0: modulo begin register 0 */
{ "mb0", MEP_OPERAND_MB0, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* me0: modulo end register 0 */
{ "me0", MEP_OPERAND_ME0, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* mb1: modulo begin register 1 */
{ "mb1", MEP_OPERAND_MB1, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* me1: modulo end register 1 */
{ "me1", MEP_OPERAND_ME1, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* psw: program status word */
{ "psw", MEP_OPERAND_PSW, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* epc: exception prog counter */
{ "epc", MEP_OPERAND_EPC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* exc: exception cause */
{ "exc", MEP_OPERAND_EXC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* npc: nmi program counter */
{ "npc", MEP_OPERAND_NPC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* dbg: debug register */
{ "dbg", MEP_OPERAND_DBG, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* depc: debug exception pc */
{ "depc", MEP_OPERAND_DEPC, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* opt: option register */
{ "opt", MEP_OPERAND_OPT, HW_H_CSR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* r1: register 1 */
{ "r1", MEP_OPERAND_R1, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* tp: tiny data area pointer */
{ "tp", MEP_OPERAND_TP, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* sp: stack pointer */
{ "sp", MEP_OPERAND_SP, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* tpr: comment */
{ "tpr", MEP_OPERAND_TPR, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* spr: comment */
{ "spr", MEP_OPERAND_SPR, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* csrn: control/special register */
{ "csrn", MEP_OPERAND_CSRN, HW_H_CSR, 8, 5,
{ 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* csrn-idx: control/special reg idx */
{ "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
{ 2, { (const PTR) &MEP_F_CSRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* crn64: copro Rn (64-bit) */
{ "crn64", MEP_OPERAND_CRN64, HW_H_CR64, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crn: copro Rn (32-bit) */
{ "crn", MEP_OPERAND_CRN, HW_H_CR, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CRN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crnx64: copro Rn (0-31, 64-bit) */
{ "crnx64", MEP_OPERAND_CRNX64, HW_H_CR64, 4, 5,
{ 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crnx: copro Rn (0-31, 32-bit) */
{ "crnx", MEP_OPERAND_CRNX, HW_H_CR, 4, 5,
{ 2, { (const PTR) &MEP_F_CRNX_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ccrn: copro control reg CCRn */
{ "ccrn", MEP_OPERAND_CCRN, HW_H_CCR, 4, 6,
{ 2, { (const PTR) &MEP_F_CCRN_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_REGNUM, 0 } }, { { 1, 0 } } } } },
/* cccc: copro flags */
{ "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RM] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* pcrel8a2: comment */
{ "pcrel8a2", MEP_OPERAND_PCREL8A2, HW_H_SINT, 8, 7,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8A2] } },
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcrel12a2: comment */
{ "pcrel12a2", MEP_OPERAND_PCREL12A2, HW_H_SINT, 4, 11,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_12S4A2] } },
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcrel17a2: comment */
{ "pcrel17a2", MEP_OPERAND_PCREL17A2, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_17S16A2] } },
{ 0|A(RELAX)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcrel24a2: comment */
{ "pcrel24a2", MEP_OPERAND_PCREL24A2, HW_H_SINT, 5, 23,
{ 2, { (const PTR) &MEP_F_24S5A2N_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* pcabs24a2: comment */
{ "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
{ 2, { (const PTR) &MEP_F_24U5A2N_MULTI_IFIELD[0] } },
{ 0|A(ABS_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LABEL, 0 } }, { { 1, 0 } } } } },
/* sdisp16: comment */
{ "sdisp16", MEP_OPERAND_SDISP16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm16: comment */
{ "simm16", MEP_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16S16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm16: comment */
{ "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* code16: uci/dsp code (16 bits) */
{ "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_16U16] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* udisp2: SSARB addend (2 bits) */
{ "udisp2", MEP_OPERAND_UDISP2, HW_H_SINT, 6, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm2: interrupt (2 bits) */
{ "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_2U10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm6: add const (6 bits) */
{ "simm6", MEP_OPERAND_SIMM6, HW_H_SINT, 8, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_6S8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* simm8: mov const (8 bits) */
{ "simm8", MEP_OPERAND_SIMM8, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_8S8] } },
{ 0|A(RELOC_IMPLIES_OVERFLOW), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* addr24a4: comment */
{ "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
{ 2, { (const PTR) &MEP_F_24U8A4N_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
/* code24: coprocessor code */
{ "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
{ 2, { (const PTR) &MEP_F_24U4N_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* callnum: system call number */
{ "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
{ 4, { (const PTR) &MEP_F_CALLNUM_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm3: bit immediate (3 bits) */
{ "uimm3", MEP_OPERAND_UIMM3, HW_H_UINT, 5, 3,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_3U5] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm4: bCC const (4 bits) */
{ "uimm4", MEP_OPERAND_UIMM4, HW_H_UINT, 8, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_4U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* uimm5: bit/shift val (5 bits) */
{ "uimm5", MEP_OPERAND_UIMM5, HW_H_UINT, 8, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U8] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* udisp7: comment */
{ "udisp7", MEP_OPERAND_UDISP7, HW_H_UINT, 9, 7,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* udisp7a2: comment */
{ "udisp7a2", MEP_OPERAND_UDISP7A2, HW_H_UINT, 9, 6,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A2] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 2, 0 } } } } },
/* udisp7a4: comment */
{ "udisp7a4", MEP_OPERAND_UDISP7A4, HW_H_UINT, 9, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
/* uimm7a4: comment */
{ "uimm7a4", MEP_OPERAND_UIMM7A4, HW_H_UINT, 9, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_7U9A4] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 4, 0 } } } } },
/* uimm24: immediate (24 bits) */
{ "uimm24", MEP_OPERAND_UIMM24, HW_H_UINT, 8, 24,
{ 2, { (const PTR) &MEP_F_24U8N_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cimm4: cache immed'te (4 bits) */
{ "cimm4", MEP_OPERAND_CIMM4, HW_H_UINT, 4, 4,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_RN] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cimm5: clip immediate (5 bits) */
{ "cimm5", MEP_OPERAND_CIMM5, HW_H_UINT, 24, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_5U24] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10: comment */
{ "cdisp10", MEP_OPERAND_CDISP10, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10a2: comment */
{ "cdisp10a2", MEP_OPERAND_CDISP10A2, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10a4: comment */
{ "cdisp10a4", MEP_OPERAND_CDISP10A4, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* cdisp10a8: comment */
{ "cdisp10a8", MEP_OPERAND_CDISP10A8, HW_H_SINT, 22, 10,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_CDISP10] } },
{ 0, { { { (1<<MACH_BASE