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; Renesas M32C CPU description. -*- Scheme -*-
;
; Copyright 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Renesas.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
; MA 02110-1301, USA.
(include "simplify.inc")
(define-arch
(name m32c)
(comment "Renesas M32C")
(default-alignment forced)
(insn-lsb0? #f)
(machs m16c m32c)
(isas m16c m32c)
)
(define-isa
(name m16c)
(default-insn-bitsize 32)
; Number of bytes of insn we can initially fetch.
(base-insn-bitsize 32)
; Used in computing bit numbers.
(default-insn-word-bitsize 32)
(decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
; fetches 1 insn at a time.
(liw-insns 1)
; executes 1 insn at a time.
(parallel-insns 1)
)
(define-isa
(name m32c)
(default-insn-bitsize 32)
; Number of bytes of insn we can initially fetch.
(base-insn-bitsize 32)
; Used in computing bit numbers.
(default-insn-word-bitsize 32)
(decode-assist (0 1 2 3 4 5 6 7)) ; Initial bitnumbers to decode insns by.
; fetches 1 insn at a time.
(liw-insns 1)
; executes 1 insn at a time.
(parallel-insns 1)
)
(define-cpu
; cpu names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name m16cbf)
(comment "Renesas M16C base family")
(insn-endian big)
(data-endian little)
(word-bitsize 16)
)
(define-cpu
; cpu names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name m32cbf)
(comment "Renesas M32C base family")
(insn-endian big)
(data-endian little)
(word-bitsize 16)
)
(define-mach
(name m16c)
(comment "Generic M16C cpu")
(cpu m32cbf)
)
(define-mach
(name m32c)
(comment "Generic M32C cpu")
(cpu m32cbf)
)
; Model descriptions.
(define-model
(name m16c)
(comment "m16c") (attrs)
(mach m16c)
; `state' is a list of variables for recording model state
; (state)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
(define-model
(name m32c)
(comment "m32c") (attrs)
(mach m32c)
; `state' is a list of variables for recording model state
; (state)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
(define-attr
(type enum)
(name RL_TYPE)
(values NONE JUMP 1ADDR 2ADDR)
(default NONE)
)
; Macros to simplify MACH attribute specification.
(define-pmacro all-isas () (ISA m16c,m32c))
(define-pmacro m16c-isa () (ISA m16c))
(define-pmacro m32c-isa () (ISA m32c))
(define-pmacro MACH16 (MACH m16c))
(define-pmacro MACH32 (MACH m32c))
(define-pmacro (machine size)
(MACH (.sym m size c)) (ISA (.sym m size c)))
(define-pmacro RL_JUMP (RL_TYPE JUMP))
(define-pmacro RL_1ADDR (RL_TYPE 1ADDR))
(define-pmacro RL_2ADDR (RL_TYPE 2ADDR))
;=============================================================
; Fields
;-------------------------------------------------------------
; Main opcodes
;
(dnf f-0-1 "opcode" (all-isas) 0 1)
(dnf f-0-2 "opcode" (all-isas) 0 2)
(dnf f-0-3 "opcode" (all-isas) 0 3)
(dnf f-0-4 "opcode" (all-isas) 0 4)
(dnf f-1-3 "opcode" (all-isas) 1 3)
(dnf f-2-2 "opcode" (all-isas) 2 2)
(dnf f-3-4 "opcode" (all-isas) 3 4)
(dnf f-3-1 "opcode" (all-isas) 3 1)
(dnf f-4-1 "opcode" (all-isas) 4 1)
(dnf f-4-3 "opcode" (all-isas) 4 3)
(dnf f-4-4 "opcode" (all-isas) 4 4)
(dnf f-4-6 "opcode" (all-isas) 4 6)
(dnf f-5-1 "opcode" (all-isas) 5 1)
(dnf f-5-3 "opcode" (all-isas) 5 3)
(dnf f-6-2 "opcode" (all-isas) 6 2)
(dnf f-7-1 "opcode" (all-isas) 7 1)
(dnf f-8-1 "opcode" (all-isas) 8 1)
(dnf f-8-2 "opcode" (all-isas) 8 2)
(dnf f-8-3 "opcode" (all-isas) 8 3)
(dnf f-8-4 "opcode" (all-isas) 8 4)
(dnf f-8-8 "opcode" (all-isas) 8 8)
(dnf f-9-3 "opcode" (all-isas) 9 3)
(dnf f-9-1 "opcode" (all-isas) 9 1)
(dnf f-10-1 "opcode" (all-isas) 10 1)
(dnf f-10-2 "opcode" (all-isas) 10 2)
(dnf f-10-3 "opcode" (all-isas) 10 3)
(dnf f-11-1 "opcode" (all-isas) 11 1)
(dnf f-12-1 "opcode" (all-isas) 12 1)
(dnf f-12-2 "opcode" (all-isas) 12 2)
(dnf f-12-3 "opcode" (all-isas) 12 3)
(dnf f-12-4 "opcode" (all-isas) 12 4)
(dnf f-12-6 "opcode" (all-isas) 12 6)
(dnf f-13-3 "opcode" (all-isas) 13 3)
(dnf f-14-1 "opcode" (all-isas) 14 1)
(dnf f-14-2 "opcode" (all-isas) 14 2)
(dnf f-15-1 "opcode" (all-isas) 15 1)
(dnf f-16-1 "opcode" (all-isas) 16 1)
(dnf f-16-2 "opcode" (all-isas) 16 2)
(dnf f-16-4 "opcode" (all-isas) 16 4)
(dnf f-16-8 "opcode" (all-isas) 16 8)
(dnf f-18-1 "opcode" (all-isas) 18 1)
(dnf f-18-2 "opcode" (all-isas) 18 2)
(dnf f-18-3 "opcode" (all-isas) 18 3)
(dnf f-20-1 "opcode" (all-isas) 20 1)
(dnf f-20-3 "opcode" (all-isas) 20 3)
(dnf f-20-2 "opcode" (all-isas) 20 2)
(dnf f-20-4 "opcode" (all-isas) 20 4)
(dnf f-21-3 "opcode" (all-isas) 21 3)
(dnf f-24-2 "opcode" (all-isas) 24 2)
(dnf f-24-8 "opcode" (all-isas) 24 8)
(dnf f-32-16 "opcode" (all-isas) 32 16)
;-------------------------------------------------------------
; Registers
;-------------------------------------------------------------
(dnf f-src16-rn "source Rn for m16c" (MACH16 m16c-isa) 10 2)
(dnf f-src16-an "source An for m16c" (MACH16 m16c-isa) 11 1)
(dnf f-src32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 11 1)
(dnf f-src32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 19 1)
; QI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0l 00'b 10'b
; r0h 01'b 00'b
; r1l 10'b 11'b
; r1h 11'b 01'b
(df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT
((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
; QI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0l 00'b 10'b
; r0h 01'b 00'b
; r1l 10'b 11'b
; r1h 11'b 01'b
(df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT
((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
; HI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0 00'b 10'b
; r1 01'b 11'b
; r2 10'b 00'b
; r3 11'b 01'b
(df f-src32-rn-unprefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 10 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
; HI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0 00'b 10'b
; r1 01'b 11'b
; r2 10'b 00'b
; r3 11'b 01'b
(df f-src32-rn-prefixed-HI "source Rn HI for m32c" (MACH32 m32c-isa) 18 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
; SI mode gr encoding for m32c is as follows:
; register encoding index
; -------------------------
; r2r0 10'b 0
; r3r1 11'b 1
(df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(dnf f-dst32-rn-ext-unprefixed "destination Rn for m32c" (MACH32 m32c-isa) 9 1)
(dnf f-dst16-rn "destination Rn for m16c" (MACH16 m16c-isa) 14 2)
(dnf f-dst16-rn-ext "destination Rn for m16c" (MACH16 m16c-isa) 14 1)
(dnf f-dst16-rn-QI-s "destination Rn for m16c" (MACH16 m16c-isa) 5 1)
(dnf f-dst16-an "destination An for m16c" (MACH16 m16c-isa) 15 1)
(dnf f-dst16-an-s "destination An for m16c" (MACH16 m16c-isa) 4 1)
(dnf f-dst32-an-unprefixed "destination An for m32c" (MACH32 m32c-isa) 9 1)
(dnf f-dst32-an-prefixed "destination An for m32c" (MACH32 m32c-isa) 17 1)
; QI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0l 00'b 10'b
; r0h 01'b 00'b
; r1l 10'b 11'b
; r1h 11'b 01'b
(df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT
((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
(df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT
((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert
((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract
)
; HI mode gr encoding for m32c is different than for m16c. The hardware
; is indexed using the m16c encoding, so perform the transformation here.
; register m16c m32c
; ----------------------
; r0 00'b 10'b
; r1 01'b 11'b
; r2 10'b 00'b
; r3 11'b 01'b
(df f-dst32-rn-unprefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 8 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
(df f-dst32-rn-prefixed-HI "destination Rn HI for m32c" (MACH32 m32c-isa) 16 2 UINT
((value pc) (mod USI (add value 2) 4)) ; insert
((value pc) (mod USI (add value 2) 4)) ; extract
)
; SI mode gr encoding for m32c is as follows:
; register encoding index
; -------------------------
; r2r0 10'b 0
; r3r1 11'b 1
(df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT
((value pc) (add USI value 2)) ; insert
((value pc) (sub USI value 2)) ; extract
)
(dnf f-dst16-1-S "destination R0[hl] for m16c" (MACH16 m16c-isa) 5 1)
;-------------------------------------------------------------
; Immediates embedded in the base insn
;-------------------------------------------------------------
(df f-imm-8-s4 "4 bit signed" (all-isas) 8 4 INT #f #f)
(df f-imm-12-s4 "4 bit signed" (all-isas) 12 4 INT #f #f)
(df f-imm-13-u3 "3 bit unsigned" (all-isas) 13 3 UINT #f #f)
(df f-imm-20-s4 "4 bit signed" (all-isas) 20 4 INT #f #f)
(df f-imm1-S "1 bit immediate for short format binary insns" (MACH32 m32c-isa) 2 1 UINT
((value pc) (sub USI value 1)) ; insert
((value pc) (add USI value 1)) ; extract
)
(dnmf f-imm3-S "3 bit unsigned for short format insns" (all-isas) UINT
(f-2-2 f-7-1)
(sequence () ; insert
(set (ifield f-7-1) (and (sub (ifield f-imm3-S) 1) 1))
(set (ifield f-2-2) (and (srl (sub (ifield f-imm3-S) 1) 1) #x3))
)
(sequence () ; extract
(set (ifield f-imm3-S) (add (or (sll (ifield f-2-2) 1)
(ifield f-7-1))
1))
)
)
;-------------------------------------------------------------
; Immediates and displacements beyond the base insn
;-------------------------------------------------------------
(df f-dsp-8-u6 "6 bit unsigned" (all-isas) 8 6 UINT #f #f)
(df f-dsp-8-u8 "8 bit unsigned" (all-isas) 8 8 UINT #f #f)
(df f-dsp-8-s8 "8 bit signed" (all-isas) 8 8 INT #f #f)
(df f-dsp-10-u6 "6 bit unsigned" (all-isas) 10 6 UINT #f #f)
(df f-dsp-16-u8 "8 bit unsigned" (all-isas) 16 8 UINT #f #f)
(df f-dsp-16-s8 "8 bit signed" (all-isas) 16 8 INT #f #f)
(df f-dsp-24-u8 "8 bit unsigned" (all-isas) 24 8 UINT #f #f)
(df f-dsp-24-s8 "8 bit signed" (all-isas) 24 8 INT #f #f)
(df f-dsp-32-u8 "8 bit unsigned" (all-isas) 32 8 UINT #f #f)
(df f-dsp-32-s8 "8 bit signed" (all-isas) 32 8 INT #f #f)
(df f-dsp-40-u8 "8 bit unsigned" (all-isas) 40 8 UINT #f #f)
(df f-dsp-40-s8 "8 bit signed" (all-isas) 40 8 INT #f #f)
(df f-dsp-48-u8 "8 bit unsigned" (all-isas) 48 8 UINT #f #f)
(df f-dsp-48-s8 "8 bit signed" (all-isas) 48 8 INT #f #f)
(df f-dsp-56-u8 "8 bit unsigned" (all-isas) 56 8 UINT #f #f)
(df f-dsp-56-s8 "8 bit signed" (all-isas) 56 8 INT #f #f)
(df f-dsp-64-u8 "8 bit unsigned" (all-isas) 64 8 UINT #f #f)
(df f-dsp-64-s8 "8 bit signed" (all-isas) 64 8 INT #f #f)
; Insn opcode endianness is big, but the immediate fields are stored
; in little endian. Handle this here at the field level for all immediate
; fields longer that 1 byte.
;
; CGEN can't handle a field which spans a 32 bit word boundary, so
; handle those as multi ifields.
;
; Take care in expressions using 'srl' or 'sll' as part of some larger
; expression meant to yield sign-extended values. CGEN translates
; uses of those operators into C expressions whose type is 'unsigned
; int', which tends to make the whole expression 'unsigned int'.
; Expressions like (set (ifield foo) X), however, just take X and
; store it in some member of 'struct cgen_fields', all of whose
; members are 'long'. On machines where 'long' is larger than
; 'unsigned int', assigning a "sign-extended" unsigned int to a long
; just produces a very large positive value. insert_normal will
; range-check the field's value and produce odd error messages like
; this:
;
; Error: operand out of range (4160684031 not between -2147483648 and 2147483647) `add.l #-265,-270[fb]'
;
; Annoyingly, the code will work fine on machines where 'long' and
; 'unsigned int' are the same size: the assignment will produce a
; negative number.
;
; Just tell yourself over and over: overflow detection is expensive,
; and you're glad C doesn't do it, because it never happens in real
; life.
(df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT
(f-dsp-24-u8 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u16) #xff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-24-u16) 8) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-24-u16) (or (sll (ifield f-dsp-32-u8) 8)
(ifield f-dsp-24-u8)))
)
)
(dnmf f-dsp-24-s16 "16 bit signed" (all-isas) INT
(f-dsp-24-u8 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-dsp-24-u8)
(and (ifield f-dsp-24-s16) #xff))
(set (ifield f-dsp-32-u8)
(and (srl (ifield f-dsp-24-s16) 8) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-24-s16)
(ext INT
(trunc HI (or (sll (ifield f-dsp-32-u8) 8)
(ifield f-dsp-24-u8)))))
)
)
(df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
(df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT
((value pc) (or UHI
(and (srl value 8) #x00ff)
(and (sll value 8) #xff00))) ; insert
((value pc) (or UHI
(and UHI (srl UHI value 8) #x00ff)
(and UHI (sll UHI value 8) #xff00))) ; extract
)
(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT
((value pc) (or SI
(or (and (srl value 16) #xff) (and value #xff00))
(sll (ext INT (trunc QI (and value #xff))) 16)))
((value pc) (or SI
(or (and (srl value 16) #xff) (and value #xff00))
(sll (ext INT (trunc QI (and value #xff))) 16)))
)
(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
)
(dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-16-u16 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-u24) #xffff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-dsp-16-u24) 16) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-16-u24) (or (sll (ifield f-dsp-32-u8) 16)
(ifield f-dsp-16-u16)))
)
)
(dnmf f-dsp-24-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-24-u8 f-dsp-32-u16)
(sequence () ; insert
(set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-u24) #xff))
(set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-24-u24) 8) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-24-u24) (or (sll (ifield f-dsp-32-u16) 8)
(ifield f-dsp-24-u8)))
)
)
(df f-dsp-32-u24 "24 bit unsigned" (all-isas) 32 24 UINT
((value pc) (or USI
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
(and (sll value 16) #xff0000))) ; insert
((value pc) (or USI
(or USI
(and USI (srl value 16) #x0000ff)
(and USI value #x00ff00))
(and USI (sll value 16) #xff0000))) ; extract
)
(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT
((value pc) (or USI
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
(and (sll value 16) #x0f0000))) ; insert
((value pc) (or USI
(or USI
(and USI (srl value 16) #x0000ff)
(and USI value #x00ff00))
(and USI (sll value 16) #x0f0000))) ; extract
)
(df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT
((value pc) (or USI
(or USI
(and (srl value 16) #x0000ff)
(and value #x00ff00))
(and (sll value 16) #xff0000))) ; insert
((value pc) (or USI
(or USI
(and USI (srl value 16) #x0000ff)
(and USI value #x00ff00))
(and USI (sll value 16) #xff0000))) ; extract
)
(dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT
(f-dsp-40-u24 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-40-s32) 24) #xff))
(set (ifield f-dsp-40-u24) (and (ifield f-dsp-40-s32) #xffffff))
)
(sequence () ; extract
(set (ifield f-dsp-40-s32) (or (and (ifield f-dsp-40-u24) #xffffff)
(and (sll (ifield f-dsp-64-u8) 24) #xff000000)))
)
)
(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT
(f-dsp-48-u16 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff)
(and (sll (ifield f-dsp-64-u8) 16) #x0f0000)))
)
)
(dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT
(f-dsp-48-u16 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u24) 16) #xff))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u24) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-u24) (or (and (ifield f-dsp-48-u16) #xffff)
(and (sll (ifield f-dsp-64-u8) 16) #xff0000)))
)
)
(dnmf f-dsp-16-s32 "32 bit signed" (all-isas) INT
(f-dsp-16-u16 f-dsp-32-u16)
(sequence () ; insert
(set (ifield f-dsp-32-u16) (and (srl (ifield f-dsp-16-s32) 16) #xffff))
(set (ifield f-dsp-16-u16) (and (ifield f-dsp-16-s32) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-16-s32) (or (and (ifield f-dsp-16-u16) #xffff)
(and (sll (ifield f-dsp-32-u16) 16) #xffff0000)))
)
)
(dnmf f-dsp-24-s32 "32 bit signed" (all-isas) INT
(f-dsp-24-u8 f-dsp-32-u24)
(sequence () ; insert
(set (ifield f-dsp-32-u24) (and (srl (ifield f-dsp-24-s32) 8) #xffffff))
(set (ifield f-dsp-24-u8) (and (ifield f-dsp-24-s32) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-24-s32) (or (and (ifield f-dsp-24-u8) #xff)
(and (sll (ifield f-dsp-32-u24) 8) #xffffff00)))
)
)
(df f-dsp-32-s32 "32 bit signed" (all-isas) 32 32 INT
((value pc)
;; insert
(ext INT
(or SI
(or SI
(and (srl value 24) #x000000ff)
(and (srl value 8) #x0000ff00))
(or SI
(and (sll value 8) #x00ff0000)
(and (sll value 24) #xff000000)))))
;; extract
((value pc)
(ext INT
(or SI
(or SI
(and (srl value 24) #x000000ff)
(and (srl value 8) #x0000ff00))
(or SI
(and (sll value 8) #x00ff0000)
(and (sll value 24) #xff000000)))))
)
(dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT
(f-dsp-48-u16 f-dsp-64-u16)
(sequence () ; insert
(set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-u32) 16) #xffff))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u32) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff)
(and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
)
)
(dnmf f-dsp-48-s32 "32 bit signed" (all-isas) INT
(f-dsp-48-u16 f-dsp-64-u16)
(sequence () ; insert
(set (ifield f-dsp-64-u16) (and (srl (ifield f-dsp-48-s32) 16) #xffff))
(set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-s32) #xffff))
)
(sequence () ; extract
(set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff)
(and (sll (ifield f-dsp-64-u16) 16) #xffff0000)))
)
)
(dnmf f-dsp-56-s16 "16 bit signed" (all-isas) INT
(f-dsp-56-u8 f-dsp-64-u8)
(sequence () ; insert
(set (ifield f-dsp-56-u8)
(and (ifield f-dsp-56-s16) #xff))
(set (ifield f-dsp-64-u8)
(and (srl (ifield f-dsp-56-s16) 8) #xff))
)
(sequence () ; extract
(set (ifield f-dsp-56-s16)
(ext INT
(trunc HI (or (sll (ifield f-dsp-64-u8) 8)
(ifield f-dsp-56-u8)))))
)
)
(df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; insert
((value pc) (ext INT
(trunc HI
(or (and (srl value 8) #x00ff)
(and (sll value 8) #xff00))))) ; extract
)
;-------------------------------------------------------------
; Bit indices
;-------------------------------------------------------------
(dnf f-bitno16-S "bit index for m16c" (all-isas) 5 3)
(dnf f-bitno32-prefixed "bit index for m32c" (all-isas) 21 3)
(dnf f-bitno32-unprefixed "bit index for m32c" (all-isas) 13 3)
(dnmf f-bitbase16-u11-S "unsigned bit,base:11" (all-isas) UINT
(f-bitno16-S f-dsp-8-u8)
(sequence () ; insert
(set (ifield f-bitno16-S) (and f-bitbase16-u11-S #x7))
(set (ifield f-dsp-8-u8) (and (srl (ifield f-bitbase16-u11-S) 3) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase16-u11-S) (or (sll (ifield f-dsp-8-u8) 3)
(ifield f-bitno16-S)))
)
)
(dnmf f-bitbase32-16-u11-unprefixed "unsigned bit,base:11" (all-isas) UINT
(f-bitno32-unprefixed f-dsp-16-u8)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u11-unprefixed #x7))
(set (ifield f-dsp-16-u8) (and (srl (ifield f-bitbase32-16-u11-unprefixed) 3) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-u11-unprefixed) (or (sll (ifield f-dsp-16-u8) 3)
(ifield f-bitno32-unprefixed)))
)
)
(dnmf f-bitbase32-16-s11-unprefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-unprefixed f-dsp-16-s8)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s11-unprefixed #x7))
(set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3)
(ifield f-bitno32-unprefixed)))
)
)
(dnmf f-bitbase32-16-u19-unprefixed "unsigned bit,base:19" (all-isas) UINT
(f-bitno32-unprefixed f-dsp-16-u16)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u19-unprefixed #x7))
(set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u19-unprefixed) 3) #xffff))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-u19-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
(ifield f-bitno32-unprefixed)))
)
)
(dnmf f-bitbase32-16-s19-unprefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-unprefixed f-dsp-16-s16)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-s19-unprefixed #x7))
(set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3)
(ifield f-bitno32-unprefixed)))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-16-u27-unprefixed "unsigned bit,base:27" (all-isas) UINT
(f-bitno32-unprefixed f-dsp-16-u16 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-bitno32-unprefixed) (and f-bitbase32-16-u27-unprefixed #x7))
(set (ifield f-dsp-16-u16) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 3) #xffff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-16-u27-unprefixed) 19) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-16-u27-unprefixed) (or (sll (ifield f-dsp-16-u16) 3)
(or (sll (ifield f-dsp-32-u8) 19)
(ifield f-bitno32-unprefixed))))
)
)
(dnmf f-bitbase32-24-u11-prefixed "unsigned bit,base:11" (all-isas) UINT
(f-bitno32-prefixed f-dsp-24-u8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u11-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u11-prefixed) 3) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-u11-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(ifield f-bitno32-prefixed)))
)
)
(dnmf f-bitbase32-24-s11-prefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-prefixed f-dsp-24-s8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s11-prefixed #x7))
(set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3)
(ifield f-bitno32-prefixed)))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-24-u19-prefixed "unsigned bit,base:19" (all-isas) UINT
(f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u19-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 3) #xff))
(set (ifield f-dsp-32-u8) (and (srl (ifield f-bitbase32-24-u19-prefixed) 11) #xff))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-u19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(or (sll (ifield f-dsp-32-u8) 11)
(ifield f-bitno32-prefixed))))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-24-s19-prefixed "signed bit,base:11" (all-isas) INT
(f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-s8)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-s19-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-s19-prefixed) 3) #xff))
(set (ifield f-dsp-32-s8) (sra INT (ifield f-bitbase32-24-s19-prefixed) 11))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(or (sll (ifield f-dsp-32-s8) 11)
(ifield f-bitno32-prefixed))))
)
)
; SID decoder doesn't handle multi-ifield referencing another multi-ifield :-(
(dnmf f-bitbase32-24-u27-prefixed "unsigned bit,base:27" (all-isas) UINT
(f-bitno32-prefixed f-dsp-24-u8 f-dsp-32-u16)
(sequence () ; insert
(set (ifield f-bitno32-prefixed) (and f-bitbase32-24-u27-prefixed #x7))
(set (ifield f-dsp-24-u8) (and (srl (ifield f-bitbase32-24-u27-prefixed) 3) #xff))
(set (ifield f-dsp-32-u16) (and (srl (ifield f-bitbase32-24-u27-prefixed) 11) #xffff))
)
(sequence () ; extract
(set (ifield f-bitbase32-24-u27-prefixed) (or (sll (ifield f-dsp-24-u8) 3)
(or (sll (ifield f-dsp-32-u16) 11)
(ifield f-bitno32-prefixed))))
)
)
;-------------------------------------------------------------
; Labels
;-------------------------------------------------------------
(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT
(f-2-2 f-7-1)
(sequence ((SI val)) ; insert
(set val (sub (sub (ifield f-lab32-jmp-s) pc) 2))
(set (ifield f-7-1) (and val #x1))
(set (ifield f-2-2) (srl val 1))
)
(sequence () ; extract
(set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1)
(ifield f-7-1))
2)))
)
)
(df f-lab-8-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 8 8 INT
((value pc) (sub SI value (add SI pc 1))) ; insert
((value pc) (add SI value (add SI pc 1))) ; extract
)
(df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT
((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8)
(srl (and (sub value (add pc 1)) #xffff) 8)))
((value pc) (add SI (or (srl (and value #xffff) 8)
(sra (sll (and value #xff) 24) 16)) (add pc 1)))
)
(df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
((value pc) (or SI
(or (srl value 16) (and value #xff00))
(sll (and value #xff) 16)))
)
(df f-lab-16-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 16 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(df f-lab-24-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 24 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(df f-lab-32-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 32 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
(df f-lab-40-8 "8 bit pc relative signed offset" (PCREL-ADDR all-isas) 40 8 INT
((value pc) (sub SI value (add SI pc 2))) ; insert
((value pc) (add SI value (add SI pc 2))) ; extract
)
;-------------------------------------------------------------
; Condition codes
;-------------------------------------------------------------
(dnf f-cond16 "condition code" (all-isas) 12 4)
(dnf f-cond16j-5 "condition code" (all-isas) 5 3)
(dnmf f-cond32 "condition code" (all-isas) UINT
(f-9-1 f-13-3)
(sequence () ; insert
(set (ifield f-9-1) (and (srl (ifield f-cond32) 3) 1))
(set (ifield f-13-3) (and (ifield f-cond32) #x7))
)
(sequence () ; extract
(set (ifield f-cond32) (or (sll (ifield f-9-1) 3)
(ifield f-13-3)))
)
)
(dnmf f-cond32j "condition code" (all-isas) UINT
(f-1-3 f-7-1)
(sequence () ; insert
(set (ifield f-1-3) (and (srl (ifield f-cond32j) 1) #x7))
(set (ifield f-7-1) (and (ifield f-cond32j) #x1))
)
(sequence () ; extract
(set (ifield f-cond32j) (or (sll (ifield f-1-3) 1)
(ifield f-7-1)))
)
)
;=============================================================
; Hardware
;
(dnh h-pc "program counter" (PC all-isas) (pc USI) () () ())
;-------------------------------------------------------------
; General registers
; The actual registers are 16 bits
;-------------------------------------------------------------
(define-hardware
(name h-gr)
(comment "general 16 bit registers")
(attrs all-isas CACHE-ADDR)
(type register HI (4))
(indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3))))
; Define different views of the grs as VIRTUAL with getter/setter specs
;
(define-hardware
(name h-gr-QI)
(comment "general 8 bit registers")
(attrs all-isas VIRTUAL)
(type register QI (4))
(indices keyword "" (("r0l" 0) ("r0h" 1) ("r1l" 2) ("r1h" 3)))
(get (index) (and (if SI (mod index 2)
(srl (reg h-gr (div index 2)) 8)
(reg h-gr (div index 2)))
#xff))
(set (index newval) (set (reg h-gr (div index 2))
(if SI (mod index 2)
(or (and (reg h-gr (div index 2)) #xff)
(sll (and newval #xff) 8))
(or (and (reg h-gr (div index 2)) #xff00)
(and newval #xff))))))
(define-hardware
(name h-gr-HI)
(comment "general 16 bit registers")
(attrs all-isas VIRTUAL)
(type register HI (4))
(indices keyword "" (("r0" 0) ("r1" 1) ("r2" 2) ("r3" 3)))
(get (index) (reg h-gr index))
(set (index newval) (set (reg h-gr index) newval)))
(define-hardware
(name h-gr-SI)
(comment "general 32 bit registers")
(attrs all-isas VIRTUAL)
(type register SI (2))
(indices keyword "" (("r2r0" 0) ("r3r1" 1)))
(get (index) (or SI
(and (reg h-gr index) #xffff)
(and (sll (reg h-gr (add index 2)) 16) #xffff0000)))
(set (index newval) (sequence ()
(set (reg h-gr index) (and newval #xffff))
(set (reg h-gr (add index 2)) (srl newval 16)))))
(define-hardware
(name h-gr-ext-QI)
(comment "general 16 bit registers")
(attrs all-isas VIRTUAL)
(type register HI (2))
(indices keyword "" (("r0l" 0) ("r1l" 1)))
(get (index) (reg h-gr-QI (mul index 2)))
(set (index newval) (set (reg h-gr (mul index 2)) newval)))
(define-hardware
(name h-gr-ext-HI)
(comment "general 16 bit registers")
(attrs all-isas VIRTUAL)
(type register SI (2))
(indices keyword "" (("r0" 0) ("r1" 1)))
(get (index) (reg h-gr (mul index 2)))
(set (index newval) (set (reg h-gr-SI index) newval)))
(define-hardware
(name h-r0l)
(comment "r0l register")
(attrs all-isas VIRTUAL)
(type register QI)
(indices keyword "" (("r0l" 0)))
(get () (reg h-gr-QI 0))
(set (newval) (set (reg h-gr-QI 0) newval)))
(define-hardware
(name h-r0h)
(comment "r0h register")
(attrs all-isas VIRTUAL)
(type register QI)
(indices keyword "" (("r0h" 0)))
(get () (reg h-gr-QI 1))
(set (newval) (set (reg h-gr-QI 1) newval)))
(define-hardware
(name h-r1l)
(comment "r1l register")
(attrs all-isas VIRTUAL)
(type register QI)
(indices keyword "" (("r1l" 0)))
(get () (reg h-gr-QI 2))
(set (newval) (set (reg h-gr-QI 2) newval)))
(define-hardware
(name h-r1h)
(comment "r1h register")
(attrs all-isas VIRTUAL)
(type register QI)
(indices keyword "" (("r1h" 0)))
(get () (reg h-gr-QI 3))
(set (newval) (set (reg h-gr-QI 3) newval)))
(define-hardware
(name h-r0)
(comment "r0 register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("r0" 0)))
(get () (reg h-gr 0))
(set (newval) (set (reg h-gr 0) newval)))
(define-hardware
(name h-r1)
(comment "r1 register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("r1" 0)))
(get () (reg h-gr 1))
(set (newval) (set (reg h-gr 1) newval)))
(define-hardware
(name h-r2)
(comment "r2 register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("r2" 0)))
(get () (reg h-gr 2))
(set (newval) (set (reg h-gr 2) newval)))
(define-hardware
(name h-r3)
(comment "r3 register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("r3" 0)))
(get () (reg h-gr 3))
(set (newval) (set (reg h-gr 3) newval)))
(define-hardware
(name h-r0l-r0h)
(comment "r0l or r0h")
(attrs all-isas VIRTUAL)
(type register QI (2))
(indices keyword "" (("r0l" 0) ("r0h" 1)))
(get (index) (reg h-gr-QI index))
(set (index newval) (set (reg h-gr-QI index) newval)))
(define-hardware
(name h-r2r0)
(comment "r2r0 register")
(attrs all-isas VIRTUAL)
(type register SI)
(indices keyword "" (("r2r0" 0)))
(get () (or (sll (reg h-gr 2) 16) (reg h-gr 0)))
(set (newval)
(sequence ()
(set (reg h-gr 0) newval)
(set (reg h-gr 2) (sra newval 16)))))
(define-hardware
(name h-r3r1)
(comment "r3r1 register")
(attrs all-isas VIRTUAL)
(type register SI)
(indices keyword "" (("r3r1" 0)))
(get () (or (sll (reg h-gr 3) 16) (reg h-gr 1)))
(set (newval)
(sequence ()
(set (reg h-gr 1) newval)
(set (reg h-gr 3) (sra newval 16)))))
(define-hardware
(name h-r1r2r0)
(comment "r1r2r0 register")
(attrs all-isas VIRTUAL)
(type register DI)
(indices keyword "" (("r1r2r0" 0)))
(get () (or DI (sll DI (reg h-gr 1) 32) (or (sll (reg h-gr 2) 16) (reg h-gr 0))))
(set (newval)
(sequence ()
(set (reg h-gr 0) newval)
(set (reg h-gr 2) (sra newval 16))
(set (reg h-gr 1) (sra newval 32)))))
;-------------------------------------------------------------
; Address registers
;-------------------------------------------------------------
(define-hardware
(name h-ar)
(comment "address registers")
(attrs all-isas)
(type register USI (2))
(indices keyword "" (("a0" 0) ("a1" 1)))
(get (index) (c-call USI "h_ar_get_handler" index))
(set (index newval) (c-call VOID "h_ar_set_handler" index newval)))
; Define different views of the ars as VIRTUAL with getter/setter specs
(define-hardware
(name h-ar-QI)
(comment "8 bit view of address register")
(attrs all-isas VIRTUAL)
(type register QI (2))
(indices keyword "" (("a0" 0) ("a1" 1)))
(get (index) (reg h-ar index))
(set (index newval) (set (reg h-ar index) newval)))
(define-hardware
(name h-ar-HI)
(comment "16 bit view of address register")
(attrs all-isas VIRTUAL)
(type register HI (2))
(indices keyword "" (("a0" 0) ("a1" 1)))
(get (index) (reg h-ar index))
(set (index newval) (set (reg h-ar index) newval)))
(define-hardware
(name h-ar-SI)
(comment "32 bit view of address register")
(attrs all-isas VIRTUAL)
(type register SI)
(indices keyword "" (("a1a0" 0)))
(get () (or SI (sll SI (ext SI (reg h-ar 1)) 16) (ext SI (reg h-ar 0))))
(set (newval) (sequence ()
(set (reg h-ar 0) (and newval #xffff))
(set (reg h-ar 1) (and (srl newval 16) #xffff)))))
(define-hardware
(name h-a0)
(comment "16 bit view of address register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("a0" 0)))
(get () (reg h-ar 0))
(set (newval) (set (reg h-ar 0) newval)))
(define-hardware
(name h-a1)
(comment "16 bit view of address register")
(attrs all-isas VIRTUAL)
(type register HI)
(indices keyword "" (("a1" 1)))
(get () (reg h-ar 1))
(set (newval) (set (reg h-ar 1) newval)))
; SB Register
(define-hardware
(name h-sb)
(comment "SB register")
(attrs all-isas)
(type register USI)
(get () (c-call USI "h_sb_get_handler"))
(set (newval) (c-call VOID "h_sb_set_handler" newval))
)
; FB Register
(define-hardware
(name h-fb)
(comment "FB register")
(attrs all-isas)
(type register USI)
(get () (c-call USI "h_fb_get_handler"))
(set (newval) (c-call VOID "h_fb_set_handler" newval))
)
; SP Register
(define-hardware
(name h-sp)
(comment "SP register")
(attrs all-isas)
(type register USI)
(get () (c-call USI "h_sp_get_handler"))
(set (newval) (c-call VOID "h_sp_set_handler" newval))
)
;-------------------------------------------------------------
; condition-code bits
;-------------------------------------------------------------
(define-hardware
(name h-sbit)
(comment "sign bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-zbit)
(comment "zero bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-obit)
(comment "overflow bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-cbit)
(comment "carry bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-ubit)
(comment "stack pointer select bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-ibit)
(comment "interrupt enable bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-bbit)
(comment "register bank select bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-dbit)
(comment "debug bit")
(attrs all-isas)
(type register BI)
)
(define-hardware
(name h-dct0)
(comment "dma transfer count 000")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-dct1)
(comment "dma transfer count 001")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-svf)
(comment "save flag 011")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-drc0)
(comment "dma transfer count reload 100")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-drc1)
(comment "dma transfer count reload 101")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-dmd0)
(comment "dma mode 110")
(attrs all-isas)
(type register UQI)
)
(define-hardware
(name h-dmd1)
(comment "dma mode 111")
(attrs all-isas)
(type register UQI)
)
(define-hardware
(name h-intb)
(comment "interrupt table 000")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-svp)
(comment "save pc 100")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-vct)
(comment "vector 101")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-isp)
(comment "interrupt stack ptr 111")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dma0)
(comment "dma mem addr 010")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dma1)
(comment "dma mem addr 011")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dra0)
(comment "dma mem addr reload 100")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dra1)
(comment "dma mem addr reload 101")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dsa0)
(comment "dma sfr addr 110")
(attrs all-isas)
(type register USI)
)
(define-hardware
(name h-dsa1)
(comment "dma sfr addr 111")
(attrs all-isas)
(type register USI)
)
;-------------------------------------------------------------
; Condition code operand hardware
;-------------------------------------------------------------
(define-hardware
(name h-cond16)
(comment "condition code hardware for m16c")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword ""
(("geu" #x00) ("c" #x00)
("gtu" #x01)
("eq" #x02) ("z" #x02)
("n" #x03)
("le" #x04)
("o" #x05)
("ge" #x06)
("ltu" #xf8) ("nc" #xf8)
("leu" #xf9)
("ne" #xfa) ("nz" #xfa)
("pz" #xfb)
("gt" #xfc)
("no" #xfd)
("lt" #xfe)
)
)
)
(define-hardware
(name h-cond16c)
(comment "condition code hardware for m16c")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword ""
(("geu" #x00) ("c" #x00)
("gtu" #x01)
("eq" #x02) ("z" #x02)
("n" #x03)
("ltu" #x04) ("nc" #x04)
("leu" #x05)
("ne" #x06) ("nz" #x06)
("pz" #x07)
("le" #x08)
("o" #x09)
("ge" #x0a)
("gt" #x0c)
("no" #x0d)
("lt" #x0e)
)
)
)
(define-hardware
(name h-cond16j)
(comment "condition code hardware for m16c")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword ""
(("le" #x08)
("o" #x09)
("ge" #x0a)
("gt" #x0c)
("no" #x0d)
("lt" #x0e)
)
)
)
(define-hardware
(name h-cond16j-5)
(comment "condition code hardware for m16c")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword ""
(("geu" #x00) ("c" #x00)
("gtu" #x01)
("eq" #x02) ("z" #x02)
("n" #x03)
("ltu" #x04) ("nc" #x04)
("leu" #x05)
("ne" #x06) ("nz" #x06)
("pz" #x07)
)
)
)
(define-hardware
(name h-cond32)
(comment "condition code hardware for m32c")
(attrs m32c-isa MACH32)
(type immediate UQI)
(values keyword ""
(("ltu" #x00) ("nc" #x00)
("leu" #x01)
("ne" #x02) ("nz" #x02)
("pz" #x03)
("no" #x04)
("gt" #x05)
("ge" #x06)
("geu" #x08) ("c" #x08)
("gtu" #x09)
("eq" #x0a) ("z" #x0a)
("n" #x0b)
("o" #x0c)
("le" #x0d)
("lt" #x0e)
)
)
)
(define-hardware
(name h-cr1-32)
(comment "control registers")
(attrs m32c-isa MACH32)
(type immediate UQI)
(values keyword "" (("dct0" 0) ("dct1" 1) ("flg" 2) ("svf" 3) ("drc0" 4)
("drc1" 5) ("dmd0" 6) ("dmd1" 7))))
(define-hardware
(name h-cr2-32)
(comment "control registers")
(attrs m32c-isa MACH32)
(type immediate UQI)
(values keyword "" (("intb" 0) ("sp" 1) ("sb" 2) ("fb" 3) ("svp" 4)
("vct" 5) ("isp" 7))))
(define-hardware
(name h-cr3-32)
(comment "control registers")
(attrs m32c-isa MACH32)
(type immediate UQI)
(values keyword "" (("dma0" 2) ("dma1" 3) ("dra0" 4)
("dra1" 5) ("dsa0" 6) ("dsa1" 7))))
(define-hardware
(name h-cr-16)
(comment "control registers")
(attrs m16c-isa MACH16)
(type immediate UQI)
(values keyword "" (("intbl" 1) ("intbh" 2) ("flg" 3) ("isp" 4)
("sp" 5) ("sb" 6) ("fb" 7))))
(define-hardware
(name h-flags)
(comment "flag hardware for m32c")
(attrs all-isas)
(type immediate UQI)
(values keyword ""
(("c" #x0)
("d" #x1)
("z" #x2)
("s" #x3)
("b" #x4)
("o" #x5)
("i" #x6)
("u" #x7)
)
)
)
;-------------------------------------------------------------
; Misc helper hardware
;-------------------------------------------------------------
(define-hardware
(name h-shimm)
(comment "shift immediate")
(attrs all-isas)
(type immediate (INT 4))
(values keyword "" (("1" 0) ("2" 1) ("3" 2) ("4" 3) ("5" 4) ("6" 5) ("7" 6)
("8" 7) ("-1" -8) ("-2" -7) ("-3" -6) ("-4" -5) ("-5" -4)
("-6" -3) ("-7" -2) ("-8" -1)
)))
(define-hardware
(name h-bit-index)
(comment "bit index for the next insn")
(attrs m32c-isa MACH32)
(type register UHI)
)
(define-hardware
(name h-src-index)
(comment "source index for the next insn")
(attrs m32c-isa MACH32)
(type register UHI)
)
(define-hardware
(name h-dst-index)
(comment "destination index for the next insn")
(attrs m32c-isa MACH32)
(type register UHI)
)
(define-hardware
(name h-src-indirect)
(comment "indirect src for the next insn")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-dst-indirect)
(comment "indirect dst for the next insn")
(attrs all-isas)
(type register UHI)
)
(define-hardware
(name h-none)
(comment "for storing unused values")
(attrs m32c-isa MACH32)
(type register SI)
)
;=============================================================
; Operands
;-------------------------------------------------------------
; Source Registers
;-------------------------------------------------------------
(dnop Src16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-src16-rn)
(dnop Src16RnHI "general register QH view" (MACH16 m16c-isa) h-gr-HI f-src16-rn)
(dnop Src32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-unprefixed-QI)
(dnop Src32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-unprefixed-HI)
(dnop Src32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-unprefixed-SI)
(dnop Src32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-src32-rn-prefixed-QI)
(dnop Src32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-src32-rn-prefixed-HI)
(dnop Src32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-src32-rn-prefixed-SI)
(dnop Src16An "address register" (MACH16 m16c-isa) h-ar f-src16-an)
(dnop Src16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-src16-an)
(dnop Src16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-src16-an)
(dnop Src32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed)
(dnop Src32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-unprefixed)
(dnop Src32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-unprefixed)
(dnop Src32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-unprefixed)
(dnop Src32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-src32-an-prefixed)
(dnop Src32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-src32-an-prefixed)
(dnop Src32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-src32-an-prefixed)
(dnop Src32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-src32-an-prefixed)
; Destination Registers
;
(dnop Dst16RnQI "general register QI view" (MACH16 m16c-isa) h-gr-QI f-dst16-rn)
(dnop Dst16RnHI "general register HI view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
(dnop Dst16RnSI "general register SI view" (MACH16 m16c-isa) h-gr-SI f-dst16-rn)
(dnop Dst16RnExtQI "general register QI/HI view for 'ext' insns" (MACH16 m16c-isa) h-gr-ext-QI f-dst16-rn-ext)
(dnop Dst32R0QI-S "general register QI view" (MACH32 m32c-isa) h-r0l f-nil)
(dnop Dst32R0HI-S "general register HI view" (MACH32 m32c-isa) h-r0 f-nil)
(dnop Dst32RnUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
(dnop Dst32RnUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-unprefixed-HI)
(dnop Dst32RnUnprefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-unprefixed-SI)
(dnop Dst32RnExtUnprefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-ext-QI f-dst32-rn-ext-unprefixed)
(dnop Dst32RnExtUnprefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-ext-HI f-dst32-rn-ext-unprefixed)
(dnop Dst32RnPrefixedQI "general register QI view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
(dnop Dst32RnPrefixedHI "general register HI view" (MACH32 m32c-isa) h-gr-HI f-dst32-rn-prefixed-HI)
(dnop Dst32RnPrefixedSI "general register SI view" (MACH32 m32c-isa) h-gr-SI f-dst32-rn-prefixed-SI)
(dnop Dst16RnQI-S "general register QI view" (MACH16 m16c-isa) h-r0l-r0h f-dst16-rn-QI-s)
(dnop Dst16AnQI-S "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-rn-QI-s)
(dnop Bit16Rn "general register bit view" (MACH16 m16c-isa) h-gr-HI f-dst16-rn)
(dnop Bit32RnPrefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-prefixed-QI)
(dnop Bit32RnUnprefixed "general register bit view" (MACH32 m32c-isa) h-gr-QI f-dst32-rn-unprefixed-QI)
(dnop R0 "r0" (all-isas) h-r0 f-nil)
(dnop R1 "r1" (all-isas) h-r1 f-nil)
(dnop R2 "r2" (all-isas) h-r2 f-nil)
(dnop R3 "r3" (all-isas) h-r3 f-nil)
(dnop R0l "r0l" (all-isas) h-r0l f-nil)
(dnop R0h "r0h" (all-isas) h-r0h f-nil)
(dnop R2R0 "r2r0" (all-isas) h-r2r0 f-nil)
(dnop R3R1 "r3r1" (all-isas) h-r3r1 f-nil)
(dnop R1R2R0 "r1r2r0" (all-isas) h-r1r2r0 f-nil)
(dnop Dst16An "address register" (MACH16 m16c-isa) h-ar f-dst16-an)
(dnop Dst16AnQI "address register QI view" (MACH16 m16c-isa) h-ar-QI f-dst16-an)
(dnop Dst16AnHI "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an)
(dnop Dst16AnSI "address register SI view" (MACH16 m16c-isa) h-ar-SI f-dst16-an)
(dnop Dst16An-S "address register HI view" (MACH16 m16c-isa) h-ar-HI f-dst16-an-s)
(dnop Dst32AnUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
(dnop Dst32AnUnprefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-unprefixed)
(dnop Dst32AnUnprefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-unprefixed)
(dnop Dst32AnUnprefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
(dnop Dst32AnExtUnprefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
(dnop Dst32AnPrefixed "address register" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
(dnop Dst32AnPrefixedQI "address register QI view" (MACH32 m32c-isa) h-ar-QI f-dst32-an-prefixed)
(dnop Dst32AnPrefixedHI "address register HI view" (MACH32 m32c-isa) h-ar-HI f-dst32-an-prefixed)
(dnop Dst32AnPrefixedSI "address register SI view" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
(dnop Bit16An "address register bit view" (MACH16 m16c-isa) h-ar f-dst16-an)
(dnop Bit32AnPrefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-prefixed)
(dnop Bit32AnUnprefixed "address register bit" (MACH32 m32c-isa) h-ar f-dst32-an-unprefixed)
(dnop A0 "a0" (all-isas) h-a0 f-nil)
(dnop A1 "a1" (all-isas) h-a1 f-nil)
(dnop sb "SB register" (all-isas SEM-ONLY) h-sb f-nil)
(dnop fb "FB register" (all-isas SEM-ONLY) h-fb f-nil)
(dnop sp "SP register" (all-isas SEM-ONLY) h-sp f-nil)
(define-full-operand SrcDst16-r0l-r0h-S-normal "r0l/r0h pair" (MACH16 m16c-isa)
h-sint DFLT f-5-1
((parse "r0l_r0h") (print "r0l_r0h")) () ()
)
(define-full-operand Regsetpop "popm regset" (all-isas) h-uint
DFLT f-8-8 ((parse "pop_regset") (print "pop_regset")) () ())
(define-full-operand Regsetpush "pushm regset" (all-isas) h-uint
DFLT f-8-8 ((parse "push_regset") (print "push_regset")) () ())
(dnop Rn16-push-S "r0[lh]" (MACH16 m16c-isa) h-gr-QI f-4-1)
(dnop An16-push-S "a[01]" (MACH16 m16c-isa) h-ar-HI f-4-1)
;-------------------------------------------------------------
; Offsets and absolutes
;-------------------------------------------------------------
(define-full-operand Dsp-8-u6 "unsigned 6 bit displacement at offset 8 bits" (all-isas)
h-uint DFLT f-dsp-8-u6
((parse "unsigned6")) () ()
)
(define-full-operand Dsp-8-u8 "unsigned 8 bit displacement at offset 8 bits" (all-isas)
h-uint DFLT f-dsp-8-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-8-u16 "unsigned 16 bit displacement at offset 8 bits" (all-isas)
h-uint DFLT f-dsp-8-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-8-s8 "signed 8 bit displacement at offset 8 bits" (all-isas)
h-sint DFLT f-dsp-8-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas)
h-sint DFLT f-dsp-8-s24
((parse "signed24")) () ()
)
(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas)
h-uint DFLT f-dsp-8-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas)
h-uint DFLT f-dsp-10-u6
((parse "unsigned6")) () ()
)
(define-full-operand Dsp-16-u8 "unsigned 8 bit displacement at offset 16 bits" (all-isas)
h-uint DFLT f-dsp-16-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-16-u16 "unsigned 16 bit displacement at offset 16 bits" (all-isas)
h-uint DFLT f-dsp-16-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-16-u20 "unsigned 20 bit displacement at offset 16 bits" (all-isas)
h-uint DFLT f-dsp-16-u24
((parse "unsigned20")) () ()
)
(define-full-operand Dsp-16-u24 "unsigned 24 bit displacement at offset 16 bits" (all-isas)
h-uint DFLT f-dsp-16-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-16-s8 "signed 8 bit displacement at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-16-s16 "signed 16 bit displacement at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-24-u8 "unsigned 8 bit displacement at offset 24 bits" (all-isas)
h-uint DFLT f-dsp-24-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-24-u16 "unsigned 16 bit displacement at offset 24 bits" (all-isas)
h-uint DFLT f-dsp-24-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-24-u20 "unsigned 20 bit displacement at offset 24 bits" (all-isas)
h-uint DFLT f-dsp-24-u24
((parse "unsigned20")) () ()
)
(define-full-operand Dsp-24-u24 "unsigned 24 bit displacement at offset 24 bits" (all-isas)
h-uint DFLT f-dsp-24-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-24-s8 "signed 8 bit displacement at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-24-s16 "signed 16 bit displacement at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-32-u8 "unsigned 8 bit displacement at offset 32 bits" (all-isas)
h-uint DFLT f-dsp-32-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-32-u16 "unsigned 16 bit displacement at offset 32 bits" (all-isas)
h-uint DFLT f-dsp-32-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-32-u24 "unsigned 24 bit displacement at offset 32 bits" (all-isas)
h-uint DFLT f-dsp-32-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-32-u20 "unsigned 20 bit displacement at offset 32 bits" (all-isas)
h-uint DFLT f-dsp-32-u24
((parse "unsigned20")) () ()
)
(define-full-operand Dsp-32-s8 "signed 8 bit displacement at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-32-s16 "signed 16 bit displacement at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-40-u8 "unsigned 8 bit displacement at offset 40 bits" (all-isas)
h-uint DFLT f-dsp-40-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas)
h-uint DFLT f-dsp-40-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas)
h-uint DFLT f-dsp-40-u20
((parse "unsigned20")) () ()
)
(define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas)
h-uint DFLT f-dsp-40-u24
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-48-u8 "unsigned 8 bit displacement at offset 48 bits" (all-isas)
h-uint DFLT f-dsp-48-u8
((parse "unsigned8")) () ()
)
(define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s8
((parse "signed8")) () ()
)
(define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas)
h-uint DFLT f-dsp-48-u16
((parse "unsigned16")) () ()
)
(define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s16
((parse "signed16")) () ()
)
(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas)
h-uint DFLT f-dsp-48-u20
((parse "unsigned24")) () ()
)
(define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas)
h-uint DFLT f-dsp-48-u24
((parse "unsigned24")) () ()
)
(define-full-operand Imm-8-s4 "signed 4 bit immediate at offset 8 bits" (all-isas)
h-sint DFLT f-imm-8-s4
((parse "signed4")) () ()
)
(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas)
h-sint DFLT f-imm-8-s4
((parse "signed4n") (print "signed4n")) () ()
)
(define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas)
h-shimm DFLT f-imm-8-s4
() () ()
)
(define-full-operand Imm-8-QI "signed 8 bit immediate at offset 8 bits" (all-isas)
h-sint DFLT f-dsp-8-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-8-HI "signed 16 bit immediate at offset 8 bits" (all-isas)
h-sint DFLT f-dsp-8-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-12-s4 "signed 4 bit immediate at offset 12 bits" (all-isas)
h-sint DFLT f-imm-12-s4
((parse "signed4")) () ()
)
(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas)
h-sint DFLT f-imm-12-s4
((parse "signed4n") (print "signed4n")) () ()
)
(define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
h-shimm DFLT f-imm-12-s4
() () ()
)
(define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas)
h-sint DFLT f-imm-13-u3
((parse "signed4")) () ()
)
(define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas)
h-sint DFLT f-imm-20-s4
((parse "signed4")) () ()
)
(define-full-operand Imm-sh-20-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas)
h-shimm DFLT f-imm-20-s4
() () ()
)
(define-full-operand Imm-16-QI "signed 8 bit immediate at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-16-HI "signed 16 bit immediate at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-16-SI "signed 32 bit immediate at offset 16 bits" (all-isas)
h-sint DFLT f-dsp-16-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-24-QI "signed 8 bit immediate at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-24-HI "signed 16 bit immediate at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-24-SI "signed 32 bit immediate at offset 24 bits" (all-isas)
h-sint DFLT f-dsp-24-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-32-QI "signed 8 bit immediate at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-32-SI "signed 32 bit immediate at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-32-HI "signed 16 bit immediate at offset 32 bits" (all-isas)
h-sint DFLT f-dsp-32-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-40-QI "signed 8 bit immediate at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-40-HI "signed 16 bit immediate at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-40-SI "signed 32 bit immediate at offset 40 bits" (all-isas)
h-sint DFLT f-dsp-40-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-48-QI "signed 8 bit immediate at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-48-HI "signed 16 bit immediate at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-48-SI "signed 32 bit immediate at offset 48 bits" (all-isas)
h-sint DFLT f-dsp-48-s32
((parse "signed32")) () ()
)
(define-full-operand Imm-56-QI "signed 8 bit immediate at offset 56 bits" (all-isas)
h-sint DFLT f-dsp-56-s8
((parse "signed8")) () ()
)
(define-full-operand Imm-56-HI "signed 16 bit immediate at offset 56 bits" (all-isas)
h-sint DFLT f-dsp-56-s16
((parse "signed16")) () ()
)
(define-full-operand Imm-64-HI "signed 16 bit immediate at offset 64 bits" (all-isas)
h-sint DFLT f-dsp-64-s16
((parse "signed16")) () ()
)
(define-full-operand Imm1-S "signed 1 bit immediate for short format binary insns" (m32c-isa)
h-sint DFLT f-imm1-S
((parse "imm1_S")) () ()
)
(define-full-operand Imm3-S "signed 3 bit immediate for short format binary insns" (m32c-isa)
h-sint DFLT f-imm3-S
((parse "imm3_S")) () ()
)
(define-full-operand Bit3-S "3 bit bit number" (m32c-isa)
h-sint DFLT f-imm3-S
((parse "bit3_S")) () ()
)
;-------------------------------------------------------------
; Bit numbers
;-------------------------------------------------------------
(define-full-operand Bitno16R "bit number for indexing registers" (m16c-isa)
h-uint DFLT f-dsp-16-u8
((parse "Bitno16R")) () ()
)
(dnop Bitno32Prefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-prefixed)
(dnop Bitno32Unprefixed "bit number for indexing objects" (m32c-isa) h-uint f-bitno32-unprefixed)
(define-full-operand BitBase16-16-u8 "unsigned bit,base:8 at offset 16for m16c" (m16c-isa)
h-uint DFLT f-dsp-16-u8
((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa)
h-sint DFLT f-dsp-16-s8
((parse "signed_bitbase8") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa)
h-uint DFLT f-dsp-16-u16
((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa)
h-uint DFLT f-bitbase16-u11-S
((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-16-u11-Unprefixed "unsigned bit,base:11 at offset 16 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-16-u11-unprefixed
((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-16-s11-Unprefixed "signed bit,base:11 at offset 16 for m32c" (m32c-isa)
h-sint DFLT f-bitbase32-16-s11-unprefixed
((parse "signed_bitbase11") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase32-16-u19-Unprefixed "unsigned bit,base:19 at offset 16 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-16-u19-unprefixed
((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-16-s19-Unprefixed "signed bit,base:19 at offset 16 for m32c" (m32c-isa)
h-sint DFLT f-bitbase32-16-s19-unprefixed
((parse "signed_bitbase19") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase32-16-u27-Unprefixed "unsigned bit,base:27 at offset 16 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-16-u27-unprefixed
((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-24-u11-Prefixed "unsigned bit,base:11 at offset 24 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-24-u11-prefixed
((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-24-s11-Prefixed "signed bit,base:11 at offset 24 for m32c" (m32c-isa)
h-sint DFLT f-bitbase32-24-s11-prefixed
((parse "signed_bitbase11") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase32-24-u19-Prefixed "unsigned bit,base:19 at offset 24 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-24-u19-prefixed
((parse "unsigned_bitbase19") (print "unsigned_bitbase")) () ()
)
(define-full-operand BitBase32-24-s19-Prefixed "signed bit,base:19 at offset 24 for m32c" (m32c-isa)
h-sint DFLT f-bitbase32-24-s19-prefixed
((parse "signed_bitbase19") (print "signed_bitbase")) () ()
)
(define-full-operand BitBase32-24-u27-Prefixed "unsigned bit,base:27 at offset 24 for m32c" (m32c-isa)
h-uint DFLT f-bitbase32-24-u27-prefixed
((parse "unsigned_bitbase27") (print "unsigned_bitbase")) () ()
)
;-------------------------------------------------------------
; Labels
;-------------------------------------------------------------
(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX)
h-iaddr DFLT f-lab-5-3
((parse "lab_5_3")) () () )
(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX)
h-iaddr DFLT f-lab32-jmp-s
((parse "lab_5_3")) () () )
(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8)
(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16)
(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24)
(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8)
(dnop Lab-24-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-24-8)
(dnop Lab-32-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-32-8)
(dnop Lab-40-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-40-8)
;-------------------------------------------------------------
; Condition code bits
;-------------------------------------------------------------
(dnop sbit "negative bit" (SEM-ONLY all-isas) h-sbit f-nil)
(dnop obit "overflow bit" (SEM-ONLY all-isas) h-obit f-nil)
(dnop zbit "zero bit" (SEM-ONLY all-isas) h-zbit f-nil)
(dnop cbit "carry bit" (SEM-ONLY all-isas) h-cbit f-nil)
(dnop ubit "stack ptr select bit" (SEM-ONLY all-isas) h-ubit f-nil)
(dnop ibit "interrupt enable bit" (SEM-ONLY all-isas) h-ibit f-nil)
(dnop bbit "reg bank select bit" (SEM-ONLY all-isas) h-bbit f-nil)
(dnop dbit "debug bit" (SEM-ONLY all-isas) h-dbit f-nil)
;-------------------------------------------------------------
; Condition operands
;-------------------------------------------------------------
(define-pmacro (cond-operand mach offset)
(dnop (.sym cond mach - offset) "condition" ((.sym m mach c-isa)) (.sym h-cond mach) (.sym f-dsp- offset -u8))
)
(cond-operand 16 16)
(cond-operand 16 24)
(cond-operand 16 32)
(cond-operand 32 16)
(cond-operand 32 24)
(cond-operand 32 32)
(cond-operand 32 40)
(dnop cond16c "condition" (m16c-isa) h-cond16c f-cond16)
(dnop cond16j "condition" (m16c-isa) h-cond16j f-cond16)
(dnop cond16j5 "condition" (m16c-isa) h-cond16j-5 f-cond16j-5)
(dnop cond32 "condition" (m32c-isa) h-cond32 f-cond32)
(dnop cond32j "condition" (m32c-isa) h-cond32 f-cond32j)
(dnop sccond32 "scCND condition" (m32c-isa) h-cond32 f-cond16)
(dnop flags16 "flags" (m16c-isa) h-flags f-9-3)
(dnop flags32 "flags" (m32c-isa) h-flags f-13-3)
(dnop cr16 "control" (m16c-isa) h-cr-16 f-9-3)
(dnop cr1-Unprefixed-32 "control" (m32c-isa) h-cr1-32 f-13-3)
(dnop cr1-Prefixed-32 "control" (m32c-isa) h-cr1-32 f-21-3)
(dnop cr2-32 "control" (m32c-isa) h-cr2-32 f-13-3)
(dnop cr3-Unprefixed-32 "control" (m32c-isa) h-cr3-32 f-13-3)
(dnop cr3-Prefixed-32 "control" (m32c-isa) h-cr3-32 f-21-3)
;-------------------------------------------------------------
; Suffixes
;-------------------------------------------------------------
(define-full-operand Z "Suffix for zero format insns" (all-isas)
h-sint DFLT f-nil
((parse "Z") (print "Z")) () ()
)
(define-full-operand S "Suffix for short format insns" (all-isas)
h-sint DFLT f-nil
((parse "S") (print "S")) () ()
)
(define-full-operand Q "Suffix for quick format insns" (all-isas)
h-sint DFLT f-nil
((parse "Q") (print "Q")) () ()
)
(define-full-operand G "Suffix for general format insns" (all-isas)
h-sint DFLT f-nil
((parse "G") (print "G")) () ()
)
(define-full-operand X "Empty suffix" (all-isas)
h-sint DFLT f-nil
((parse "X") (print "X")) () ()
)
(define-full-operand size "any size specifier" (all-isas)
h-sint DFLT f-nil
((parse "size") (print "size")) () ()
)
;-------------------------------------------------------------
; Misc
;-------------------------------------------------------------
(dnop BitIndex "Bit Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-bit-index f-nil)
(dnop SrcIndex "Source Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-src-index f-nil)
(dnop DstIndex "Destination Index for the next insn" (SEM-ONLY MACH32 m32c-isa) h-dst-index f-nil)
(dnop NoRemainder "Place holder for when the remainder is not kept" (SEM-ONLY MACH32 m32c-isa) h-none f-nil)
;=============================================================
; Derived Operands
; Memory reference macros that clip addresses appropriately. Refer to
; memory at ADDRESS in MODE, clipped appropriately for either the m16c
; or m32c.
(define-pmacro (mem16 mode address)
(mem mode (and #xffff address)))
(define-pmacro (mem20 mode address)
(mem mode (and #xfffff address)))
(define-pmacro (mem32 mode address)
(mem mode (and #xffffff address)))
; Like mem16 and mem32, but takes MACH as a parameter. MACH must be
; either 16 or 32.
(define-pmacro (mem-mach mach mode address)
((.sym mem mach) mode address))
;-------------------------------------------------------------
; Source
;-------------------------------------------------------------
; Rn direct
;-------------------------------------------------------------
(define-pmacro (src16-Rn-direct-operand xmode)
(begin
(define-derived-operand
(name (.sym src16-Rn-direct- xmode))
(comment (.str "m16c Rn direct source " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Src16Rn xmode)))
(syntax (.str "$Src16Rn" xmode))
(base-ifield f-8-4)
(encoding (+ (f-8-2 0) (.sym Src16Rn xmode)))
(ifield-assertion (eq f-8-2 0))
(getter (trunc xmode (.sym Src16Rn xmode)))
(setter (set (.sym Src16Rn xmode) newval))
)
)
)
(src16-Rn-direct-operand QI)
(src16-Rn-direct-operand HI)
(define-pmacro (src32-Rn-direct-operand group base xmode)
(begin
(define-derived-operand
(name (.sym src32-Rn-direct- group - xmode))
(comment (.str "m32c Rn direct source " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32Rn group xmode)))
(syntax (.str "$Src32Rn" group xmode))
(base-ifield (.sym f- base -11))
(encoding (+ ((.sym f- base -3) 4) (.sym Src32Rn group xmode)))
(ifield-assertion (eq (.sym f- base -3) 4))
(getter (trunc xmode (.sym Src32Rn group xmode)))
(setter (set (.sym Src32Rn group xmode) newval))
)
)
)
(src32-Rn-direct-operand Unprefixed 1 QI)
(src32-Rn-direct-operand Prefixed 9 QI)
(src32-Rn-direct-operand Unprefixed 1 HI)
(src32-Rn-direct-operand Prefixed 9 HI)
(src32-Rn-direct-operand Unprefixed 1 SI)
(src32-Rn-direct-operand Prefixed 9 SI)
;-------------------------------------------------------------
; An direct
;-------------------------------------------------------------
(define-pmacro (src16-An-direct-operand xmode)
(begin
(define-derived-operand
(name (.sym src16-An-direct- xmode))
(comment (.str "m16c An direct destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Src16An xmode)))
(syntax (.str "$Src16An" xmode))
(base-ifield f-8-4)
(encoding (+ (f-8-2 1) (f-10-1 0) (.sym Src16An xmode)))
(ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 0)))
(getter (trunc xmode (.sym Src16An xmode)))
(setter (set (.sym Src16An xmode) newval))
)
)
)
(src16-An-direct-operand QI)
(src16-An-direct-operand HI)
(define-pmacro (src32-An-direct-operand group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym src32-An-direct- group - xmode))
(comment (.str "m32c An direct destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group xmode)))
(syntax (.str "$Src32An" group xmode))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Src32An group xmode)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
(getter (trunc xmode (.sym Src32An group xmode)))
(setter (set (.sym Src32An group xmode) newval))
)
)
)
(src32-An-direct-operand Unprefixed 1 10 QI)
(src32-An-direct-operand Unprefixed 1 10 HI)
(src32-An-direct-operand Unprefixed 1 10 SI)
(src32-An-direct-operand Prefixed 9 18 QI)
(src32-An-direct-operand Prefixed 9 18 HI)
(src32-An-direct-operand Prefixed 9 18 SI)
;-------------------------------------------------------------
; An indirect
;-------------------------------------------------------------
(define-pmacro (src16-An-indirect-operand xmode)
(begin
(define-derived-operand
(name (.sym src16-An-indirect- xmode))
(comment (.str "m16c An indirect destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Src16An))
(syntax "[$Src16An]")
(base-ifield f-8-4)
(encoding (+ (f-8-2 1) (f-10-1 1) Src16An))
(ifield-assertion (andif (eq f-8-2 1) (eq f-10-1 1)))
(getter (mem16 xmode Src16An))
(setter (set (mem16 xmode Src16An) newval))
)
)
)
(src16-An-indirect-operand QI)
(src16-An-indirect-operand HI)
(define-pmacro (src32-An-indirect-operand group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym src32-An-indirect- group - xmode))
(comment (.str "m32c An indirect destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group)))
(syntax (.str "[$Src32An" group "]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Src32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
(getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group)
(const 0)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval
(.sym Src32An group) (const 0)))
; (getter (mem32 xmode (.sym Src32An group)))
; (setter (set (mem32 xmode (.sym Src32An group)) newval))
)
)
)
(src32-An-indirect-operand Unprefixed 1 10 QI)
(src32-An-indirect-operand Unprefixed 1 10 HI)
(src32-An-indirect-operand Unprefixed 1 10 SI)
(src32-An-indirect-operand Prefixed 9 18 QI)
(src32-An-indirect-operand Prefixed 9 18 HI)
(src32-An-indirect-operand Prefixed 9 18 SI)
;-------------------------------------------------------------
; dsp:d[r] relative
;-------------------------------------------------------------
(define-pmacro (src16-relative-operand xmode)
(begin
(define-derived-operand
(name (.sym src16-16-8-SB-relative- xmode))
(comment (.str "m16c dsp:8[sb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dsp-16-u8))
(syntax "${Dsp-16-u8}[sb]")
(base-ifield f-8-4)
(encoding (+ (f-8-4 #xA) Dsp-16-u8))
(ifield-assertion (eq f-8-4 #xA))
(getter (mem16 xmode (add Dsp-16-u8 (reg h-sb))))
(setter (set (mem16 xmode (add Dsp-16-u8 (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym src16-16-16-SB-relative- xmode))
(comment (.str "m16c dsp:16[sb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dsp-16-u16))
(syntax "${Dsp-16-u16}[sb]")
(base-ifield f-8-4)
(encoding (+ (f-8-4 #xE) Dsp-16-u16))
(ifield-assertion (eq f-8-4 #xE))
(getter (mem16 xmode (add Dsp-16-u16 (reg h-sb))))
(setter (set (mem16 xmode (add Dsp-16-u16 (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym src16-16-8-FB-relative- xmode))
(comment (.str "m16c dsp:8[fb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dsp-16-s8))
(syntax "${Dsp-16-s8}[fb]")
(base-ifield f-8-4)
(encoding (+ (f-8-4 #xB) Dsp-16-s8))
(ifield-assertion (eq f-8-4 #xB))
(getter (mem16 xmode (add Dsp-16-s8 (reg h-fb))))
(setter (set (mem16 xmode (add Dsp-16-s8 (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym src16-16-8-An-relative- xmode))
(comment (.str "m16c dsp:8[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Src16An Dsp-16-u8))
(syntax "${Dsp-16-u8}[$Src16An]")
(base-ifield f-8-4)
(encoding (+ (f-8-2 2) (f-10-1 0) Dsp-16-u8 Src16An))
(ifield-assertion (andif (eq f-8-2 2) (eq f-10-1 0)))
(getter (mem16 xmode (add Dsp-16-u8 Src16An)))
(setter (set (mem16 xmode (add Dsp-16-u8 Src16An)) newval))
)
(define-derived-operand
(name (.sym src16-16-16-An-relative- xmode))
(comment (.str "m16c dsp:16[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Src16An Dsp-16-u16))
(syntax "${Dsp-16-u16}[$Src16An]")
(base-ifield f-8-4)
(encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u16 Src16An))
(ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0)))
(getter (mem16 xmode (add Dsp-16-u16 Src16An)))
(setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval))
)
(define-derived-operand
(name (.sym src16-16-20-An-relative- xmode))
(comment (.str "m16c dsp:20[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Src16An Dsp-16-u20))
(syntax "${Dsp-16-u20}[$Src16An]")
(base-ifield f-8-4)
(encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An))
(ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0)))
(getter (mem20 xmode (add Dsp-16-u20 Src16An)))
(setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval))
)
)
)
(src16-relative-operand QI)
(src16-relative-operand HI)
(define-pmacro (src32-relative-operand offset group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym src32- offset -8-SB-relative- group - xmode))
(comment (.str "m32c dsp:8[sb] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[sb]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
(getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u8)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u8)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym src32- offset -16-SB-relative- group - xmode))
(comment (.str "m32c dsp:16[sb] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[sb]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
(getter (c-call xmode (.str "operand_getter_" xmode) sb (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval sb (.sym Dsp- offset -u16)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym src32- offset -8-FB-relative- group - xmode))
(comment (.str "m32c dsp:8[fb] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -s8)))
(syntax (.str "${Dsp-" offset "-s8}[fb]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
(getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s8)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s8)))
; (getter (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym src32- offset -16-FB-relative- group - xmode))
(comment (.str "m32c dsp:16[fb] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -s16)))
(syntax (.str "${Dsp-" offset "-s16}[fb]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
(getter (c-call xmode (.str "operand_getter_" xmode) fb (.sym Dsp- offset -s16)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval fb (.sym Dsp- offset -s16)))
; (getter (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym src32- offset -8-An-relative- group - xmode))
(comment (.str "m32c dsp:8[An] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group) (.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[$Src32An" group "]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Src32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
(getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u8)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u8)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u8) (.sym Src32An group))) newval))
)
(define-derived-operand
(name (.sym src32- offset -16-An-relative- group - xmode))
(comment (.str "m32c dsp:16[An] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group) (.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[$Src32An" group "]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Src32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
(getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u16)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u16) (.sym Src32An group))) newval))
)
(define-derived-operand
(name (.sym src32- offset -24-An-relative- group - xmode))
(comment (.str "m32c dsp:16[An] relative destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Src32An group) (.sym Dsp- offset -u24)))
(syntax (.str "${Dsp-" offset "-u24}[$Src32An" group "]"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Src32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
(getter (c-call xmode (.str "operand_getter_" xmode) (.sym Src32An group) (.sym Dsp- offset -u24) ))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (.sym Src32An group) (.sym Dsp- offset -u24)))
; (getter (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))))
; (setter (set (mem32 xmode (add (.sym Dsp- offset -u24) (.sym Src32An group))) newval))
)
)
)
(src32-relative-operand 16 Unprefixed 1 10 QI)
(src32-relative-operand 16 Unprefixed 1 10 HI)
(src32-relative-operand 16 Unprefixed 1 10 SI)
(src32-relative-operand 24 Prefixed 9 18 QI)
(src32-relative-operand 24 Prefixed 9 18 HI)
(src32-relative-operand 24 Prefixed 9 18 SI)
;-------------------------------------------------------------
; Absolute address
;-------------------------------------------------------------
(define-pmacro (src16-absolute xmode)
(begin
(define-derived-operand
(name (.sym src16-16-16-absolute- xmode))
(comment (.str "m16c absolute address " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dsp-16-u16))
(syntax (.str "${Dsp-16-u16}"))
(base-ifield f-8-4)
(encoding (+ (f-8-4 #xF) Dsp-16-u16))
(ifield-assertion (eq f-8-4 #xF))
(getter (mem16 xmode Dsp-16-u16))
(setter (set (mem16 xmode Dsp-16-u16) newval))
)
)
)
(src16-absolute QI)
(src16-absolute HI)
(define-pmacro (src32-absolute offset group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym src32- offset -16-absolute- group - xmode))
(comment (.str "m32c absolute address " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
(getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u16)))
; (getter (mem32 xmode (.sym Dsp- offset -u16)))
; (setter (set (mem32 xmode (.sym Dsp- offset -u16)) newval))
)
(define-derived-operand
(name (.sym src32- offset -24-absolute- group - xmode))
(comment (.str "m32c absolute address " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dsp- offset -u24)))
(syntax (.str "${Dsp-" offset "-u24}"))
(base-ifield (.sym f- base1 -11))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
(getter (c-call xmode (.str "operand_getter_" xmode) (const 0) (.sym Dsp- offset -u24)))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) (.sym Dsp- offset -u24)))
; (getter (mem32 xmode (.sym Dsp- offset -u24)))
; (setter (set (mem32 xmode (.sym Dsp- offset -u24)) newval))
)
)
)
(src32-absolute 16 Unprefixed 1 10 QI)
(src32-absolute 16 Unprefixed 1 10 HI)
(src32-absolute 16 Unprefixed 1 10 SI)
(src32-absolute 24 Prefixed 9 18 QI)
(src32-absolute 24 Prefixed 9 18 HI)
(src32-absolute 24 Prefixed 9 18 SI)
;-------------------------------------------------------------
; An indirect indirect
;
; Double indirect addressing uses the lower 3 bytes of the value stored
; at the address referenced by 'op' as the effective address.
;-------------------------------------------------------------
(define-pmacro (indirect-addr op) (and USI (mem32 USI op) #x00ffffff))
; (define-pmacro (src-An-indirect-indirect-operand xmode)
; (define-derived-operand
; (name (.sym src32-An-indirect-indirect- xmode))
; (comment (.str "m32c An indirect indirect destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Src32AnPrefixed))
; (syntax (.str "[[$Src32AnPrefixed]]"))
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 0) (f-18-1 0) Src32AnPrefixed))
; (ifield-assertion (andif (eq f-9-3 0) (eq f-18-1 0)))
; (getter (mem32 xmode (indirect-addr Src32AnPrefixed)))
; (setter (set (mem32 xmode (indirect-addr Src32AnPrefixed)) newval))
; )
; )
; (src-An-indirect-indirect-operand QI)
; (src-An-indirect-indirect-operand HI)
; (src-An-indirect-indirect-operand SI)
;-------------------------------------------------------------
; Relative indirect
;-------------------------------------------------------------
(define-pmacro (src-relative-indirect-operand xmode)
(begin
; (define-derived-operand
; (name (.sym src32-24-8-SB-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[sb] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-24-u8))
; (syntax "[${Dsp-24-u8}[sb]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 1) (f-18-2 2) Dsp-24-u8))
; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 2)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 (reg h-sb)))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-16-SB-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[sb] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-24-u16))
; (syntax "[${Dsp-24-u16}[sb]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 2) (f-18-2 2) Dsp-24-u16))
; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 2)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 (reg h-sb)))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-8-FB-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[fb] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-24-s8))
; (syntax "[${Dsp-24-s8}[fb]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 1) (f-18-2 3) Dsp-24-s8))
; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-2 3)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s8 (reg h-fb)))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-16-FB-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[fb] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dsp-24-s16))
; (syntax "[${Dsp-24-s16}[fb]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 2) (f-18-2 3) Dsp-24-s16))
; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-2 3)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-s16 (reg h-fb)))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-8-An-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[An] relative indirect source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Src32AnPrefixed Dsp-24-u8))
; (syntax "[${Dsp-24-u8}[$Src32AnPrefixed]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 1) (f-18-1 0) Dsp-24-u8 Src32AnPrefixed))
; (ifield-assertion (andif (eq f-9-3 1) (eq f-18-1 0)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u8 Src32AnPrefixed))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-16-An-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[An] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Src32AnPrefixed Dsp-24-u16))
; (syntax "[${Dsp-24-u16}[$Src32AnPrefixed]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 2) (f-18-1 0) Dsp-24-u16 Src32AnPrefixed))
; (ifield-assertion (andif (eq f-9-3 2) (eq f-18-1 0)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u16 Src32AnPrefixed))) newval))
; )
; (define-derived-operand
; (name (.sym src32-24-24-An-relative-indirect- xmode))
; (comment (.str "m32c dsp:24[An] relative source " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Src32AnPrefixed Dsp-24-u24))
; (syntax "[${Dsp-24-u24}[$Src32AnPrefixed]]")
; (base-ifield f-9-11)
; (encoding (+ (f-9-3 3) (f-18-1 0) Dsp-24-u24 Src32AnPrefixed))
; (ifield-assertion (andif (eq f-9-3 3) (eq f-18-1 0)))
; (getter (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))))
; (setter (set (mem32 xmode (indirect-addr (add Dsp-24-u24 Src32AnPrefixed))) newval))
; )
)
)
; (src-relative-indirect-operand QI)
; (src-relative-indirect-operand HI)
; (src-relative-indirect-operand SI)
;-------------------------------------------------------------
; Absolute Indirect address
;-------------------------------------------------------------
(define-pmacro (src32-absolute-indirect offset base1 base2 xmode)
(begin
; (define-derived-operand
; (name (.sym src32- offset -16-absolute-indirect-derived- xmode))
; (comment (.str "m32c absolute indirect address " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u16)))
; (syntax (.str "[${Dsp-" offset "-u16}]"))
; (base-ifield (.sym f- base1 -11))
; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))))
; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u16))) newval))
; )
; (define-derived-operand
; (name (.sym src32- offset -24-absolute-indirect-derived- xmode))
; (comment (.str "m32c absolute indirect address " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u24)))
; (syntax (.str "[${Dsp-" offset "-u24}]"))
; (base-ifield (.sym f- base1 -11))
; (encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
; (ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
; (getter (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))))
; (setter (set (mem32 xmode (indirect-addr (.sym Dsp- offset -u24))) newval))
; )
)
)
(src32-absolute-indirect 24 9 18 QI)
(src32-absolute-indirect 24 9 18 HI)
(src32-absolute-indirect 24 9 18 SI)
;-------------------------------------------------------------
; Register relative source operands for short format insns
;-------------------------------------------------------------
(define-pmacro (src-2-S-operands mach xmode base opc1 opc2 opc3)
(begin
(define-derived-operand
(name (.sym src mach -2-S-8-SB-relative- xmode))
(comment (.str "m" mach "c SB relative address"))
(attrs (machine mach))
(mode xmode)
(args (Dsp-8-u8))
(syntax "${Dsp-8-u8}[sb]")
(base-ifield (.sym f- base -2))
(encoding (+ ((.sym f- base -2) opc1) Dsp-8-u8))
(ifield-assertion (eq (.sym f- base -2) opc1))
(getter (c-call xmode (.str "operand_getter_" xmode) sb Dsp-8-u8))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval sb Dsp-8-u8))
; (getter (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))))
; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-sb) Dsp-8-u8))) newval))
)
(define-derived-operand
(name (.sym src mach -2-S-8-FB-relative- xmode))
(comment (.str "m" mach "c FB relative address"))
(attrs (machine mach))
(mode xmode)
(args (Dsp-8-s8))
(syntax "${Dsp-8-s8}[fb]")
(base-ifield (.sym f- base -2))
(encoding (+ ((.sym f- base -2) opc2) Dsp-8-s8))
(ifield-assertion (eq (.sym f- base -2) opc2))
(getter (c-call xmode (.str "operand_getter_" xmode) fb Dsp-8-s8))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval fb Dsp-8-s8))
; (getter (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))))
; (setter (set (mem-mach mach xmode (indirect-addr (add (reg h-fb) Dsp-8-s8))) newval))
)
(define-derived-operand
(name (.sym src mach -2-S-16-absolute- xmode))
(comment (.str "m" mach "c absolute address"))
(attrs (machine mach))
(mode xmode)
(args (Dsp-8-u16))
(syntax "${Dsp-8-u16}")
(base-ifield (.sym f- base -2))
(encoding (+ ((.sym f- base -2) opc3) Dsp-8-u16))
(ifield-assertion (eq (.sym f- base -2) opc3))
(getter (c-call xmode (.str "operand_getter_" xmode) (const 0) Dsp-8-u16))
(setter (c-call DFLT (.str "operand_setter_" xmode) newval (const 0) Dsp-8-u16))
; (getter (mem-mach mach xmode Dsp-8-u16))
; (setter (set (mem-mach mach xmode Dsp-8-u16) newval))
)
)
)
(src-2-S-operands 16 QI 6 1 2 3)
(src-2-S-operands 32 QI 2 2 3 1)
(src-2-S-operands 32 HI 2 2 3 1)
;=============================================================
; Derived Operands
;-------------------------------------------------------------
; Destination
;-------------------------------------------------------------
; Rn direct
;-------------------------------------------------------------
(define-pmacro (dst16-Rn-direct-operand xmode)
(begin
(define-derived-operand
(name (.sym dst16-Rn-direct- xmode))
(comment (.str "m16c Rn direct destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dst16Rn xmode)))
(syntax (.str "$Dst16Rn" xmode))
(base-ifield f-12-4)
(encoding (+ (f-12-2 0) (.sym Dst16Rn xmode)))
(ifield-assertion (eq f-12-2 0))
(getter (trunc xmode (.sym Dst16Rn xmode)))
(setter (set (.sym Dst16Rn xmode) newval))
)
)
)
(dst16-Rn-direct-operand QI)
(dst16-Rn-direct-operand HI)
(dst16-Rn-direct-operand SI)
(define-derived-operand
(name dst16-Rn-direct-Ext-QI)
(comment "m16c Rn direct destination QI")
(attrs (machine 16))
(mode HI)
(args (Dst16RnExtQI))
(syntax "$Dst16RnExtQI")
(base-ifield f-12-4)
(encoding (+ (f-12-2 0) Dst16RnExtQI (f-15-1 0)))
(ifield-assertion (andif (eq f-12-2 0) (eq f-15-1 0)))
(getter (trunc QI (.sym Dst16RnExtQI)))
(setter (set Dst16RnExtQI newval))
)
(define-pmacro (dst32-Rn-direct-operand group base xmode)
(begin
(define-derived-operand
(name (.sym dst32-Rn-direct- group - xmode))
(comment (.str "m32c Rn direct destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dst32Rn group xmode)))
(syntax (.str "$Dst32Rn" group xmode))
(base-ifield (.sym f- base -6))
(encoding (+ ((.sym f- base -3) 4) (.sym Dst32Rn group xmode)))
(ifield-assertion (eq (.sym f- base -3) 4))
(getter (trunc xmode (.sym Dst32Rn group xmode)))
(setter (set (.sym Dst32Rn group xmode) newval))
)
)
)
(dst32-Rn-direct-operand Unprefixed 4 QI)
(dst32-Rn-direct-operand Prefixed 12 QI)
(dst32-Rn-direct-operand Unprefixed 4 HI)
(dst32-Rn-direct-operand Prefixed 12 HI)
(dst32-Rn-direct-operand Unprefixed 4 SI)
(dst32-Rn-direct-operand Prefixed 12 SI)
(define-pmacro (dst32-Rn-direct-Ext-operand group base1 base2 smode dmode)
(begin
(define-derived-operand
(name (.sym dst32-Rn-direct- group - smode))
(comment (.str "m32c Rn direct destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32Rn group smode)))
(syntax (.str "$Dst32Rn" group smode))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 4) ((.sym f- base2 -1) 1) (.sym Dst32Rn group smode)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 4) (eq (.sym f- base2 -1) 1)))
(getter (trunc smode (.sym Dst32Rn group smode)))
(setter (set (.sym Dst32Rn group smode) newval))
)
)
)
(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 QI HI)
(dst32-Rn-direct-Ext-operand ExtUnprefixed 4 8 HI SI)
(define-derived-operand
(name dst32-R3-direct-Unprefixed-HI)
(comment "m32c R3 direct HI")
(attrs (machine 32))
(mode HI)
(args (R3))
(syntax "$R3")
(base-ifield f-4-6)
(encoding (+ (f-4-3 4) (f-8-2 #x1)))
(ifield-assertion (andif (eq f-4-3 4) (eq f-8-2 #x1)))
(getter (trunc HI R3))
(setter (set R3 newval))
)
;-------------------------------------------------------------
; An direct
;-------------------------------------------------------------
(define-pmacro (dst16-An-direct-operand xmode)
(begin
(define-derived-operand
(name (.sym dst16-An-direct- xmode))
(comment (.str "m16c An direct destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dst16An xmode)))
(syntax (.str "$Dst16An" xmode))
(base-ifield f-12-4)
(encoding (+ (f-12-2 1) (f-14-1 0) (.sym Dst16An xmode)))
(ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 0)))
(getter (trunc xmode (.sym Dst16An xmode)))
(setter (set (.sym Dst16An xmode) newval))
)
)
)
(dst16-An-direct-operand QI)
(dst16-An-direct-operand HI)
(dst16-An-direct-operand SI)
(define-pmacro (dst32-An-direct-operand group base1 base2 xmode)
(begin
(define-derived-operand
(name (.sym dst32-An-direct- group - xmode))
(comment (.str "m32c An direct destination " xmode))
(attrs (machine 32))
(mode xmode)
(args ((.sym Dst32An group xmode)))
(syntax (.str "$Dst32An" group xmode))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 1) (.sym Dst32An group xmode)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 1)))
(getter (trunc xmode (.sym Dst32An group xmode)))
(setter (set (.sym Dst32An group xmode) newval))
)
)
)
(dst32-An-direct-operand Unprefixed 4 8 QI)
(dst32-An-direct-operand Prefixed 12 16 QI)
(dst32-An-direct-operand Unprefixed 4 8 HI)
(dst32-An-direct-operand Prefixed 12 16 HI)
(dst32-An-direct-operand Unprefixed 4 8 SI)
(dst32-An-direct-operand Prefixed 12 16 SI)
;-------------------------------------------------------------
; An indirect
;-------------------------------------------------------------
(define-pmacro (dst16-An-indirect-operand xmode)
(begin
(define-derived-operand
(name (.sym dst16-An-indirect- xmode))
(comment (.str "m16c An indirect destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dst16An))
(syntax "[$Dst16An]")
(base-ifield f-12-4)
(encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
(ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
(getter (mem16 xmode Dst16An))
(setter (set (mem16 xmode Dst16An) newval))
)
)
)
(dst16-An-indirect-operand QI)
(dst16-An-indirect-operand HI)
(dst16-An-indirect-operand SI)
(define-derived-operand
(name dst16-An-indirect-Ext-QI)
(comment "m16c An indirect destination QI")
(attrs (machine 16))
(mode HI)
(args (Dst16An))
(syntax "[$Dst16An]")
(base-ifield f-12-4)
(encoding (+ (f-12-2 1) (f-14-1 1) Dst16An))
(ifield-assertion (andif (eq f-12-2 1) (eq f-14-1 1)))
(getter (mem16 QI Dst16An))
(setter (set (mem16 HI Dst16An) newval))
)
(define-pmacro (dst32-An-indirect-operand group base1 base2 smode dmode)
(begin
(define-derived-operand
(name (.sym dst32-An-indirect- group - smode))
(comment (.str "m32c An indirect destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32An group)))
(syntax (.str "[$Dst32An" group "]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 0) ((.sym f- base2 -1) 0) (.sym Dst32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 0) (eq (.sym f- base2 -1) 0)))
(getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group)
(const 0)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval
(.sym Dst32An group) (const 0)))
; (getter (mem32 smode (.sym Dst32An group)))
; (setter (set (mem32 dmode (.sym Dst32An group)) newval))
)
)
)
(dst32-An-indirect-operand Unprefixed 4 8 QI QI)
(dst32-An-indirect-operand Prefixed 12 16 QI QI)
(dst32-An-indirect-operand Unprefixed 4 8 HI HI)
(dst32-An-indirect-operand Prefixed 12 16 HI HI)
(dst32-An-indirect-operand Unprefixed 4 8 SI SI)
(dst32-An-indirect-operand Prefixed 12 16 SI SI)
(dst32-An-indirect-operand ExtUnprefixed 4 8 QI HI)
(dst32-An-indirect-operand ExtUnprefixed 4 8 HI SI)
;-------------------------------------------------------------
; dsp:d[r] relative
;-------------------------------------------------------------
(define-pmacro (dst16-relative-operand offset xmode)
(begin
(define-derived-operand
(name (.sym dst16- offset -8-SB-relative- xmode))
(comment (.str "m16c dsp:8[sb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
(ifield-assertion (eq f-12-4 #xA))
(getter (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))))
(setter (set (mem16 xmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -16-SB-relative- xmode))
(comment (.str "m16c dsp:16[sb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
(ifield-assertion (eq f-12-4 #xE))
(getter (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))))
(setter (set (mem16 xmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -8-FB-relative- xmode))
(comment (.str "m16c dsp:8[fb] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dsp- offset -s8)))
(syntax (.str "${Dsp-" offset "-s8}[fb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
(ifield-assertion (eq f-12-4 #xB))
(getter (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))))
(setter (set (mem16 xmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -8-An-relative- xmode))
(comment (.str "m16c dsp:8[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dst16An (.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
(ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
(getter (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)))
(setter (set (mem16 xmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
)
(define-derived-operand
(name (.sym dst16- offset -16-An-relative- xmode))
(comment (.str "m16c dsp:16[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dst16An (.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
(ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
(getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)))
(setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
)
(define-derived-operand
(name (.sym dst16- offset -20-An-relative- xmode))
(comment (.str "m16c dsp:20[An] relative destination " xmode))
(attrs (machine 16))
(mode xmode)
(args (Dst16An (.sym Dsp- offset -u20)))
(syntax (.str "${Dsp-" offset "-u20}[$Dst16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An))
(ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
(getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)))
(setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval))
)
)
)
(dst16-relative-operand 16 QI)
(dst16-relative-operand 24 QI)
(dst16-relative-operand 32 QI)
(dst16-relative-operand 40 QI)
(dst16-relative-operand 48 QI)
(dst16-relative-operand 16 HI)
(dst16-relative-operand 24 HI)
(dst16-relative-operand 32 HI)
(dst16-relative-operand 40 HI)
(dst16-relative-operand 48 HI)
(dst16-relative-operand 16 SI)
(dst16-relative-operand 24 SI)
(dst16-relative-operand 32 SI)
(dst16-relative-operand 40 SI)
(dst16-relative-operand 48 SI)
(define-pmacro (dst16-relative-Ext-operand offset smode dmode)
(begin
(define-derived-operand
(name (.sym dst16- offset -8-SB-relative-Ext- smode))
(comment (.str "m16c dsp:8[sb] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args ((.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xA) (.sym Dsp- offset -u8)))
(ifield-assertion (eq f-12-4 #xA))
(getter (mem16 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
(setter (set (mem16 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -16-SB-relative-Ext- smode))
(comment (.str "m16c dsp:16[sb] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[sb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xE) (.sym Dsp- offset -u16)))
(ifield-assertion (eq f-12-4 #xE))
(getter (mem16 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
(setter (set (mem16 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -8-FB-relative-Ext- smode))
(comment (.str "m16c dsp:8[fb] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args ((.sym Dsp- offset -s8)))
(syntax (.str "${Dsp-" offset "-s8}[fb]"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xB) (.sym Dsp- offset -s8)))
(ifield-assertion (eq f-12-4 #xB))
(getter (mem16 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
(setter (set (mem16 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym dst16- offset -8-An-relative-Ext- smode))
(comment (.str "m16c dsp:8[An] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args (Dst16An (.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[$Dst16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 2) (f-14-1 0) (.sym Dsp- offset -u8) Dst16An))
(ifield-assertion (andif (eq f-12-2 2) (eq f-14-1 0)))
(getter (mem16 smode (add (.sym Dsp- offset -u8) Dst16An)))
(setter (set (mem16 dmode (add (.sym Dsp- offset -u8) Dst16An)) newval))
)
(define-derived-operand
(name (.sym dst16- offset -16-An-relative-Ext- smode))
(comment (.str "m16c dsp:16[An] relative destination " smode))
(attrs (machine 16))
(mode dmode)
(args (Dst16An (.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[$Dst16An]"))
(base-ifield f-12-4)
(encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u16) Dst16An))
(ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0)))
(getter (mem16 smode (add (.sym Dsp- offset -u16) Dst16An)))
(setter (set (mem16 dmode (add (.sym Dsp- offset -u16) Dst16An)) newval))
)
)
)
(dst16-relative-Ext-operand 16 QI HI)
(define-pmacro (dst32-relative-operand offset group base1 base2 smode dmode)
(begin
(define-derived-operand
(name (.sym dst32- offset -8-SB-relative- group - smode))
(comment (.str "m32c dsp:8[sb] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[sb]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u8)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 2)))
(getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u8)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u8)))
; (getter (mem32 smode (add (.sym Dsp- offset -u8) (reg h-sb))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -16-SB-relative- group - smode))
(comment (.str "m32c dsp:16[sb] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[sb]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 2)))
(getter (c-call dmode (.str "operand_getter_" dmode) sb (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval sb (.sym Dsp- offset -u16)))
; (getter (mem32 smode (add (.sym Dsp- offset -u16) (reg h-sb))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (reg h-sb))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -8-FB-relative- group - smode))
(comment (.str "m32c dsp:8[fb] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -s8)))
(syntax (.str "${Dsp-" offset "-s8}[fb]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s8)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -2) 3)))
(getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s8)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s8)))
; (getter (mem32 smode (add (.sym Dsp- offset -s8) (reg h-fb))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -s8) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -16-FB-relative- group - smode))
(comment (.str "m32c dsp:16[fb] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -s16)))
(syntax (.str "${Dsp-" offset "-s16}[fb]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -2) 3) (.sym Dsp- offset -s16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -2) 3)))
(getter (c-call dmode (.str "operand_getter_" dmode) fb (.sym Dsp- offset -s16)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval fb (.sym Dsp- offset -s16)))
; (getter (mem32 smode (add (.sym Dsp- offset -s16) (reg h-fb))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -s16) (reg h-fb))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -8-An-relative- group - smode))
(comment (.str "m32c dsp:8[An] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32An group) (.sym Dsp- offset -u8)))
(syntax (.str "${Dsp-" offset "-u8}[$Dst32An" group "]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 1) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u8) (.sym Dst32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 1) (eq (.sym f- base2 -1) 0)))
(getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u8)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u8)))
; (getter (mem32 smode (add (.sym Dsp- offset -u8) (.sym Dst32An group))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u8) (.sym Dst32An group))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -16-An-relative- group - smode))
(comment (.str "m32c dsp:16[An] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32An group) (.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}[$Dst32An" group "]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 2) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u16) (.sym Dst32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 2) (eq (.sym f- base2 -1) 0)))
(getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u16)))
; (getter (mem32 smode (add (.sym Dsp- offset -u16) (.sym Dst32An group))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u16) (.sym Dst32An group))) newval))
)
(define-derived-operand
(name (.sym dst32- offset -24-An-relative- group - smode))
(comment (.str "m32c dsp:16[An] relative destination " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dst32An group) (.sym Dsp- offset -u24)))
(syntax (.str "${Dsp-" offset "-u24}[$Dst32An" group "]"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -1) 0) (.sym Dsp- offset -u24) (.sym Dst32An group)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -1) 0)))
(getter (c-call dmode (.str "operand_getter_" dmode) (.sym Dst32An group) (.sym Dsp- offset -u24)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (.sym Dst32An group) (.sym Dsp- offset -u24)))
; (getter (mem32 smode (add (.sym Dsp- offset -u24) (.sym Dst32An group))))
; (setter (set (mem32 dmode (add (.sym Dsp- offset -u24) (.sym Dst32An group))) newval))
)
)
)
(dst32-relative-operand 16 Unprefixed 4 8 QI QI)
(dst32-relative-operand 24 Unprefixed 4 8 QI QI)
(dst32-relative-operand 32 Unprefixed 4 8 QI QI)
(dst32-relative-operand 40 Unprefixed 4 8 QI QI)
(dst32-relative-operand 16 Unprefixed 4 8 HI HI)
(dst32-relative-operand 24 Unprefixed 4 8 HI HI)
(dst32-relative-operand 32 Unprefixed 4 8 HI HI)
(dst32-relative-operand 40 Unprefixed 4 8 HI HI)
(dst32-relative-operand 16 Unprefixed 4 8 SI SI)
(dst32-relative-operand 24 Unprefixed 4 8 SI SI)
(dst32-relative-operand 32 Unprefixed 4 8 SI SI)
(dst32-relative-operand 40 Unprefixed 4 8 SI SI)
(dst32-relative-operand 24 Prefixed 12 16 QI QI)
(dst32-relative-operand 32 Prefixed 12 16 QI QI)
(dst32-relative-operand 40 Prefixed 12 16 QI QI)
(dst32-relative-operand 48 Prefixed 12 16 QI QI)
(dst32-relative-operand 24 Prefixed 12 16 HI HI)
(dst32-relative-operand 32 Prefixed 12 16 HI HI)
(dst32-relative-operand 40 Prefixed 12 16 HI HI)
(dst32-relative-operand 48 Prefixed 12 16 HI HI)
(dst32-relative-operand 24 Prefixed 12 16 SI SI)
(dst32-relative-operand 32 Prefixed 12 16 SI SI)
(dst32-relative-operand 40 Prefixed 12 16 SI SI)
(dst32-relative-operand 48 Prefixed 12 16 SI SI)
(dst32-relative-operand 16 ExtUnprefixed 4 8 QI HI)
(dst32-relative-operand 16 ExtUnprefixed 4 8 HI SI)
;-------------------------------------------------------------
; Absolute address
;-------------------------------------------------------------
(define-pmacro (dst16-absolute offset xmode)
(begin
(define-derived-operand
(name (.sym dst16- offset -16-absolute- xmode))
(comment (.str "m16c absolute address " xmode))
(attrs (machine 16))
(mode xmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}"))
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xF) (.sym Dsp- offset -u16)))
(ifield-assertion (eq f-12-4 #xF))
(getter (mem16 xmode (.sym Dsp- offset -u16)))
(setter (set (mem16 xmode (.sym Dsp- offset -u16)) newval))
)
)
)
(dst16-absolute 16 QI)
(dst16-absolute 24 QI)
(dst16-absolute 32 QI)
(dst16-absolute 40 QI)
(dst16-absolute 48 QI)
(dst16-absolute 16 HI)
(dst16-absolute 24 HI)
(dst16-absolute 32 HI)
(dst16-absolute 40 HI)
(dst16-absolute 48 HI)
(dst16-absolute 16 SI)
(dst16-absolute 24 SI)
(dst16-absolute 32 SI)
(dst16-absolute 40 SI)
(dst16-absolute 48 SI)
(define-derived-operand
(name dst16-16-16-absolute-Ext-QI)
(comment "m16c absolute address QI")
(attrs (machine 16))
(mode HI)
(args (Dsp-16-u16))
(syntax "${Dsp-16-u16}")
(base-ifield f-12-4)
(encoding (+ (f-12-4 #xF) Dsp-16-u16))
(ifield-assertion (eq f-12-4 #xF))
(getter (mem16 QI Dsp-16-u16))
(setter (set (mem16 HI Dsp-16-u16) newval))
)
(define-pmacro (dst32-absolute offset group base1 base2 smode dmode)
(begin
(define-derived-operand
(name (.sym dst32- offset -16-absolute- group - smode))
(comment (.str "m32c absolute address " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -u16)))
(syntax (.str "${Dsp-" offset "-u16}"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 3) (.sym Dsp- offset -u16)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 3)))
(getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u16)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u16)))
; (getter (mem32 smode (.sym Dsp- offset -u16)))
; (setter (set (mem32 dmode (.sym Dsp- offset -u16)) newval))
)
(define-derived-operand
(name (.sym dst32- offset -24-absolute- group - smode))
(comment (.str "m32c absolute address " smode))
(attrs (machine 32))
(mode dmode)
(args ((.sym Dsp- offset -u24)))
(syntax (.str "${Dsp-" offset "-u24}"))
(base-ifield (.sym f- base1 -6))
(encoding (+ ((.sym f- base1 -3) 3) ((.sym f- base2 -2) 2) (.sym Dsp- offset -u24)))
(ifield-assertion (andif (eq (.sym f- base1 -3) 3) (eq (.sym f- base2 -2) 2)))
(getter (c-call smode (.str "operand_getter_" smode) (const 0) (.sym Dsp- offset -u24)))
(setter (c-call DFLT (.str "operand_setter_" dmode) newval (const 0) (.sym Dsp- offset -u24)))
; (getter (mem32 smode (.sym Dsp- offset -u24)))
; (setter (set (mem32 dmode (.sym Dsp- offset -u24)) newval))
)
)
)
(dst32-absolute 16 Unprefixed 4 8 QI QI)
(dst32-absolute 24 Unprefixed 4 8 QI QI)
(dst32-absolute 32 Unprefixed 4 8 QI QI)
(dst32-absolute 40 Unprefixed 4 8 QI QI)
(dst32-absolute 16 Unprefixed 4 8 HI HI)
(dst32-absolute 24 Unprefixed 4 8 HI HI)
(dst32-absolute 32 Unprefixed 4 8 HI HI)
(dst32-absolute 40 Unprefixed 4 8 HI HI)
(dst32-absolute 16 Unprefixed 4 8 SI SI)
(dst32-absolute 24 Unprefixed 4 8 SI SI)
(dst32-absolute 32 Unprefixed 4 8 SI SI)
(dst32-absolute 40 Unprefixed 4 8 SI SI)
(dst32-absolute 24 Prefixed 12 16 QI QI)
(dst32-absolute 32 Prefixed 12 16 QI QI)
(dst32-absolute 40 Prefixed 12 16 QI QI)
(dst32-absolute 48 Prefixed 12 16 QI QI)
(dst32-absolute 24 Prefixed 12 16 HI HI)
(dst32-absolute 32 Prefixed 12 16 HI HI)
(dst32-absolute 40 Prefixed 12 16 HI HI)
(dst32-absolute 48 Prefixed 12 16 HI HI)
(dst32-absolute 24 Prefixed 12 16 SI SI)
(dst32-absolute 32 Prefixed 12 16 SI SI)
(dst32-absolute 40 Prefixed 12 16 SI SI)
(dst32-absolute 48 Prefixed 12 16 SI SI)
(dst32-absolute 16 ExtUnprefixed 4 8 QI HI)
(dst32-absolute 16 ExtUnprefixed 4 8 HI SI)
;-------------------------------------------------------------
; An indirect indirect
;-------------------------------------------------------------
;(define-pmacro (dst-An-indirect-indirect-operand xmode)
; (define-derived-operand
; (name (.sym dst32-An-indirect-indirect- xmode))
; (comment (.str "m32c An indirect indirect destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args (Dst32AnPrefixed))
; (syntax (.str "[[$Dst32AnPrefixed]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 0) (f-16-1 0) Dst32AnPrefixed))
; (ifield-assertion (andif (eq f-12-3 0) (eq f-16-1 0)))
; (getter (mem32 xmode (indirect-addr Dst32AnPrefixed)))
; (setter (set (mem32 xmode (indirect-addr Dst32AnPrefixed)) newval))
; )
;)
; (dst-An-indirect-indirect-operand QI)
; (dst-An-indirect-indirect-operand HI)
; (dst-An-indirect-indirect-operand SI)
;-------------------------------------------------------------
; Relative indirect
;-------------------------------------------------------------
(define-pmacro (dst-relative-indirect-operand offset xmode)
(begin
; (define-derived-operand
; (name (.sym dst32- offset -8-SB-relative-indirect- xmode))
; (comment (.str "m32c dsp:8[sb] relative destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u8)))
; (syntax (.str "[${Dsp-" offset "-u8}[sb]]"))
; (base-ifield f-12-6)
; (encoding (+ (f-12-3 1) (f-16-2 2) (.sym Dsp- offset -u8)))
; (ifield-assertion (andif (eq f-12-3 1) (eq f-16-2 2)))
; (getter (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))))
; (setter (set (mem32 xmode (indirect-addr (add (.sym Dsp- offset -u8) (reg h-sb)))) newval))
; )
; (define-derived-operand
; (name (.sym dst32- offset -16-SB-relative-indirect- xmode))
; (comment (.str "m32c dsp:16[sb] relative destination " xmode))
; (attrs (machine 32))
; (mode xmode)
; (args ((.sym Dsp- offset -u16)))
; (syntax (.str "[${Dsp-" offset "-u16}[sb]]"))
; (base-ifield f-12-6)