diff --git a/MANIFEST b/MANIFEST
new file mode 100644
index 0000000..1e876de
--- /dev/null
+++ b/MANIFEST
@@ -0,0 +1,249 @@
+By codito
+ added files:
+  gas/testsuite/gas/arc/general_a700.d
+  gas/testsuite/gas/arc/dsp1.d
+  gas/testsuite/gas/arc/general_a700.s
+  gas/testsuite/gas/arc/dsp1.s
+  gas/testsuite/gas/arc/ld_arc700.s
+  gas/testsuite/gas/arc/sub_s.d
+  gas/testsuite/gas/arc/lsl_s.d
+  gas/testsuite/gas/arc/gen_simd.d
+  gas/testsuite/gas/arc/sub_s.s
+  gas/testsuite/gas/arc/lsl_s.s
+  gas/testsuite/gas/arc/prefetch.d
+  gas/testsuite/gas/arc/gen_simd.s
+  gas/testsuite/gas/arc/reloctest.d
+  gas/testsuite/gas/arc/arc700.exp
+  gas/testsuite/gas/arc/dsp2.d
+  gas/testsuite/gas/arc/prefetch.s
+  gas/testsuite/gas/arc/reloctest.s
+  gas/testsuite/gas/arc/dsp2.s
+  gas/testsuite/gas/arc/mpy_a700.d
+  gas/testsuite/gas/arc/ex_arc700.s
+  gas/testsuite/gas/arc/mpy_a700.s
+  gas/config/extlib
+  gas/config/extlib/configure
+  gas/config/extlib/Makefile.in
+  gas/config/extlib/arcsimd.s
+  gas/config/extlib/configure.in
+  gas/config/extlib/arcextlib.s
+  include/elf/ChangeLog.codito
+  libgloss/arc/syscall.h (delivered as linux/include/asm-arcnommu/unistd.h)
+  ld/emultempl/arclinux.em
+  ld/configdoc.texi
+  ld/scripttempl/elfarc.sc
+  ld/scripttempl/arclinux.sc
+  ld/emulparams/arclinux.sh
+  md5.sum
+  opcodes/ChangeLog.codito
+  opcodes/arcompact-dis.c
+ changed files:
+  bfd/archures.c (merged)
+  bfd/bfd-in2.h (merged/regenerated)
+  bfd/config.bfd
+  bfd/configure.in
+  bfd/cpu-arc.c (merged)
+  bfd/elf32-arc.c
+  bfd/reloc.c
+  bfd/cpu-arc.c
+  Makefile.in
+  gas/configure.tgt (patch was originally in configure.in)
+  gas/doc/c-arc.texi
+  gas/doc/as.texinfo
+  gas/configure.in
+  gas/testsuite/gas/arc/swi.d
+  gas/testsuite/gas/arc/sbc.d
+  gas/testsuite/gas/arc/sleep.d
+  gas/testsuite/gas/arc/brk.d
+  gas/testsuite/gas/arc/swi.s
+  gas/testsuite/gas/arc/rrc.d
+  gas/testsuite/gas/arc/bic.d
+  gas/testsuite/gas/arc/extb.d
+  gas/testsuite/gas/arc/arc.exp
+  gas/testsuite/gas/arc/asl.d
+  gas/testsuite/gas/arc/asr.d
+  gas/testsuite/gas/arc/sexw.d
+  gas/testsuite/gas/arc/adc.d
+  gas/testsuite/gas/arc/lsr.d
+  gas/testsuite/gas/arc/mov.d
+  gas/testsuite/gas/arc/ror.d
+  gas/testsuite/gas/arc/and.d
+  gas/testsuite/gas/arc/xor.d
+  gas/testsuite/gas/arc/rlc.d
+  gas/testsuite/gas/arc/or.d
+  gas/testsuite/gas/arc/sexb.d
+  gas/testsuite/gas/arc/jl.d
+  gas/testsuite/gas/arc/extw.d
+  gas/testsuite/gas/arc/add.d
+  gas/testsuite/gas/arc/sub.d
+  gas/struc-symbol.h
+  gas/config/tc-arc.c
+  gas/config/tc-arc.h
+  gas/Makefile.am
+  include/dis-asm.h
+  include/elf/arc.h
+  include/elf/common.h (adapted)
+  include/opcode/arc.h
+  ld/configure.in
+  ld/emulparams/arcelf.sh
+  ld/configure.tgt
+  ld/Makefile.am
+  binutils/configure.in
+  binutils/testsuite/binutils-all/objdump.exp
+  binutils/readelf.c
+  opcodes/configure.in
+  opcodes/arc-dis.c
+  opcodes/arc-dis.h
+  opcodes/arc-opc.c
+  opcodes/Makefile.am
+  opcodes/arc-ext.c
+  opcodes/arc-ext.h
+  gdb/doc/Makefile.in
+  gdb/doc/gdb.texinfo
+  gdb/remote.c
+  gdb/testsuite/gdb.base/float.exp
+  gdb/testsuite/lib/gdbserver-support.exp
+  gdb/testsuite/gdb.asm/asm-source.exp
+  gdb/dwarf2read.c
+  gdb/dwarf2-frame.c
+  gdb/configure.tgt
+  gdb/version.in
+  gdb/gdbserver/Makefile.in
+  gdb/gdbserver/configure.srv
+  gdb/gdbserver/proc-service.c
+  gdb/gdbserver/remote-utils.c
+  gdb/Makefile.in
+
+By ARC employees:
+ added files:
+  cgen/cpu/ARCompact.cpu
+  cgen/cpu/arc.opc
+  cgen/cpu/arc.cpu
+  cpu/arc.opc
+  cpu/sh-sim.cpu
+  cpu/arc.cpu
+  cpu/ARCompact.cpu
+  gas/ChangeLog.ARC
+  gdb/config/arc/arc.mt
+  include/gdb/target-io/arc.h
+  ld/ChangeLog.ARC
+  opcodes/arc-opc.h
+  opcodes/arc-opinst.c
+  opcodes/arc-desc.c
+  opcodes/arc-desc.h
+  opcodes/arc-ibld.c
+  opcodes/arc-asm.c
+  sim/arc/ChangeLog
+  sim/arc/configure.ac
+  sim/arc/mloop5.in
+  sim/arc/mloop6.in
+  sim/arc/mloop7.in
+  sim/arc/arc-sim.h
+  sim/arc/Makefile.in
+  sim/arc/tconfig.in
+  sim/arc/sim-main.h
+  sim/arc/devices.c
+  sim/arc/sim-if.c
+  sim/arc/arc5.c
+  sim/arc/arc6.c
+  sim/arc/arc7.c
+  sim/arc/config.in
+  sim/arc/configure
+  sim/arc/arch.h
+  sim/arc/arch.c
+  sim/arc/decode5.h
+  sim/arc/decode6.h
+  sim/arc/decode7.h
+  sim/arc/decode5.c
+  sim/arc/decode6.c
+  sim/arc/decode7.c
+  sim/arc/sem5-switch.c
+  sim/arc/sem6-switch.c
+  sim/arc/sem7-switch.c
+  sim/arc/sem5.c
+  sim/arc/sem6.c
+  sim/arc/sem7.c
+  sim/arc/cpu5.h
+  sim/arc/cpu6.h
+  sim/arc/cpu7.h
+  sim/arc/cpuall.h
+  sim/arc/cpu5.c
+  sim/arc/cpu6.c
+  sim/arc/cpu7.c
+  sim/arc/model5.c
+  sim/arc/model6.c
+  sim/arc/model7.c
+  sim/arc/traps.c
+  sim/common/ChangeLog.ARC
+  newlib/ChangeLog.ARC
+  newlib/libc/sys/arc/sys/fcntl.h
+ replaced files:
+  opcodes/arc-dis.c
+  opcodes/arc-opc.c
+ changed files:
+  bfd/configure
+  bfd/elf32-arc.c
+  bfd/libbfd.h
+  bfd/bfd-in2.h
+  cgen/ChangeLog
+  cgen/read.scm
+  cgen/sim-cpu.scm
+  cgen/utils-sim.scm
+  cgen/cpu/ip2k.opc
+  cgen/cpu/sparc.opc
+  cgen/cpu/xc16x.opc
+  cgen/cpu/fr30.opc
+  cgen/cpu/mep.opc
+  cgen/cpu/m32r.opc
+  cgen/cpu/i960.opc
+  cgen/cpu/sh.opc
+  cgen/cpu/iq2000.opc
+  cgen/cpu/openrisc.opc
+  cgen/cpu/xstormy16.opc
+  cgen/opc-itab.scm
+  cpu/ChangeLog
+  gas/config/tc-arc.c
+  gas/config/tc-arc.h
+  gas/configure
+  gas/Makefile.in
+  gas/doc/c-arc.texi
+  gas/as.c
+  gas/symbols.c
+  gas/symbols.h
+  gdb/ChangeLog
+  gdb/configure.tgt
+  include/ChangeLog
+  include/dis-asm.h
+  include/gdb/callback.h
+  include/gdb/ChangeLog
+  include/opcode/arc.h
+  include/opcode/cgen.h
+  ld/ChangeLog
+  ld/scripttempl/arclinux.sc
+  ld/scripttempl/elfarc.sc
+  ld/emulparams/arclinux.sh
+  ld/Makefile.am
+  ld/Makefile.in
+  libgloss/ChangeLog
+  opcodes/arc-dis.h
+  opcodes/arc-dis.c
+  opcodes/arc-ext.h
+  opcodes/arc-ext.c
+  opcodes/arc-opc.c
+  opcodes/ChangeLog
+  opcodes/configure
+  opcodes/configure.in
+  opcodes/Makefile.am
+  opcodes/Makefile.in
+  opcodes/cgen-dis.c
+  sim/ChangeLog
+  sim/configure.ac
+  sim/configure
+  sim/common/callback.c
+  sim/common/cgen-trace.c
+  sim/common/ChangeLog
+  sim/common/gennltvals.sh
+  sim/common/gentvals.sh
+  sim/common/nltvals.def
+  sim/common/sim-utils.c
+  sim/common/syscall.c
diff --git a/gdb/ChangeLog.codito b/gdb/ChangeLog.codito
new file mode 100644
index 0000000..50bedf8
--- /dev/null
+++ b/gdb/ChangeLog.codito
@@ -0,0 +1,1198 @@
+2006-05-18  Kunal Parmar  <kunal.parmar@codito.com>
+
+	18th May 2006 Release
+	* version.in: Change to 6.3_codito_20060518, which is when it is
+	scheduled to be released.
+
+2006-05-11  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* arc-tdep.c (a4_scan_prologue): Include function only for A4. 
+
+2006-04-28  Ashwin Pathmudi  <ashwin.pathmudi@codito.com>
+
+	* arc-tdep.c (arc_push_dummy_call): Correct handling
+	of struct return for the a4 core.  
+
+2006-04-26  Ashwin Pathmudi  <ashwin.pathmudi@codito.com>
+
+	* arc-tdep.c (a4_address_to_pointer): New. Converts address
+	to pointer for the a4 core.  
+	(a4_pointer_to_address): New.  Converts pointers to address
+	for the a4 core.  
+	(arc_gdbarch_init): Add the above 2 new functions to the 
+	gdbarch structure for the A4 core. 
+
+2006-03-29  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* Makefile.in (arc-jtag-ops.o): Add arc-tdep.h to the list of
+	dependencies. 
+	* arc-jtag-ops.h: Include arc-tdep.h.
+	(IS_ARC700): New macro. Return 1 if processor connected is
+	ARC700. 
+	(IS_ARC600): New macro. Return 1 if processor connected is
+	ARC600. 
+	(IS_A5): New macro. Return 1 if processor connected is A5. 
+	(IS_A4): New macro. Return 1 if processor connected is A4. 
+	* arc-jtag-ops.c (ARCProcessor): New global variable. Contains the
+	processor type that has been connected.
+	(arc_get_architecture): New function. Return the processor type
+	that has been connected. Set ``ARCProcessor'' when run the
+	first time.
+	(arc_jtag_close): Unset ``ARCProcessor''.
+	(arc_jtag_open): Remove ifdefs and use above macros instead.
+	(arc_jtag_wait): Ditto.
+	* arc-jtag.c (arc_update_architecture): Use above macros.
+
+2006-03-13  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* arc-tdep.c (arc_gdbarch_init): Characters are unsigned by
+	default. 
+
+2006-03-08  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* arc-jtag-ops.c (arcjtag_retry_count): New variable. Defines the
+	number of times a JTAG operation is attempted before returning a
+	failure.	
+	(arc_jtag_read_core_reg): Use above variable.
+	(arc_jtag_write_core_reg): Ditto.
+	(arc_jtag_read_aux_reg): Ditto.
+	(arc_jtag_write_aux_reg): Ditto.
+	(read_mem): Ditto.
+	(write_mem): Ditto.
+	* arc-jtag.c (_initialize_arc_debug): Add command to set above
+	variable. 
+
+2006-03-03  Ashwin Pathmudi  <ashwin.pathmudi@codito.com>
+
+	* arc-tdep.c (arc_push_dummy_call): Add support for dummy
+	call for the A4 core.  
+	(arc_extract_return_value): Enable for A4 core.  
+	(arc_store_return_value): Likewise.  
+	(arc_return_value): Likewise.  
+	(arc_gdbarch_init): Set call_dummy_location to 
+	AT_ENTRY_POINT for A4 core.  
+
+	* arc-jtag-tdep.c (arc_jtag_register_reggroup_p): Adding the 
+	status register to save/restore group for the A4 core.  
+
+2006-03-03  Ashwin Pathmudi  <ashwin.pathmudi@codito.com>
+
+	* arc-tdep.c (printFrameInfo): Print more verbose messages.  
+	(printInsnState): Likewise.  
+	(a4_scan_prologue): New.  Function to scan the prologue and 
+	fill the unwind cache.  
+	(arc_skip_prologue): Call a4_scan_prologue for a A4 core.  
+	(arc_frame_unwind_cache): Likewise.  
+	(arc_dwarf2_frame_init_reg): Defined for A4 core.  
+	(arc_unwind_pc): Defined for A4 core.  
+	(arc_scan_prologue): Cosmetic change.  
+	(arc_frame_this_id): Likewise.  
+	(arc_frame_prev_register): Likewise.  
+	(arc_next_pc): Likewise.  
+	(arc_software_single_step): Likewise.  
+	(arc_extract_return_value): Likewise.  
+	(arc_store_return_value): Likewise.  
+	(arc_return_value): Likewise.  
+	(arc_sigtramp_frame_cache): Likewise.  
+	(arc_sigtramp_frame_this_id): Likewise.  
+	(arc_sigtramp_frame_prev_register): Likewise.
+	(arc_sigtramp_frame_cache): Likewise.  
+	(arc_sigtramp_frame_sniffer): Likewise.  
+	(arc_push_dummy_call): Likewise.  
+	(arc_gdbarch_init): Change definition of disassembler to
+	arc_get_disassembler for the A4 core.  
+
+	* arc-jtag.h (debug_arc_jtag_target_message): New.  Definition
+	moved here.  
+
+	* arc-jtag.c (arc_debug_open): Cosmetic change.  
+	(arc_get_hw_regnum_mapping): Setting boundary limit for
+	A4 core.  
+
+	* arc-jtag-tdep.c (A4_HALT_VALUE): New. Define Halt 
+	value in status register.  
+	(a4_jtag_write_pc): Correct handling of write pc.
+	(a4_jtag_read_pc): New.  Function to read pc for the 
+	a4 core.  
+	(arc_jtag_init): Modify tdep gdbarch structure to
+	include read_pc.
+
+2006-03-03  Ashwin Pathmudi  <ashwin.pathmudi@codito.com>
+
+	* arc-tdep.c (arc_scan_prologue): Disabling temporarily for
+	the A4 core.  
+	(arc_skip_prologue): Likewise.  
+	(arc_frame_unwind_cache): Likewise.  
+	(arc_frame_this_id): Likewise.  
+	(arc_frame_prev_register): Likewise.  
+	(arc_next_pc): Likewise.  
+	(arc_software_single_step): Likewise.  
+	(arc_dwarf2_frame_init_reg): Likewise.  
+	(arc_extract_return_value): Likewise.  
+	(arc_store_return_value): Likewise.  
+	(arc_return_value): Likewise.  
+	(arc_sigtramp_frame_cache): Likewise.  
+	(arc_sigtramp_frame_this_id): Likewise.  
+	(arc_sigtramp_frame_prev_register): Likewise.  
+	(arc_sigtramp_frame_sniffer): Likewise.  
+	(arc_push_dummy_call): Likewise.  
+	(arc_gdbarch_init): Modify gdbarch structure for A4. 
+	(arc_binutils_reg_to_regnum): Add A4 specific conversion of
+	register numbers.  
+
+	* arc-jtag.c (arc_debug_open): A4 specific status register
+	read.  
+	(arc_debug_resume): A4 specific change for status and 
+	debug auxillary registers.  
+	(arc_debug_insert_breakpoint): Add opcode for the A4 break
+	instruction.  
+	(arc_debug_remove_breakpoint): Write 4 bytes back for the 
+	A4.  
+	(arc_print_processor_variant_info): Adding A4 to the list
+	of processors.  
+
+	* arc-jtag-tdep.c (a4_jtag_breakpoint_size): New. Defines
+	the size of the breakpoint instruction for A4.  
+	(a4_jtag_breakpoint_insn): New.  Defines the opcode for 
+	the breakpoint instruction for A4.  
+	(arc_jtag_register_name): Exclude non A4 registers for
+	A4-gdb.  
+	(a4_jtag_write_pc): New.  Write value to the program
+	counter for A4.  
+	(arc_jtag_init): Modify the target dependent part of 
+	gdbarch struct for the A4 core.  
+
+	* arc-jtag-ops.c (A4_HALT_VALUE): New. Halt bit set in
+	the status auxillary (0x0) register.  
+	(ARC700_HALT_VALUE): New.  Halt bit set in status32
+	auxillary register.  
+	(arc_jtag_read_aux_reg): Add more verbose messages.  
+	(arc_jtag_write_aux_reg): Likewise.  
+	(arc_jtag_open): Read the status auxillary register
+	for the A4 core.  
+	(arc_jtag_wait): Likewise.  
+
+2006-03-02  Ashwin Pathmudi  <ashwin.pathmudi@codito.com>
+
+	* configure.tgt: Add A4-JTAG target.  
+	* config/arc/a4-jtag.mt: New. Makefile fragment for
+	new A4-JTAG target.  
+	* config/arc/tm-a4-jtag.h: New. Target specific header file 
+	for the A4-JTAG target.  
+
+	* arc-tdep.h: Add the A4 to the ARC processor version
+	information.  
+
+	* arc-tdep.c (arc_cannot_store_register): Exclude non A4 
+	registers for A4-gdb.  
+	(arc_next_pc): Likewise.  
+	(arc_register_reggroup_p): Likewise.  
+
+	* arc-regnums-defs.h: Exclude non-A4 registers for A4-gdb.  
+
+	* arc-jtag.c (arc_update_architecture): Identify the A4 core.  
+	(clear_status32_user_bit): Allow only A4 Registers.  
+	(restore_status32_user_bit): Likewise.  
+	(arc_debug_open): Not compiling for the A4 core yet.
+	(arc_debug_resume): Likewise.  
+	(arc_debug_wait): Excluding Arc600 specific part for A4 core.  
+	(arc_get_hw_regnum_mapping): Exclude non-A4 registers for
+	the A4 core.  
+	(arc_debug_fetch_regs): Likewise.  
+	(arc_debug_store_regs): Likewise.  
+	(init_arc_debug_ops): Modify target_ops for A4 core.  
+
+	* arc-jtag-tdep.c (arc_jtag_register_reggroup_p): Allow only A4 
+	Registers.  
+	(arc_jtag_print_registers_info): Likewise.  
+	(arc_jtag_init): Likewise.  
+
+2006-01-02  Ashwin Pathmudi  <ashwin.pathmudi@codito.com>
+
+        PR 1496
+	* dwarf2-frame.c (dwarf2_frame_state_copy_regs): Correct 
+	allocated size.  
+
+2005-12-17  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* arc-jtag.c (arc_debug_wait): Reverting to version 1.40
+
+2005-12-16  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* arc-jtag-ops.c (arc_jtag_open): Change the message printed when
+	processor is running.
+	* arc-jtag.c (arc_debug_wait): Dont assume the program to have
+	exited when SH bit is set.
+
+2005-11-08  Kunal Parmar  <kunal.parmar@codito.com>
+
+	8th November Release
+	* version.in: Change to 6.3_codito_20051108, which is when it is
+	going to be released.
+
+2005-09-28  Kunal Parmar  <kunal.parmar@codito.com>
+
+	Bug #1479
+	* arc-jtag-tdep.c (arc_jtag_register_reggroup_p): Remove IDENTITY
+	register from save/restore group.
+
+2005-09-27  Kunal Parmar  <kunal.parmar@codito.com>
+
+	Bug #1476
+	* arc-jtag.c (arc_debug_xfer_partial): Fix for Bug #1476 (gdb for
+	JTAG goes into infinite loop).
+
+2005-09-24  Kunal Parmar  <kunal.parmar@codito.com>
+
+	Bug #1475
+	* arc-jtag-ops.c (arc_jtag_read_chunk): Fix for Bug #1475 (printf
+	command in gdb for JTAG fails).
+
+2005-09-23  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* arc-jtag.c (arc_debug_xfer_partial): The value being returned
+	was incorrect.
+
+2005-09-23  Kunal Parmar  <kunal.parmar@codito.com>
+
+	Bug #1286
+	* arc-jtag-ops.c: Fix for Bug #1286 (reading an invalid register
+	causes next operation to fail).
+	
+2005-09-23  Kunal Parmar  <kunal.parmar@codito.com>
+
+	Bug #1272
+	* arc-jtag.c (arc_debug_create_inferior): Check if an executable
+	file has been handed to us, print an error if none is specified.
+
+2005-07-14  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+        Bug #1381
+	* arc-jtag-ops.c (arc_jtag_close): Close file descriptor opened
+	for communication with gpio driver.
+
+2005-07-06  Soam Vasani  <soam.vasani@codito.com>
+
+	Bug #1364
+	* arc-jtag.c (arc_debug_xfer_partial): Restore the User bit in
+	status32.  This fixes bug #1364 (userland debugging: kernel
+	panic).
+
+2005-06-28  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (arc_debug_detach): Resume the inferior.
+
+2005-06-28  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (arc_debug_xfer_partial): Clear STATUS32 user bit
+	when reading or writing memory (earlier, we only cleared it while
+	writing.)
+
+2005-06-25  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-linux-tdep.c (arc_linux_register_name): Change name of
+	stop_pc from "stop_pc" to "pc".
+	(arc_linux_print_registers_info): Remove "ret" and add stop_pc.
+
+2005-06-24  Soam Vasani  <soam.vasani@codito.com>
+
+	Bug #1325 (core file support)
+	* arc-linux-tdep.c (arcompact_linux_core_reg_offsets): New array.
+	offsets of registers in core file's register section, for
+	ARCompact.
+	(arcompact_linux_supply_gregset): New function.  Get registers
+	from core file's register section, for ARCompact.
+	(arc_linux_supply_gregset): New function.  Get registers from core
+	file register section.
+	(arc_linux_gregset): For the gdbarch function.
+	(arc_linux_regset_from_core_section): This is called through
+	gdbarch.
+	* config/arc/linux.mt (TDEPFILES): Add corelow.c to list.
+
+2005-06-21  Soam Vasani  <soam.vasani@codito.com>
+
+	* gdb/arc-jtag.c (arc_update_architecture): Check for A5, print a
+	warning but don't give an error.
+	* gdb/arc-tdep.h (ARCProcessorVersion): Add A5.
+
+2005-06-20  Soam Vasani  <soam.vasani@codito.com>
+
+	Bug #1311
+	* arc-jtag.c (arc_debug_wait): In ARC600, try to detect the case
+	of a breakpoint on the last instruction of a ZOL and warn the
+	user.
+	(arc_debug_read_core_register): New function.  Read a core
+	register and check for errors.
+
+2005-06-19  Soam Vasani  <soam.vasani@codito.com>
+
+	Bug #1305
+	* dwarf2read.c: Fix for bug #1305 (Failure with Metaware compiled
+	binaries)
+
+2005-05-21  Soam Vasani  <soam.vasani@codito.com>
+
+	23rd May Release
+	* version.in: Change to 6.3_codito_20050523, which is when it is
+	going to be released.
+
+2005-05-21  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (arc_debug_store_regs): Show regno argument in debug
+	message.
+
+2005-05-21  Soam Vasani  <soam.vasani@codito.com>
+
+	* Makefile.in (arc-tdep.o): Add observer.h to the list of
+	dependencies.
+
+2005-05-21  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag-tdep.c (arc_jtag_register_reggroup_p): Remove extension
+	registers from _all_ reggroups, because they do not exist (as of
+	now).  Narrow down the list of registers in the save/restore group.
+
+2005-05-21  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+        * arc-jtag-ops.c: Included more header files to remove build time
+	warnings
+	
+2005-05-21  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+        PR arcgdb/1282
+	* arc-jtag.c: small changes to remove warnings during compilation.
+	* arc-jtag-ops.c(arc_debug_wait): Adding code to block and unblock
+	signals so that ctrl+c should work.
+
+2005-05-21  Soam Vasani  <soam.vasani@codito.com>
+
+	21st May 2005 Release.
+        * version.in: Bump version to 6.3_codito_20050521
+
+2005-05-21  Soam Vasani  <soam.vasani@codito.com>
+
+	Bug #1278
+	* arc-tdep.c (arc_set_main_name): New function.  Set main name to
+	_main if necessary.
+	(arc_gdbarch_init): Make arc_set_main_name an observer of
+	inferior_created.
+
+2005-05-16  Soam Vasani  <soam.vasani@codito.com>
+
+	Bug #1279
+	* remote.c (remote_open_1): Call observer_notify_inferior_created.
+	
+2005-05-16  Soam Vasani  <soam.vasani@codito.com>
+
+	15th May 2005 Release.
+        * version.in: Bump version to 6.3.50_cdt_gdb_20050515
+
+2005-05-15  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag-tdep.c (arc_jtag_init): Rename the aux-read command to
+	arc-aux-read and aux-write to arc-aux-write.
+
+2005-05-15  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (arc_debug_wait): If the SH (self halt) bit is set,
+	assume that the program has exited, with exit code in R0.
+	* arc-jtag.h (ARC_DEBUG_REG_SH_BIT): Define.  Self halt bit in the
+	debug register.
+
+2005-05-15  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag-ops.c (arc_jtag_open): Correct and conditionalise debug
+	printfs.
+
+2005-05-15  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (arc_debug_open): Call target_preopen,
+	reopen_exec_file and reread_symbols.
+
+2005-05-13  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag-ops.c (arc_jtag_close): Conditionalize a debug printf.
+
+2005-05-13  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.h (ARC_TARGET_OBJECT_AUXREGS): Define.  For use in
+	target_xfer_partial.
+	(target_read_aux_reg, target_write_aux_reg): Change to use
+	target_xfer_partial.
+	* arc-jtag.c (arc_debug_xfer_partial): Support reading/writing of
+	auxillary registers, using ARC_TARGET_OBJECT_AUXREGS.
+	(init_arc_debug_ops): Stop using to_data (we'll use
+	target_xfer_partial for aux registers).
+	* arc-jtag-tdep.c (arc_jtag_aux_read_command): New command: read a
+	range of aux registers.
+	(arc_jtag_aux_write_command): New command: write an aux register.
+	(arc_jtag_init): Add the above commands.
+
+2005-05-13  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* arc-jtag-ops.c(check_and_raise_error_if_jtag_closed):New function
+	for sanity checks. 
+	(arc_jtag_reset_board):Use above.
+	(arc_jtag_wait):Likewise.
+	(arc_jtag_read_chunk):Likewise.
+	(arc_jtag_read_core_reg):Likewise.
+	(arc_jtag_write_core_reg):Likewise.
+	(arc_jtag_read_aux_reg):Likewise.
+	(arc_jtag_write_aux_reg):Likewise.
+
+
+2005-05-13  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* arc-jtag.c: Rename cmd arc_bcr_registers to arc-bcr-registers.
+	Rename arcjtag-debugstatemachine to arcjtag-debug-statemachine 
+
+2005-05-13  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* arc-jtag-ops.h: Rename members to JTAG_OPENED and JTAG_CLOSED.
+	* arc-jtag-ops.c(arc_jtag_reset_board): Introduce
+	  sanity checks for checking target being opened. 
+	  (arc_jtag_open):set status to JTAG_OPENED.  
+
+2005-05-13  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag-ops.h: Add new member for reset_board.
+	* arc-jtag-ops.c(arc_jtag_reset_board):New function.
+	(initialize_arc_jtag_ops):Initialize reset board. 
+	* arc-jtag.c: New command arc-reset-board
+
+2005-05-13  Sameer Dhavale <sameer.dhavale@codito.com>
+
+	* arc-jtag.c: Add corrections to code to remove build time
+	warnings.
+	
+2005-05-13  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (clear_status32_user_bit, restore_status32_user_bit):
+	New functions: clear/restore the user-mode bit in the status32
+	register.
+	(set_debug_user_bit): Set the UB bit in the debug register, so
+	that breakpoints work in user mode.
+	(arc_debug_open, arc_debug_resume): Call set_debug_user_bit.
+	(arc_debug_xfer_partial): When writing, go to kernel mode so that
+	we are not affected by privileges.
+	
+2005-05-12  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+        PR arcgdb/1277
+	* arc-jtag-ops.c(gpio_write): Add function to write data to
+	parallel port.
+	(gpio_read): Add function to read from parallel port.
+	* gpio.h: New file. Add to support the interface with /dev/gpio.
+	
+2005-05-12  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* dwarf2-frame.c(execute_cfa_program): Ignore the contents
+	for a MW_ARC_info cfa directive. 
+
+2005-05-12  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* dwarf2-frame.c(decode_frame_entry_1):Ignore High C compilers
+	augmentation value in the frame entry. 
+
+2005-05-12  Sameer Dhavale <sameer.dhavale@codito.com>
+
+	* arc-jtag-ops.c(arc_jtag_write_aux_reg): Return value on
+	successful transaction.
+	* arc-jtag-ops.h: Change in prototype of function
+	jtag_memory_read().	
+
+2005-05-11  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+	* arc-jtag-ops.c: Remove extra messages introduced by prev commit
+	and changing all printf() to printf_filtered().
+
+2005-05-10  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+        PR arcgdb/1275 
+	* arc-jtag-ops.h(struct jtag_ops):Change protypes of functions
+	jtag_read_core_reg(), jtag_read_aux_reg(), jtag_write_core_reg(),
+	jtag_write_aux_reg() to handle errors gracefully.
+	* arc-jtag-ops.h(arc_jtag_read_core_reg): Change definition of
+	function to return the no of bytes read instead of returning
+	value.
+	(arc_jtag_write_core_reg): Change definition of function to return
+	the no of bytes actually written.
+	(arc_jtag_read_aux_reg):  Change definition of
+	function to return the no of bytes read instead of returning
+	value.
+	(arc_jtag_write_aux_reg): Change definition of function to return
+	the no of bytes actually written.
+	*arc-jtag.c: Change all calls to interface functions to accomodate
+	the changes made above and check and handle error gracefully with
+	error messages.
+
+2005-05-10  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* arc-jtag.c(arc_update_architecture):Set up decr_pc_after_break
+	for ARC600 as 2 and 0 for ARC700.
+
+2005-05-10  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* arc-jtag.h(is_arc700):New Function.
+	(is_arc600):New Function.
+	* arc-jtag.c(arc_jtag_resume):Single Step Mask 
+	is different for both ARC600 and ARC700. Use functions is_arc700
+	and is_arc600.
+
+2005-05-10  Ramana Radhakrishnan  <ramana@codito.com>
+	    Soam Vasani		  <soam.vasani@codito.com>
+
+	* arc-jtag.c(arc_debug_resume): Invalidate caches
+	for single stepping or even while resuming. 
+
+2005-05-10  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* arc-jtag.c(arc_debug_open):Set STATUS32 to 1 
+	when opening JTAG .
+
+2005-05-10  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* Makefile.in:Update dependency for arc-jtag-tdep.o
+	* ChangeLog.codito: Correct changelog entry. 
+
+2005-05-10  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag-tdep.c: Update copyright notice.
+	* arc-tdep.h: Likewise.
+	
+2005-05-10  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* Makefile.in:Update dependencies for ARC specific files.
+
+2005-05-10  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	*arc-jtag.h: (enum arc_hw_regnums): New enum. 
+	(arc-regnum-defs.h):Include.
+	(Define and undefine R_AUX and R_BCR)
+	* arc-regnum-defs.h: New file. 
+	* arc-jtag-ops.h(enum arc700_hw_regnum):Remove. 
+	* arc-jtag.c(R):Remove Macro.
+	(arc-regnum-defs.h):Include. 
+	(RAUX):New macro.
+	(RBCR):New macro. 
+	(arc_bcr_reg_info):Use above macros.
+	(arc_aux_reg_map):Likewise.
+	(struct arc_reg_info):Change type to arc_hw_regnum
+	(arc_update_architecture):Use ARC_HW_IDENTITY_REGNUM. 
+	(invalidateCaches):Use ARC_HW_ICACHE_IVIC
+	Use ARC_HW_DCACHE_IVIC to invalidate caches. 
+	(disableCaches):Use ARC_HW_ICACHE_CONTROL, 
+	ARC_HW_DCACHE_CONTROL to disable caches. 
+	(arc_debug_resume):Use ARC_HW_STATUS32_REGNUM. 
+	Use ARC_HW_DEBUG_REGNUM.
+	
+
+2005-05-10  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag-tdep.c(struct arc_reg_info):New struct. 
+	(arc_jtag_register_name):Move BCR registers below all 
+	the Auxiliary registers. This is to take care of printing
+	Build Configuration Registers and Auxiliary registers in 
+	one chunk. 
+	Rename BCR Registers to their correct names. 
+	(arc_jtag_print_registers_info):Use the all parameter to print
+	bcr registers and all the known ARC700 auxiliary registers 
+	and Build Configuration Registers.
+	* arc-jtag.c:(arc_aux_reg_map):New regmap for Auxiliary registers. 
+	(arc_get_hw_regnum_mapping):Use this to create mapping 
+	between gdb regnums and hw regnums. 
+	(arc_debug_fetch_regs):Use above.
+	(arc_debug_store_regs):Use above. 
+	* arc-tdep.h:Add processor versions UNSUPPORTED and ARCompact. 
+	* config/arc/tm-embed.h:Restructure the AUX Registers
+	information to be above the BCRs.
+	
+
+2005-05-09  Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag.c(arc_jtag_open):Remove call to invalidateCache. 
+	(arc_debug_load):Add code to zero out the bss section.
+
+2005-05-09  Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag.c(struct arc_reg_info): Correct typo for arc_gdb_regnums.
+
+2005-05-09  Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
+
+	* arc-tdep.h (ARCProcessorVersion):New enum.
+	(ARCExtensionsSupportedInformation):New enum.
+	(ARCProcessorInformation):New structure to store ARC 
+	processor variant information.
+	(gdbarch_tdep):Add member of ARCProcessorInformation.
+	* arc-jtag-tdep.c (arc_debug_processor_information):Add new
+	variable. 
+	(arc_jtag_init):Initialize tdep->arc_processor_variant_info. 
+	* arc-linux-tdep.c (arc_linux_init_abi):Set ARC processor 
+	variant info to NULL.
+	* arc-jtag.c (arc_update_architecture):New function Update 
+	architecture information. 
+	(invalidateCaches):Invalidate Cache.
+	(disableCaches):Disable Cache.
+	(arc_debug_open):Call enable and invalidate caches and 
+	arc_update_architecture. 
+
+2005-05-06  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (arc_debug_wait): Set status waitkind and signal
+	value, so that our caller thinks we stopped due to a SIGTRAP.
+
+2005-05-05  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+	PR arcgdb/1271 
+	* arc-jtag.c (arc_debug_resume): Add support for hardware single
+	instruction stepping. 
+
+2005-05-05  Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag.h: Add copyright notice.
+
+2005-05-05  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (arc_debug_read_aux_register,
+	arc_debug_write_aux_register): New functions.
+	(arc_debug_aux_reg_functions): Struct containing pointers to
+	arc_debug_read/write_aux_register.
+	(init_arc_debug_ops): Set to_data to arc_debug_aux_reg_functions.
+	* arc-jtag.h (target_read_aux_reg, target_write_aux_reg): New
+	macros.
+
+2005-05-05  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag-ops.c(AA3SSPinState):New enum for target comms
+	to AA3.
+	(arc_jtag_read_chunk):Change usage of rw_flag.
+	(arc_jtag_write_chunk):Change usage of rw_flag.
+	(read_mem):Change usage of rw_flag.
+	(write_mem):Change usage of rw_flag to use the new enum.
+	(arc_jtag_write_chunk):Formatting cleanups.
+	
+	
+
+2005-05-05  Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag-ops.c:Cleanup. 
+	(port_perms_setup): Make static.
+	(tapc_set_tms): Likewise.
+	(tapc_set_tck): Likewise.
+	(tapc_set_tdi): Likewise.
+	(clockdelay): Likewise.
+	(tapc_pulse): Likewise.
+	(tapc_reset): Likewise.
+	(tapc_tms): Likewise.
+	(tapc_readbit): Likewise.
+	(tapc_shiftbit): Likewise.
+	(tapc_shiftnbits): Likewise.
+	(read_jtag_status_reg): Likewise.
+	(print_jtag_status_reg_val): Likewise.
+	(write_jtag_reg): Likewise.
+	(read_jtag_reg): Likewise.
+	(arc_jtag_read_core_reg): Likewise.
+	(arc_jtag_write_core_reg): Likewise.
+	(arc_jtag_read_aux_reg): Likewise.
+	(arc_jtag_write_aux_reg): Likewise.
+	(read_mem): Likewise.
+	(write_mem): Likewise.
+	(arc_jtag_write_chunk): Likewise.
+	(arc_jtag_read_chunk): Likewise.
+	(arc_jtag_open): Likewise.
+	(arc_jtag_close): Likewise.
+	(arc_jtag_wait): Likewise.
+	(tapc_shift4bits):Remove.
+		
+2005-05-05  Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag-ops.c, arc-jtag-ops.h: Add copyright notice.
+
+2005-05-05  Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag.c:debug_arc_jtag_target_messages New variable. 
+	(_initialize_arc_debug):Use above. Add a new boolean command, 
+	arcjtag-debug-target to print debug target messages.
+
+2005-05-05  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (arc_debug_open): Print message on success.
+
+2005-05-05  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+        PR arcgdb/1270
+	* arc-jtag-ops.c (tapc_pulse): Remove cals to clock delay to
+	achieve download speed-up.
+	(arc_jtag_read_core_reg): Add a call to tapc_reset() before
+	reading any register.
+	(arc_jtag_write_core_reg): Add a call to tapc_reset() before
+	writing any register. 
+	(arc_jtag_read_aux_reg): Add transition to run-test-idle state in
+	the wait loop.
+	(arc_jtag_read_aux_reg): Add a call to tapc_reset() before reading
+	any aux register.
+	(arc_jtag_write_chunk): Add a fix to support the writes to memory
+	which are not integral multiples of four.
+	(arc_jtag_read_chunk): Add a fix to support the reads from memory
+	which are not integral multiples of four.
+	(_initialize_arc_jtag_ops): Add entries to initialize read/write
+	core registers.
+	* arc-jtag-tdep.c (arc_jtag_init): Add to initialize
+	tdep->sigtramp_p to NULL. This avoids the segmentation fault.
+	* arc-jtag.c (arc_debug_open): Disable Dcache and Icache.
+	(arc_debug_xfer_partial): Add fix for address alignment.
+	(arc_debug_insert_breakpoint): Modify to support ARC700 specific
+	breakpoint.
+	(arc_debug_remove_breakpoint): Modify to support ARC700 specific
+	breakpoint.
+	
+
+2005-05-04  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* arc-jtag-ops.c: Correct ioperms error messages. 
+	Setup read_core_register correctly.
+
+2005-05-04  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	PR arcgdb/1267
+	* arc-jtag-ops.h: Add new enum arc_jtag_status for housekeeping. 
+	  (arc_jtag_ops):Add data member to this. 
+	* arc-jtag-ops.c: #define printf to printf_filtered when used 
+	in gdb. 
+	(port_perms_setup):Return error message in case of errors
+	(arc_jtag_close):Call tapc_reset only when the JTAG is not 
+	already closed. 
+	
+2005-05-03  Soam Vasani  <soam.vasani@codito.com>
+
+	PR arcgdb/1260
+	* arc-tdep.h (struct gdbarch_tdep): Add member lowest_pc, which is
+	initialized in the linux or jtag tdep files.  It's meant to stop
+	backtraces at the entry point (_start).
+	* arc-tdep.c (arc_frame_this_id): Don't set frame_id if 
+	func <= lowest_pc.
+	* arc-linux-tdep.c (arc_linux_init_abi): Init lowest_pc to 0x74.
+	* arc-jtag-tdep.c (arc_jtag_init): Init lowest_pc to 0.
+	
+2005-05-03  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-tdep.c (arc_software_single_step): We cannot single-step
+	single instruction zero overhead loops and branch-to-self's.  Step
+	over them and print a warning.
+
+2005-05-02  Sameer Dhavale <sameer.dhavale@codito.com>
+
+	PR arcgdb/1265
+	* arc-jtag-ops.h (arc700_hw_regnums): Add entries to map LP_START
+	and LP_END registers.
+	* arc-jtag.c (arc_debug_store_regs): Add register mapping from
+	gdbarch register numbers to hardware register numbers.
+	(arc_debug_fetch_regs): Add register mapping from
+	gdbarch register numbers to hardware register numbers.
+
+2005-04-29  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-tdep.c (arc_gdbarch_init): Move the call of
+	set_gdbarch_software_single_step to arc-linux-tdep.c.
+	* arc-linux-tdep.c (arc_linux_init_abi): Set gdbarch software
+	single step.
+
+2005-04-28  Soam Vasani  <soam.vasani@codito.com>
+
+	* config/arc/tm-embed.h (enum arc700_jtag_regnums): Fix mistakes
+	in numbering.
+
+2005-04-28  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-tdep.c (arc_scan_prologue): Pass stream and fprintf_func to
+	init_disassemble_info, to be used in case of a memory error.
+
+2005-04-28  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-tdep.c (arc_scan_prologue): Handle R27 along with other
+	callee-saved registers.
+
+2005-04-27  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-jtag.c (arc_debug_wait): Setup control-C signal handler.
+	(arc_debug_interrupt): New function; handler for SIGINT.
+	(arc_debug_interrupt_twice): New function; called when user does
+	control-C twice.
+
+2005-04-26  Soam Vasani <soam.vasani@codito.com>
+
+	* arc-tdep.c (arc_register_name): Moved to arc-linux-tdep.c and
+	arc-jtag-tdep.c.
+	(arc_register_reggroup_p): Save/restore reggroups contain all
+	writable registers.
+	* arc-tdep.h (arc700_api_regnums): Define ARC_ARGx_REGNUMs and
+	ARC_RETURNx_REGNUMs.
+	(arc700_regnums): Moved to tm-linux.h and tm-embed.h.
+	(gdbarch_tdep): Removed member register_name.
+	gdbarch_register_name is now in arc-linux-tdep.c and
+	arc-jtag-tdep.c.
+	* arc-linux-tdep.c (arc700_linux_regnums): Moved to
+	config/arc/tm-linux.h.
+	(arc_linux_register_name): Names for all the registers in linux.
+	Moved from arc-tdep.c.
+	* arc-jtag.h (arc700_jtag_regnums): Moved to
+	config/arc/tm-embed.h.
+	* arc-jtag-tdep.c (arc_jtag_register_name): Names for all the
+	registers.  Moved from arc-tdep.c.
+	(arc_jtag_pseudo_register_read, arc_jtag_pseudo_register_write):
+	Removed; no pseudo registers when using JTAG.
+	* config/arc/tm-embed.h (arc700_jtag_regnums): Define all the
+	basecase registers (core as well as aux).  Renamed the
+	ARC_*_PSEUDO_REGNUMs to ARC_*_REGNUMs; changed references
+	appropriately.
+	* config/arc/tm-linux.h (arc700_linux_regnums): Define all the
+	registers that linux/ptrace gives.
+
+2005-04-25  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+	* arc-jtag-ops.h: Add
+	Previous commit did not actually add the file to cvs.  So adding it
+	via this commit. 
+
+2005-04-22  Soam Vasani <soam.vasani@codito.com>
+
+	* arc-linux-tdep.c (arc_linux_skip_solib_resolver): New function;
+	skip uClibc's runtime resolver.
+	* arc-linux-tdep.c (arc_linux_init_abi): Set gdbarch
+	fetch_link_map_offset and skip_solib_resolver.
+	* config/arc/linux.mt (TDEPFILES): Remove glibc-tdep, we don't
+	need it.
+
+2005-04-20  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+	PR arcgdb/1242
+	* arc-jtag-ops.h: Add 
+	(jtag_ops): New structure defined.
+	* arc-jtag-ops.c: Add
+	(port_perms_setup): New function. Add to set desired permissions
+	for port access.
+	(tapc_set_tms): New function. Add for Setting value to TMS pin of JTAG
+	port.
+	(tapc_set_tck): New function. Add for setting or resetting TCK pin
+	of JTAG port.
+	(tapc_set_tdi): New function. Add for sending data into JTAG
+	module via TDI input pin.
+	(clockdelay): New function. Add to generate required pulse width.
+	(tapc_pulse): New function. Add to generate pulse over TCK.
+	(tapc_reset): New function. Add to reset the JTAG state machine
+	(tapc_tms): New function. Add to set or reset the TMS pin of JTAG
+	port.
+	(tapc_readbit): New function. Add to read a single bit from TDO
+	pin of JTAG port.
+	(tapc_shiftbit): New function. Add to shift in one bit through TDI
+	and simultaneously shift out bit through TDO.
+	(tapc_shiftnbits): New function. Add to shift n bits in either
+	LSB-first or MSB-first fashion.
+	(read_jtag_status_reg): New function. Add to read the status of
+	transaction being requested by JTAG module.
+	(write_jtag_reg): New function. Add to write to any internal
+	registers of JTAG module.
+	(read_jtag_reg): New function. Add to read from any internal
+	register of JTAG.
+	(read_core_reg): New function. Add to read from any core register
+	of ARC700 via JTAG.
+	(write_core_reg): New function. Add to write to any core register
+	of ARC700 via JTAG.
+	(arc_jtag_read_aux_reg): New function. Add to write to any auxillary
+	register of ARC700 via JTAG.
+	(arc_jtag_write_aux_reg): New function. Add to write to any
+	auxillary register of ARC700 via JTAG.
+	(read_mem): New function. Add to read 4 bytes from memory.
+	(write_mem): New function. Add to write 4 bytes at a specified
+	memory location.
+	(arc_jtag_write_chunk): New function. Add to write to a stream of
+	data starting from the specified memory location. This function
+	makes use of speacial feature supported by ARC-JTAG for streaming
+	data.
+	(arc_jtag_read_chunk): New function. Add to read a stream of
+	data starting from the specified memory location. This function
+	makes use of speacial feature supported by ARC-JTAG for streaming
+	data. 
+	(arc_jtag_open): New function. Add to provide target specific open
+	function for GDB backend. This function sets port permissions and
+	resets JTAG state machine.
+	(arc_jtag_close): New function. Add to provide target specific
+	close function to GDB backend.
+	(arc_jtag_wait): New function. Add to poll the status32 register
+	of ARC700 till the processor is halted.
+	(_initialize_arc_jtag_ops): New function. Add to initialize
+	function pointers for structure arc_jtag_ops.
+	* gdb/config/arc/embed.mt (TDEPFILES): Add entry for
+	arc-jtag-ops.o
+	
+2005-04-20  Sameer Dhavale  <sameer.dhavale@codito.com>
+
+	PR arcgdb/1241
+	* target.c (target_read_memory_partial): Correct the handling of
+	variable err depending on the value returned
+	target_xfer_partial().
+	(target_write_memory_partial): Correct the handling of
+	variable err depending on the value returned
+	target_xfer_partial(). 
+??? patch sites don't exist any more, need to check for regression.
+
+2005-04-19  Soam Vasani <soam.vasani@codito.com>
+
+	* arc-jtag.h (enum arc700_jtag_regnums): Add debug register.
+	* arc-jtag-tdep.c (arc_jtag_register_name): Ditto.
+
+2005-04-19  Soam Vasani <soam.vasani@codito.com>
+
+	* arc-jtag.h: New file, defines arc700_jtag_regnums.
+
+2005-04-19  Soam Vasani <soam.vasani@codito.com>
+
+	* arc-tdep.c (ARC_ILINK1_PSEUDO_REGNUM, ARC_ILINK2_PSEUDO_REGNUM,
+	ARC_ERET_PSEUDO_REGNUM, ARC_STATUSL1_PSEUDO_REGNUM,
+	ARC_STATUSL2_PSEUDO_REGNUM, ARC_ERSTATUS_PSEUDO_REGNUM): Move to
+	arc-tdep.h.
+	(arc_pseudo_register_read, arc_pseudo_register_write,
+	arc_print_registers_info): Move to arc-linux-tdep.c and
+	arc-jtag-tdep.c.
+	(arc_register_name): Registers are split into 3 classes: the
+	registers common to both linux and jtag; registers available only
+	in one of the two targets; and pseudo registers.  Common registers
+	and pseudo-registers have their names defined here; for other
+	registers, call tdep->register_name.
+	(arc_register_reggroup_p): Call tdep->register_reggroup_p, for the
+	target-specific registers.
+	(arc_sigtramp_frame_prev_register): Use
+	tdep->pc_regnum_in_sigcontext rather than ARC_RET_REGNUM directly.
+	(arc_gdbarch_init): Do not assume OSABI = Linux.  Instead, get the
+	OSABI from the new CONFIG_OSABI macro in tm-<target>.h file.
+	Move to arc-linux-tdep.c and arc-jtag-tdep.c: Set
+	gdbarch_num_regs, gdbarch_pc_regnum, gdbarch_pseudo_register_read,
+	gdbarch_pseudo_register_write, gdbarch_print_registers_info.
+	Call CONFIG_INIT_TDEP, which is a macro defined in tm-<target>.h.
+	
+	* arc-linux-tdep.c: (enum arc700_linux_regnums): Moved here from
+	arc-tdep.h, so that arc-tdep.c cannot see them.  Contains the
+	registers that linux makes up, but do not actually exist on the
+	processor.  Also, change ARC_RET_REGNUM such that it is after all
+	the common registers.
+	(arc_linux_register_name): Names of the arc700_linux_regnums.
+	(arc_linux_pseudo_register_read): Moved from arc-tdep.c.  Here
+	we'll use orig_r8 to get the pseudo-registers.
+	(arc_linux_pseudo_register_write): Moved from arc-tdep.c.
+	(arc_linux_print_registers_info): Moved from arc-tdep.c.  Register
+	sets are different for different targets.
+	(arc_linux_sc_reg_offset): ARC_RET_REGNUM was changed, so changed
+	this appropriately.
+	(arc_linux_init_abi): Set tdep->pc_regnum_in_sigcontext to
+	ARC_RET_REGNUM (see comment in arc-tdep.h).  Set
+	tdep->register_name to arc_linux_register_name.  
+	And moved from arc-tdep.c: Set gdbarch_num_regs,
+	gdbarch_pc_regnum, gdbarch_pseudo_register_read,
+	gdbarch_pseudo_register_write, gdbarch_print_registers_info.
+	(arc_linux_register_reggroup_p): Register groups for linux-only
+	registers.
+
+	* arc-jtag-tdep.c: New file.  Define the breakpoint intruction,
+	register_name, pseudo register read/write, register_reggroup_p,
+	and print_registers_info.
+
+	* arc-tdep.h (enum arc700_regnums): Remove linux-only regnums like
+	ARC_RET_REGNUMS.
+	(ARC_ILINK1_PSEUDO_REGNUM, ARC_ILINK2_PSEUDO_REGNUM,
+	ARC_ERET_PSEUDO_REGNUM, ARC_STATUSL1_PSEUDO_REGNUM,
+	ARC_STATUSL2_PSEUDO_REGNUM, ARC_ERSTATUS_PSEUDO_REGNUM): Moved
+	from arc-tdep.c.  Though the regnums are different across targets
+	for these registers, the macros are same because the regnums are
+	define in terms of NUM_REGS.
+	(struct gdbarch_tdep): New fields: pc_regnum_in_sigcontext,
+	register_reggroup_p.
+
+	* config/arc/embed.mt (TDEPFILES): Add arc-jtag-tdep.o to this
+	list.	
+
+	* config/arc/tm-embed.h (CONFIG_OSABI, CONFIG_INIT_TDEP): New macros.
+	* config/arc/tm-linux.h (CONFIG_OSABI, CONFIG_INIT_TDEP): Ditto.
+	
+	* gdbserver/linux-arc-low.c (arc_regmap): ARC_RET_REGNUM was
+	changed in GDB, change this appropriately.
+	* regformats/reg-arc.dat: Ditto.
+	
+2005-04-12  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arc-jtag.c: Add copyright, add comments to each of the 
+	functions explaining their role. 
+
+2005-04-08  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arc-tdep.c(arc_print_float_info): New function. 
+	  (gdbarch_init):Initialize gdbarch_print_float_info.
+
+2005-04-07  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	PR arcgdb/1198
+	* arc-tdep.c(arc_push_dummy_call):Correct handling for
+	structures.Move initial assignment of structure address
+	above initialization.
+	(arc_frame_align): Align frame to natural boundary.
+
+2005-04-06  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	PR arcgdb/1194 
+	* arc-tdep.c(arc_push_dummy_call):Correct limit check. The ARC has
+	8 parameter registers.
+	* arc-tdep.h(enum arc700_regnums):Add ARC_ARG7_REGNUM.
+
+2005-04-04  Sameer Dhavale <sameer.dhavale@codito.com>
+
+	PR arcgdb/1189
+	* arc-jtag.c(): Add
+	  (struct arc_jtag_ops): New structure. Add to support
+	arcjtag target operations.
+	  (arc_jtag_open): New function. Add for initializations.
+	  (arc_jtag_attach): New function. Add for attaching to already
+	  running targets.
+	  (arc_jtag_detach): New function. Add for detaching from a
+	  target.
+	  (arc_jtag_resume): New function. Make the inferior to resume
+	  execution.
+	  (arc_jtag_wait): New function.
+	  (arc_jtag_fetch_regs): New function. Put values in register
+	  cache.
+	  (arc_jtag_store_regs): New function.
+	  (arc_jtag_prepare_to_store): New function.
+	  (arc_jtag_xfer_memory): New function.
+	  (arc_jtag_files_info): New function.
+	  (arc_jtag_insert_breakpoint): New function.
+	  (arc_jtag_remove_breakpoint): New function.
+	  (arc_jtag_kill): New function.
+	  (arc_jtag_load): New function.
+	  (arc_jtag_create_inferior): New function.
+	  (arc_jtag_mourn_inferior): New function.
+	  (arc_jtag_thread_alive): New function.
+	  (arc_jtag_stop): New function.
+	  (init_arc_jtag_ops): New function. Initialize jtag_target_ops to
+	  values appropriate for arcjtag target.
+	  (_initialize_arc_jtag): New function. Add a new target to gdb.
+	* config/arc/embed.mt: Add change to include arc-jtag.o so that
+	new target should be automatically built with arc-elf32.
+	 
+2005-04-03  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	PR arcgdb/1185
+	* arc-tdep.c(arc_write_pc): Remove. 
+	  (arc_gdbarch_init): Remove initialization of write_pc.
+	* arc-linux-tdep.c(arc700_linux_write_pc): New function . Add
+	fix for orig_r8 hack.
+	 (arc_linux_init_abi): Set gdbarch_init to arc700_linux_write_pc.
+
+2005-04-03  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	PR arcgdb/1184
+	* arc-tdep.h(struct gdbarch_tdep): Add members breakpoint_insn
+	and breakpoint_size.
+	* arc-tdep.c(arc_breakpoint_from_pc): Return gdbarch_tdep value
+	for software bp instructions to be used. 
+	* arc-linux-tdep.c(arc_linux_init_abi): Initialize the tdep for 
+	arc700_linux_default_breakpoints. 
+	  arc700_linux_breakpoint_insn:New breakpoint insn for ARC700
+	  linux.
+	  arc700_linux_breakpoint_size:New breakpoint size for ARC700 
+	  linux.
+
+2005-04-03  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arc-tdep.c(arc_linux_write_pc):Correct comment for orig_r8.
+
+2005-04-02  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* version.in: should have been 20050401.
+
+2005-04-01  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* version.in: Bump up version for release.
+	
+2005-04-01  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+	
+	* ChangeLog.codito: Remove more spurious entries.
+
+	PR arcgdb/1175
+	* arc-tdep.c(arc_push_dummy_call): New function.
+	  (push_stack_item):New function.
+	  (pop_stack_item):New function.
+	  (arc_add_reggroups_p):Register system_reggroup.
+	  (arc_register_reggroup_p):Add orig_r8 to system_reggroup.
+	  (arc_linux_write_pc):	Set orig_r8 to -3 to work correctly 
+	  dummy frames and signal handlers. Fixes failures in signals.exp.
+	  (arc_gdbarch_init):Set dummy call to use arc_push_dummy_call. 
+	  Set breakpoint for dummy code at entry point.
+	  Register arc_linux_write_pc.
+	* ChangeLog.codito: Remove spurious Changelog entry.
+
+2005-04-01  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arc-tdep.h: Add enum arc700_regnums for ARC register types. 
+
+
+
+2005-03-30  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	PR arcgdb/1172
+	* arc-tdep.c(arc_scan_prologue): Skip over argument save
+	registers. 
+
+2005-03-28  Ramana Radhakrishnan  <ramana@codito.com>
+
+<	* arc-tdep.c: Add contribution tag. 
+	  (printFrameInfo): Conditionally compile with ARC_DEBUG.
+	  (printInsnState): Likewise.
+	  (UPDATESTACKSPACE): Correct for variadic args. 
+	  (PUSHBLINKFI): Correct for variadic args. 
+	  (ISSUBSPFI): Update for mixed code.
+	  (arc_scan_prologue): Update prologue description and correct.
+	  (arc_scan_prologue): Clean up declarations. 
+	  Handle callee saves, Handle 16 bit ARCompact insns.
+	
+
+2005-03-21  Soam Vasani  <soam.vasani@codito.com>
+
+	* arc-tdep.c (arc_gdbarch_init): Assume OSABI = Linux for now.
+	Call gdbarch_init_osabi.
+	* arc-linux-tdep.c (_initialize_arc_linux_tdep): Pass machine = 0
+	to gdbarch_register_osabi.
+
+2005-03-20  Soam Vasani <soam.vasani@codito.com>
+
+	PR gdb/1098
+	* arc-tdep.c(arc_cannot_store_register): Don't print warning.
+	  (arc_register_reggroup_p): Remove read-only registers from 
+	  save/restore reggroups.
+
+2005-03-17  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arc-linux-tdep.c:Add copyright notice. 
+
+2005-03-17  Soam Vasani <soam.vasani@codito.com>
+
+	* gdb/arc-tdep.c: Cleanup and remove warnings.
+	* gdb/arc-linux-tdep.c: Ditto.
+
+2005-03-17  Soam Vasani <soam.vasani@codito.com>
+
+	* gdb/arc-linux-tdep.c (arc_sigtramp_insn): Defined.
+	  (arc_linux_sigtramp_p): Defined: check if PC is in a signal 
+	  trampoline.
+	  (arc_linux_sigcontext_addr): Defined: return the address of the
+	  sigcontext structure.
+	  (arc_linux_sc_reg_offset): Defined: mapping from regnum to
+	  sigcontext offset.
+	  (arc_linux_linux_init_abi): Defined: add stuff to gdbarch->tdep.
+	* gdb/arc-tdep.h (ARC_PC_REGNUM): Replaced by ARC_RET_REGNUM.
+	* gdb/arc-tdep.c (ARC_PC_REGNUM): Replace all references by either
+	  PC_REGNUM or ARC_RET_REGNUM.
+	  (arc_unwind_pc): Call the unwinder with PC_REGNUM instead of
+	  ARC_RET_REGNUM.  The unwinder will decide what register to give
+	  for PC_REGNUM, because PC_REGNUM itself is not a real register.
+	  (arc_sigtramp_frame_cache, arc_sigtramp_frame_this_id, 
+	  arc_sigtramp_frame_prev_register, arc_sigtramp_frame_unwind,
+	  arc_sigtramp_frame_sniffer): Defined.
+	  (arc_gdbarch_init): Append arc_sigtramp_frame_sniffer.
diff --git a/gdb/arc-jtag-ops.c b/gdb/arc-jtag-ops.c
new file mode 100644
index 0000000..0a237f6
--- /dev/null
+++ b/gdb/arc-jtag-ops.c
@@ -0,0 +1,1229 @@
+/* Target dependent code for ARC700, for GDB, the GNU debugger.
+
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Contributed by Codito Technologies Pvt. Ltd. (www.codito.com)
+
+   Authors: 
+      Sameer Dhavale <sameer.dhavale@codito.com>
+      Soam Vasani <soam.vasani@codito.com>
+
+   This file is part of GDB.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+
+#include <stdio.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <sys/io.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <assert.h>
+#include "arc-jtag-ops.h"
+#include "gpio.h"
+#include <signal.h>
+#include <defs.h>
+#include <sys/ioctl.h>
+#include "arc-tdep.h"
+#define printf printf_filtered
+
+
+unsigned int arcjtag_retry_count = 50;
+
+
+/* ------------------------------------ */
+/*         For ARC jtag Cable           */
+/*                                      */
+/* Pin no.  Signal           Word , Bit */
+/*                                      */
+/* - 	    TRST 	                */
+/* 8 	    TMS 	     Data 6     */
+/* 1 	    TCK 	     Control 0  */
+/* 9 	    TDI 	     Data 7     */
+/* 13 	    TDO 	     Status 4   */
+
+
+#define JTAG_TRST 0x00  /* not there */
+#define JTAG_TMS  0x40  /* data port */
+#define JTAG_TCK  0x01  /* control port. Driven Low. */
+
+#define JTAG_TDI  0x80  /* data port */
+#define JTAG_TDO  0x10  /* status port */
+
+/* ------------------------------------ */
+
+/* */
+#define A4_HALT_VALUE 0x02000000
+#define ARC700_HALT_VALUE 0x1
+
+
+/* Parallel port i/o addr. (LPT1) */
+#define DATA_PORT    0x378
+#define STATUS_PORT  0x379
+#define CONTROL_PORT 0x37A
+
+
+unsigned char tapc_dataport=0, tapc_statusport=0, tapc_controlport=0x1;
+int fd;
+struct GPIO_ioctl jtag_ioctl;
+sigset_t block_mask;
+
+enum AA3SSPinState
+  {
+    READ_FROM_AA3 = 0,
+    WRITE_TO_AA3 = 1
+  };
+enum AA3SSPinState rw_flag; 
+
+
+
+struct jtag_ops arc_jtag_ops;
+static enum ARCProcessorVersion ARCProcessor = UNSUPPORTED;
+
+
+/* Sanity check to give error if jtag is not opened at all. */
+
+static void 
+check_and_raise_error_if_jtag_closed (void)
+{
+  if( arc_jtag_ops.jtag_status == JTAG_CLOSED )
+    error ("JTAG connection is closed. Use target arcjtag first\n");
+}
+
+
+/* Initializations for GPIO interface */
+static int
+gpio_setup (void)
+{
+  fd=open("//dev//gpio",O_RDWR);
+  ioctl(fd,GPIO_IOC_HARDRESET);
+  ioctl(fd,GPIO_IOC_SET_PORT_BASE,0x378);
+  jtag_ioctl.inlen=0;
+  jtag_ioctl.outlen=0;
+  jtag_ioctl.inbuf=(unsigned char *)xmalloc(2*sizeof(unsigned char));
+  jtag_ioctl.outbuf=(unsigned char *)xmalloc(2*sizeof(unsigned char));
+  return 0;
+}
+
+void gpio_write(unsigned int port, unsigned char *data)
+{
+    jtag_ioctl.inlen=2;
+    jtag_ioctl.inbuf[1]=*data;
+    switch(port)
+    {
+    case DATA_PORT:
+	jtag_ioctl.inbuf[0]=0;
+	break;
+
+    case STATUS_PORT:
+	jtag_ioctl.inbuf[0]=1;
+	break;
+
+    case CONTROL_PORT:
+	jtag_ioctl.inbuf[0]=2;
+	break;
+	    
+    default:
+	error("Invalid port\n");
+    }
+
+ 
+    if(ioctl(fd,GPIO_IOC_DO_IO,&jtag_ioctl))
+	error("Failure writing to port 0x%x\n",port);
+
+}
+
+
+unsigned char gpio_read(unsigned int port)
+{
+    //jtag_ioctl.inbuf[1]=tapc_statusport;
+    jtag_ioctl.inlen=2;
+    jtag_ioctl.outlen=1;
+
+    switch(port)
+    {
+    case DATA_PORT:
+	jtag_ioctl.inbuf[0]=0x80;
+	break;
+
+    case STATUS_PORT:
+	jtag_ioctl.inbuf[0]=0x81;
+	break;
+
+    case CONTROL_PORT:
+	jtag_ioctl.inbuf[0]=0x82;
+	break;
+	    
+    default:
+	error("Invalid port\n");
+    }
+    
+    if(ioctl(fd,GPIO_IOC_DO_IO,&jtag_ioctl))
+	error("Failure reading from port 0x%x\n",port);
+	  
+    return jtag_ioctl.outbuf[0];
+
+
+}
+
+/* Helper functions for setting
+   TMS / TCK / TDI. Valid inputs
+   are 1 and 0. The tapc_<tms/tck/tdi> 
+   functions set the internal values 
+   to be written out to the port. The 
+   final values are written only by doing 
+   the pulse.
+ */
+
+static void
+tapc_set_tms (char x)
+{
+    if(x)
+	tapc_dataport |= JTAG_TMS;
+    else
+	tapc_dataport &= ~JTAG_TMS;
+
+    /* outb(tapc_dataport, DATA_PORT); */
+    gpio_write(DATA_PORT,&tapc_dataport);
+}
+
+
+/* Set TCK. */
+static void
+tapc_set_tck (char x)
+{
+  /* active low. The clock is active low. */
+    if(!x) 
+  	tapc_controlport |= JTAG_TCK;
+    else
+	tapc_controlport &= ~JTAG_TCK;
+    
+    if(rw_flag == READ_FROM_AA3)
+      tapc_controlport |= 0x4; 
+    else
+      tapc_controlport &= ~(0x4); 
+      
+    /* outb(tapc_controlport, CONTROL_PORT); */
+    gpio_write(CONTROL_PORT,&tapc_controlport);
+}
+
+
+static void
+tapc_set_tdi (char x)
+{
+    if(x)
+	tapc_dataport |= JTAG_TDI;
+    else
+	tapc_dataport &= ~JTAG_TDI;
+    
+    /* outb(tapc_dataport, DATA_PORT); */
+    gpio_write(DATA_PORT,&tapc_dataport);
+}
+
+/* Unused function clockdelay. Why not add a command
+ that allows the user to set the clock delay ? */
+
+static void
+clockdelay (void)
+{
+    int i;
+    //for (i=0; i<10; ++i)
+    
+    //   usleep(0);
+}
+
+/* Clock the JTAG on the ARC platform. */
+static void
+tapc_pulse (void)
+{
+    /* Control 0 bit is active low */
+    unsigned char temp;
+    assert( (tapc_controlport & JTAG_TCK) );  // clock should be zero on entry
+   
+    /* outb(tapc_controlport & ~JTAG_TCK, CONTROL_PORT); */
+    temp = tapc_controlport & ~JTAG_TCK;
+    gpio_write(CONTROL_PORT,&temp);
+   /*  outb(tapc_controlport, CONTROL_PORT); */
+    gpio_write(CONTROL_PORT,&tapc_controlport);
+    
+}
+
+/* All the JTAG state machine handlers.  */
+
+/* Reset the TAPC controller on the JTAG. 
+ */
+static void
+tapc_reset (void)
+{
+    /* from any state, these many ones should get us into "test-logic reset" 
+     */
+    tapc_set_tms(1);
+    tapc_set_tck(0);  /* want rising edge */
+    tapc_pulse();
+    tapc_pulse();
+    tapc_pulse();
+    tapc_pulse();
+    tapc_pulse();
+    tapc_pulse();
+}
+
+/* Set the tms to the value of the bit and 
+   clock the jtag. */
+
+static void
+tapc_tms (char x)
+{
+    tapc_set_tms(x);
+    tapc_pulse();
+}
+
+/* Read bit from the TDO of the JTAG. */
+static char
+tapc_readbit (void)
+{
+    if(gpio_read(STATUS_PORT) & JTAG_TDO)
+	return 1; 
+    else
+	return 0;
+}
+
+
+/* Interface functions that use the below mentioned 
+   JTAG state machine handler functions. 
+*/
+
+/* Shift one bit out on the JTAG TDI. */
+static char
+tapc_shiftbit (char x)
+{
+    char read;
+
+    //printf("tapc_shiftbit: Shifted %d\n", x);
+
+    read = tapc_readbit();    
+    tapc_set_tdi(x);
+    tapc_pulse();
+
+    return read;
+}
+
+
+/*
+ * Shift N bits from to_write into TDI, and out from TDO into read.
+ *
+ * If msb_first=0, shift LSB first, starting from to_write[0], to_write[1],
+ * etc.
+ 
+ * If msb_first=1, shift to_write[-1] MSB first, then to_write[-2] etc.
+ *
+ * Must be called in Shift DR/IR state.
+ * Leaves in Exit1 DR/IR state.
+ */ 
+static void
+tapc_shiftnbits (int n, 
+		unsigned char *to_write, 
+		unsigned char *read, 
+		char msb_first)
+{
+    unsigned char outbyte, inbyte;
+    int nbytes = (n-1)/8 + 1,limit=8;
+    int i, j;
+
+    for(i=0; i < nbytes; ++i)
+    {
+	if(msb_first)
+	    outbyte = to_write[-1-i];
+	else	   
+	    outbyte = to_write[i];
+
+	inbyte = 0;
+	/* should write a maximum of 8 bits */
+	if(i == nbytes-1)
+	    limit = ((n-1) % 8) + 1;  
+	
+	for(j = 0; j < limit; ++j)
+	{
+	    unsigned char outbit, inbit;
+
+	    if(msb_first)
+		outbit = !!(outbyte & 0x80);
+	    else
+		outbit = outbyte & 1;
+	    /* the last bit of the last byte */
+	    /* transition to EXIT-1 state before last bit */
+	    if((i == nbytes-1)&&(j == limit-1)) 
+	      tapc_set_tms(1); 
+	    
+	    inbit = tapc_shiftbit(outbit);
+
+	    if(msb_first)
+	      {
+		inbyte |= (inbit << (7-j));
+		outbyte <<= 1;
+	      }
+	    else
+	      {
+		inbyte |= inbit << j;
+		outbyte >>= 1;
+	    }
+	}
+
+	//tapc_tms(1);
+	if(msb_first)
+	    read[-1-i] = inbyte;
+	else
+	    read[i] = inbyte;
+    }
+}
+
+
+/* Read the JTAG status register. This indicates
+   the status of the JTAG for the user. 
+*/
+static unsigned int
+read_jtag_status_reg (void)
+{
+    unsigned int wr, rd;
+    int x;
+    //rw_flag=0;
+    //tapc_tms(0); // runtest/idle
+    tapc_tms(1); // select dr
+    tapc_tms(1); // select ir
+    tapc_tms(0); // capture ir
+    tapc_tms(0); // shift ir
+
+    wr = 0x8;    // IR = status register
+
+    tapc_shiftnbits(4, (unsigned char *)&wr, (unsigned char*)&rd, 0);
+
+    
+    
+    // goto shift DR
+    tapc_tms(1); // update ir
+    //tapc_tms(0); // runtest/idle
+    tapc_tms(1); // select dr
+    tapc_tms(0); // capture dr
+    tapc_tms(0); // shift dr
+
+    rd = 0;
+
+    // read 1 bit, if it is zero then keep reading
+    rd = tapc_shiftbit(0);
+    if (rd)
+	return rd; 
+
+    rd |= tapc_shiftbit(0) << 1;
+    if (rd)
+	return rd;
+    
+    rd |= tapc_shiftbit(0) << 2;
+
+    /* the last bit is optional */
+    /*rd |= tapc_shiftbit(0) << 3;*/
+    
+    return rd;    
+}
+
+
+/* Interpret the status message. */
+static void
+print_jtag_status_reg_val (unsigned int status)
+{
+    int i ;
+    char * messages [] = { "Stalled" , "Failure", "Ready", "PC Selected" };
+    for(i=0;i<=3;i++)
+    {
+	printf_filtered("%s %s \t",(status & 1)?"":"Not",messages[i]);
+	status = status >> 1;
+    }
+    printf_filtered("\n");
+}
+
+
+
+/* Write a JTAG Command to a JTAG register. 
+   enter in update dr/ir state
+   or Test-Logic-Reset.
+   exit in update dr
+*/
+static void
+write_jtag_reg (char regnum, unsigned int data, int ndatabits)
+{
+    unsigned int wr=0,rd=0;
+    rw_flag = WRITE_TO_AA3 ;
+    //    tapc_tms(0); // runtest/idle
+    tapc_tms(1); // select dr
+    tapc_tms(1); // select ir
+    tapc_tms(0); // capture ir
+    tapc_tms(0); // shift ir
+
+		
+    tapc_shiftnbits(4, (unsigned char *)&regnum, (unsigned char *)&rd, 0);
+
+    
+    tapc_tms(1); // update ir
+
+    tapc_tms(1); // select dr
+    tapc_tms(0); // capture dr
+    tapc_tms(0); // shift dr
+
+    tapc_shiftnbits(ndatabits, (unsigned char *)&data, 
+		    (unsigned char *)&rd, 0);
+    tapc_tms(1); // update dr
+}
+	    
+
+// enter in update dr/ir state
+// exit in update dr
+static unsigned int
+read_jtag_reg (char regnum, int ndatabits)
+{
+    unsigned int wr=0x0,rd=0;
+    rw_flag = READ_FROM_AA3;
+    //    tapc_tms(0); // runtest/idle
+    tapc_tms(1); // select dr
+    tapc_tms(1); // select ir
+    tapc_tms(0); // capture ir
+    tapc_tms(0); // shift ir
+
+    tapc_shiftnbits(4, (unsigned char *)&regnum, (unsigned char *)&rd, 0);
+    tapc_tms(1); // update ir
+
+    /* JTAG registers can be read without going to run-test/idle state.
+       
+       Doing tapc_tms(0) will take us to run-test/idle state.
+       This will make JTAG perform the transaction as per TCR.
+       We dont want this. 
+    */
+    //    tapc_tms(0); // runtest/idle
+    tapc_tms(1); // select dr
+    tapc_tms(0); // capture dr
+    tapc_tms(0); // shift dr
+
+    tapc_shiftnbits(ndatabits, (unsigned char *)&wr, (unsigned char *)&rd, 0);
+    tapc_tms(1); // update dr
+
+    return rd;
+}
+
+
+
+    
+    
+
+
+
+static int
+arc_jtag_read_core_reg (unsigned int regnum, unsigned int *readbuf)
+{
+    unsigned int rd, wr, data, i;
+    check_and_raise_error_if_jtag_closed();
+    tapc_reset();
+    tapc_tms(0);//run-test idle
+    write_jtag_reg(0xA, regnum, 32);//update dr
+
+    
+
+    // Setup instruction register to 0x9 indicating
+    // a JTAG instruction is being downloaded.
+    // jtag transaction command reg = 0x5 (read core reg)
+    write_jtag_reg(0x9, 0x5, 4);//update dr
+
+    /* Perform the transaction.
+     */
+    tapc_tms(0); // run-test idle
+    
+    // poll the status
+
+    for (i=0;i<arcjtag_retry_count;i++)
+    {
+	unsigned int status = read_jtag_status_reg();
+	//if( !(status & 1) && (status & 4) )
+	if(status == 4)
+	    break;
+	if(status == 2)
+	    return JTAG_READ_FAILURE;
+	tapc_tms(1);//exit1-dr
+	tapc_tms(1);//update-dr
+	/* Do not redo the transaction. Pause and re-try.
+	 */
+	//tapc_tms(0);//run-test-idle
+    }
+    if (i==arcjtag_retry_count)
+      return JTAG_READ_FAILURE;
+
+    /* JTAG status register leaves us in Shift DR */
+    tapc_tms(1); /* Move to Exit-1 DR */
+    tapc_tms(1); /* Move to Update DR */
+    
+    // data = jtag data reg
+    data = read_jtag_reg(0xB, 32);
+
+    *readbuf = data;
+    
+    return sizeof(data);
+}
+
+static int
+arc_jtag_write_core_reg (unsigned int regnum, unsigned int data)
+{
+    unsigned int rd, wr, i;
+
+    check_and_raise_error_if_jtag_closed();
+    tapc_reset();
+    tapc_tms(0);//run-test idle
+
+    // data = jtag data reg
+    write_jtag_reg(0xB, data, 32);//update dr
+
+    // jtag addr register = regnum:
+    write_jtag_reg(0xA, regnum, 32);//update dr
+    
+    
+
+    // jtag transaction command reg = 0x1(write core reg)
+    write_jtag_reg(0x9, 0x1, 4);//update dr
+
+    /* Perform the transaction.
+     */
+    tapc_tms(0); // run-test idle
+    
+    for (i=0;i<arcjtag_retry_count;i++)
+    {
+      unsigned int status = read_jtag_status_reg();
+      	if(status == 4)
+	    break;
+	if(status == 2)
+	    return JTAG_WRITE_FAILURE;
+	tapc_tms(1);//exit1-dr
+	tapc_tms(1);//update-dr
+	/* Do not redo the transaction. Pause and re-try.
+	 */
+	//tapc_tms(0);//run-test-idle
+    }
+    if (i==arcjtag_retry_count)
+      return JTAG_READ_FAILURE;
+
+    tapc_tms(1);//exit1-dr
+    tapc_tms(1);//update-dr
+    /* This should have been done earlier i.e. before
+       reading the JTAG status register.
+     */
+    //tapc_tms(0);//rn-test-idle
+    return sizeof(data);
+}
+
+static int
+arc_jtag_read_aux_reg (unsigned int regnum, unsigned int *readbuf)
+{
+    unsigned int rd, wr, data, i;
+    if(arc_jtag_ops.arc_jtag_state_machine_debug)
+      printf_filtered("\nEntered arc_jtag_read_aux_reg()\
+         \n Regnum:%d \n",regnum);
+    check_and_raise_error_if_jtag_closed();
+    check_and_raise_error_if_jtag_closed();
+    tapc_reset();
+    tapc_tms(0);//run-test idle
+    write_jtag_reg(0xA, regnum, 32);//update dr
+
+
+
+    // Setup instruction register to 0x9 indicating
+    // a JTAG instruction is being downloaded.
+    // jtag transaction command reg = 0x6 (read aux reg)
+    write_jtag_reg(0x9, 0x6, 4);//update dr
+
+    /* Perform the transaction.
+     */
+    tapc_tms(0); // run-test idle
+
+    // poll the status
+
+    for (i=0;i<arcjtag_retry_count;i++)
+    {
+	unsigned int status = read_jtag_status_reg();
+	
+	if(status == 4)
+	    break;
+	if(status == 2)
+	    return JTAG_READ_FAILURE;
+	tapc_tms(1);//exit1-dr
+	tapc_tms(1);//update-dr
+	/* Do not redo the transaction. Pause and re-try.
+	 */
+	//tapc_tms(0);//run-test-idle
+
+    }
+    if (i==arcjtag_retry_count)
+      return JTAG_READ_FAILURE;
+
+
+/*     JTAG status register leaves us in Shift DR */
+    tapc_tms(1); /* Move to Exit-1 IR */
+    tapc_tms(1); /* Move to Update IR */
+    
+    // data = jtag data reg
+    data = read_jtag_reg(0xB, 32);
+    *readbuf = data;
+    if(arc_jtag_ops.arc_jtag_state_machine_debug)
+      printf(" Data: %d\n",data);
+    return sizeof(data);
+}
+
+static int
+arc_jtag_write_aux_reg (unsigned int regnum, unsigned int data)
+{
+    unsigned int rd, wr, i;
+    if(arc_jtag_ops.arc_jtag_state_machine_debug)
+      printf_filtered("\nEntered arc_jtag_write_aux_reg()\n Regnum:%d\nData:%d\n",regnum,data);
+    check_and_raise_error_if_jtag_closed();
+    tapc_reset();
+    tapc_tms(0);//run-test idle
+    
+    // data = jtag data reg
+    write_jtag_reg(0xB, data, 32);//update dr
+
+    // jtag addr register = regnum:
+    write_jtag_reg(0xA, regnum, 32);//update dr
+    
+    
+
+    // jtag transaction command reg = 0x2 (write aux reg)
+    write_jtag_reg(0x9, 0x2, 4);//update dr
+
+    /* Perform the transaction.
+     */
+    tapc_tms(0); // run-test idle
+
+    for (i=0;i<arcjtag_retry_count;i++)
+    {
+	unsigned int status = read_jtag_status_reg();
+	if(status == 4)
+	    break;
+	if(status == 2)
+	    return JTAG_WRITE_FAILURE;
+	tapc_tms(1);//exit1-dr
+	tapc_tms(1);//update-dr
+	/* Do not redo the transaction. Pause and re-try.
+	 */
+	//tapc_tms(0);//run-test-idle
+    }
+    if (i==arcjtag_retry_count)
+      return JTAG_READ_FAILURE;
+
+	tapc_tms(1);//exit1-dr
+	tapc_tms(1);//update-dr
+	/* This should have been done earlier i.e. before
+	   reading the JTAG status register.
+	*/
+	//tapc_tms(0);//run-test-idle
+	return sizeof(data);
+}
+
+
+static int
+read_mem (unsigned int addr, unsigned int *readbuf)
+{
+    unsigned int rd, wr, data, i;
+
+    rw_flag = READ_FROM_AA3;
+    if(arc_jtag_ops.arc_jtag_state_machine_debug)
+      printf_filtered("\nEntered read_mem() 0x%x\n",addr);
+    // jtag addr register = regnum:
+    tapc_reset();
+    tapc_tms(0);//run-test idle
+    write_jtag_reg(0xA, addr, 32);//update dr
+
+    
+
+    // Setup instruction register to 0x9 indicating
+    // a JTAG instruction is being downloaded.
+    // jtag transaction command reg = 0x5 (read core reg)
+    write_jtag_reg(0x9, 0x4, 4);//update dr
+
+    /* Perform the transaction.
+     */
+    tapc_tms(0); // run-test idle
+
+    // poll the status
+
+    for (i=0;i<arcjtag_retry_count;i++)
+    {
+	unsigned int status = read_jtag_status_reg();
+	if(status == 4)
+	    break;
+	if(status == 2)
+	    return JTAG_READ_FAILURE;
+	tapc_tms(1);//exit1-dr
+	tapc_tms(1);//update-dr
+	/* Do not redo the transaction. Pause and re-try.
+	 */
+	//tapc_tms(0); // run-test-idle
+    }
+    if (i==arcjtag_retry_count)
+      return JTAG_READ_FAILURE;
+
+    /* JTAG status register leaves us in Shift DR */
+    tapc_tms(1); /* Move to Exit-1 DR */
+    tapc_tms(1); /* Move to Update DR */
+    
+    // data = jtag data reg
+    data = read_jtag_reg(0xB, 32);
+    *readbuf = data;
+    if(arc_jtag_ops.arc_jtag_state_machine_debug)
+    printf_filtered("\n Read rd =0x%x in read_mem",data);
+
+    return sizeof(data);
+}
+
+
+static int
+write_mem (unsigned int addr, unsigned int data)
+{
+    unsigned int rd, wr, i;
+    if(arc_jtag_ops.arc_jtag_state_machine_debug)
+      printf_filtered("\nEntered write_mem() to write 0x%x at 0x%x\n",data,addr);
+    tapc_reset();
+    tapc_tms(0);//run-test idle
+    
+    // data = jtag data reg
+    write_jtag_reg(0xB, data, 32);//update dr
+
+    // jtag addr register = regnum:
+    write_jtag_reg(0xA, addr, 32);//update dr
+    
+    
+
+    // jtag transaction command reg = 0x0(write mem)
+    write_jtag_reg(0x9, 0x0, 4);//update dr
+
+    /* Perform the transaction.
+     */
+    tapc_tms(0); // run-test idle
+
+    for (i=0;i<arcjtag_retry_count;i++)
+    {
+	unsigned int status = read_jtag_status_reg();
+	if(status == 4)
+	    break;
+	if(status == 2)
+	    return JTAG_WRITE_FAILURE;
+	tapc_tms(1);//exit1-dr
+	tapc_tms(1);//update-dr
+	/* Do not redo the transaction. Pause and re-try.
+	 */
+	//tapc_tms(0);//run-tes-idle
+    }
+    if (i==arcjtag_retry_count)
+      return JTAG_READ_FAILURE;
+
+    tapc_tms(1);//exit1-dr
+    tapc_tms(1);//update-dr
+    /* This should have been done earlier i.e. before
+       reading the JTAG status register.
+     */
+    //tapc_tms(0);//run-test-idle
+    return sizeof(data);
+}
+
+
+static int 
+arc_jtag_write_chunk (unsigned int addr, unsigned int *write_buf, int len)
+{
+  unsigned int rd, wr;
+  unsigned int status;
+  check_and_raise_error_if_jtag_closed();
+    
+  rw_flag = WRITE_TO_AA3 ;
+  int i = 0;
+  int len_mod = len % 4;
+  len = len - len_mod;
+  
+  tapc_reset();
+  if(arc_jtag_ops.arc_jtag_state_machine_debug)
+    printf_filtered("Entered arc_jtag_write_chunk()......0x%x\n",*write_buf);
+  tapc_tms(0);//run-test idle
+  
+  // jtag addr register = regnum:
+  write_jtag_reg(0xA, addr, 32);//update dr
+  
+  
+  
+  // jtag transaction command reg = 0x0(write mem)
+  write_jtag_reg(0x9, 0x0, 4);//update dr
+  
+  while(len)
+    {
+      
+      // data = jtag data reg
+      write_jtag_reg(0xB, write_buf[i++], 32);//update dr
+      
+      /* Perform the transaction.
+       */
+      tapc_tms(0); // run-test idle
+      
+      
+      while(1)
+	{
+	  status = read_jtag_status_reg();
+	  if(status == 4)
+	    break;
+	  if(status == 2)
+	    return (i-1) * 4;
+
+	  tapc_tms(1);//exit1-dr
+	  tapc_tms(1);//update-dr
+	  /* Do not redo the transaction. Pause and re-try.
+	   */
+	  //tapc_tms(0);//run-tes-idle
+	}
+      
+      tapc_tms(1);//exit1-dr
+      tapc_tms(1);//update-dr
+      /* This should have been done earlier i.e. before
+	 reading the JTAG status register.
+      */
+      //tapc_tms(0);//run-test idle
+      len = len - 4;
+    }
+
+  if(arc_jtag_ops.arc_jtag_state_machine_debug)
+    printf_filtered("leaving arc_jtag_write_chunk() with return value %d",i*4);
+  
+  // added support for writing no of bytes those are not exact mutiple of four
+  
+  if(!len_mod)
+    return i*4;
+  else
+    {
+      
+      addr=addr+(i*4);
+      if(read_mem(addr,&rd)==JTAG_READ_FAILURE)
+	  return i*4;
+      if(arc_jtag_ops.arc_jtag_state_machine_debug)
+      printf_filtered("\nrd=0x%x and wr=0x%x\n",rd,write_buf[i]);
+
+      switch(len_mod)
+	{
+	  
+	case 1:
+	  wr = (rd & 0xffffff00)|(write_buf[i] & 0xff);
+	  break;
+	  
+	case 2:
+	  wr = (rd & 0xffff0000)|(write_buf[i] & 0xffff);
+	  break;
+	  
+	case 3:
+	  wr = (rd & 0xff000000)|(write_buf[i] & 0xffffff);
+	  break;
+	  
+	}
+      if(arc_jtag_ops.arc_jtag_state_machine_debug)
+	printf_filtered("\nwrite_mem writing 0x%x at 0x%x",wr,addr);
+      arc_jtag_write_chunk(addr,&wr,4);
+      return (i*4 + len_mod);
+    }
+  
+  
+}
+
+static int 
+arc_jtag_read_chunk (unsigned int addr, unsigned int *read_buf, int len)
+{
+    unsigned int rd, wr, data;
+    int i=0;
+    rw_flag = READ_FROM_AA3 ;
+    int len_mod=len%4;
+    len=len-len_mod;
+    if(arc_jtag_ops.arc_jtag_state_machine_debug)
+      printf_filtered("\nEntered arc_jtag_read_chunk() 0x%x\n",addr);
+    check_and_raise_error_if_jtag_closed();
+
+    // jtag addr register = regnum:
+    tapc_reset();
+    tapc_tms(0);//run-test idle
+    
+    write_jtag_reg(0xA, addr, 32);//update dr
+
+    
+    while(len)
+    {
+    // Setup instruction register to 0x9 indicating
+    // a JTAG instruction is being downloaded.
+    // jtag transaction command reg = 0x5 (read core reg)
+    write_jtag_reg(0x9, 0x4, 4);//update dr
+
+    /* Perform the transaction.
+     */
+    tapc_tms(0); // run-test idle
+
+    // poll the status
+
+    while(1)
+    {
+	unsigned int status = read_jtag_status_reg();
+	if(status == 4)
+	    break;
+	if(status == 2)
+	    return (i-1)*4;
+	tapc_tms(1);//exit1-dr
+	tapc_tms(1);//update-dr
+	/* Do not redo the transaction. Pause and re-try.
+	 */
+	//tapc_tms(0);//run-test-idle
+
+    }
+
+    /* JTAG status register leaves us in Shift DR */
+    tapc_tms(1); /* Move to Exit-1 DR */
+    tapc_tms(1); /* Move to Update DR */
+    
+    // data = jtag data reg
+    read_buf[i++] = read_jtag_reg(0xB, 32);// exits in Update DR
+    len= len-4;
+    //tapc_tms(0);/* Move to run-test-idle */
+
+    }
+
+    // added support for reading no of bytes those are not exact mutiple of four
+
+    if(!len_mod)
+	return i*4;
+    else
+    {
+        char *ptr = (char *)read_buf + i*4;
+	addr=addr+(i*4);
+	if(read_mem(addr,&rd)==JTAG_READ_FAILURE)
+	    return i*4;
+
+	switch(len_mod)
+	{
+	case 1:
+	    ptr[0] = rd & 0xff;
+	    break;
+
+	case 2:
+	    ptr[0] = rd & 0xff;
+	    ptr[1] = (rd>>8) & 0xff;
+	    break;
+
+	case 3:
+	    ptr[0] = rd & 0xff;
+	    ptr[1] = (rd>>8) & 0xff;
+	    ptr[2] = (rd>>16) & 0xff;
+	    break;
+	}
+
+	return ((i*4)+len_mod);
+	
+    }
+
+
+}
+
+
+
+/*
+ * Return the Processor Variant that is connected.
+ */
+int
+arc_get_architecture() 
+{
+  if (ARCProcessor == UNSUPPORTED) {
+    unsigned int value;
+
+    /* Read the Identity Register. */
+    if (arc_jtag_read_aux_reg(4, &value) == JTAG_READ_FAILURE)
+      error("Failure reading from auxillary IDENTITY register");
+
+    /* Get Identity Mask. */
+    value &= 0xff ;
+
+    if((value >= 0x30) && (value <= 0x3f))
+      ARCProcessor = ARC700;
+    else if((value >= 0x20) && (value <= 0x2f))
+      ARCProcessor = ARC600;
+    else if((value >= 0x10) && (value <= 0x1f))
+      ARCProcessor = A5;
+    else if ((value >= 0x00) && (value <= 0x0f)) 
+      ARCProcessor = A4;
+    else 
+      error("Unsupported Processor Version 0x%x\n", value);
+  }
+
+  return ARCProcessor;
+}
+
+
+
+static void 
+arc_jtag_open (void)
+{
+  int retval;
+  unsigned int read_status = 0;
+  sigaddset(&block_mask,SIGINT);
+  retval = gpio_setup();
+  if(retval != 0)
+    {
+      error("Unable to open JTAG Port .%s \n",(retval == EINVAL)?
+	    "Invalid Params":"Permission Denied" );
+      arc_jtag_ops.jtag_status = JTAG_CLOSED;
+      return ;
+    }
+  arc_jtag_ops.jtag_status = JTAG_OPENED;
+
+  tapc_reset();
+  //Writing debug bit of debug register
+  
+  do
+    {
+      /* Note: Reading the status/status32 register here to
+         check if halt bit is set*/
+      if (IS_A4) {
+	if(arc_jtag_read_aux_reg( 0x0, &read_status) == JTAG_READ_FAILURE)
+	  error("Failure reading auxillary register 0xA\n");
+	if(read_status & A4_HALT_VALUE)
+	  break;
+      }
+      else {
+	if(arc_jtag_read_aux_reg( 0xA, &read_status) == JTAG_READ_FAILURE)
+	  error("Failure reading auxillary register 0xA\n");
+	if(read_status & ARC700_HALT_VALUE)
+	  break;
+      }
+      printf_filtered("Processor running. Trying to halt.....\n");
+      if(arc_jtag_write_aux_reg(0x5,0x2)==JTAG_WRITE_FAILURE)
+	error("Failure writing 0x2 to auxillary register 0x5:debug register\n");
+    }while(1);
+  if (arc_jtag_ops.arc_jtag_state_machine_debug)
+    printf_filtered("Processor halted.....\n");
+
+}
+
+static void 
+arc_jtag_close (void)
+{
+  ARCProcessor = UNSUPPORTED;
+
+  if(arc_jtag_ops.jtag_status != JTAG_CLOSED)
+    {
+      tapc_reset();
+      /* closing file descriptor opened for communication with gpio driver */
+      close(fd);
+      if(arc_jtag_ops.arc_jtag_state_machine_debug)
+	printf_filtered("arc-jtag closed\n");
+      arc_jtag_ops.jtag_status = JTAG_CLOSED;
+    }
+
+}
+
+static void 
+arc_jtag_wait(void)
+{
+  unsigned int read_status;
+  check_and_raise_error_if_jtag_closed();
+  do
+    {
+      sigprocmask(SIG_BLOCK,&block_mask, NULL);
+
+      if (IS_A4) {
+	if(arc_jtag_read_aux_reg( 0x0, &read_status) == JTAG_READ_FAILURE)
+	  error("Failure reading auxillary register 0x0\n");
+	//FIXMEA:    if(debug_arc_jtag_target_message)
+	//      printf_filtered ("\n Read Status: 0x%x,%d\n", read_status, read_status);
+
+	if(read_status & A4_HALT_VALUE)
+	  {
+	    sigprocmask(SIG_BLOCK,&block_mask, NULL);
+	    break;
+	  }
+      }
+      else {
+	if(arc_jtag_read_aux_reg( 0xA, &read_status) == JTAG_READ_FAILURE)
+	  error("Failure reading auxillary register 0xA\n");
+	if(read_status & ARC700_HALT_VALUE)
+	  {
+	    sigprocmask(SIG_BLOCK,&block_mask, NULL);
+	    break;
+
+	  }
+      }
+      sigprocmask(SIG_UNBLOCK,&block_mask, NULL);	
+    }while(1);
+
+  while (1)
+    {
+      if (arc_jtag_read_aux_reg (0x5,&read_status) == JTAG_READ_FAILURE)
+	error ("Failure reading Debug register \n");
+      if (!(read_status & 0x80000000))
+	break;
+    }
+}
+
+static void
+arc_jtag_reset_board (void)
+{
+  char c = 5;
+  int  auxval = 2 ;
+  check_and_raise_error_if_jtag_closed ();
+
+  /*
+    Writing 9 did not work. But thats 
+    what the manual says. Hmmm. 
+  gpio_write (CONTROL_PORT, &c);
+  */
+
+  gpio_write ( CONTROL_PORT, &c);
+  c = 0xd;
+  gpio_write ( CONTROL_PORT, &c);
+  c = 5;
+  gpio_write ( CONTROL_PORT, &c);
+
+  if (arc_jtag_write_aux_reg(0x5 , 2) == JTAG_WRITE_FAILURE)
+    error ("Failure writing to auxiliary register Debug\n");
+
+  c = 0;
+  gpio_write ( 0x378, &c);
+  c = 0x40;
+  gpio_write ( 0x378, &c);
+  c = 0;
+  gpio_write ( 0x378, &c);
+  
+  tapc_reset();
+}
+
+
+void
+_initialize_arc_jtag_ops (void)
+{
+    arc_jtag_ops.name=NULL;
+    arc_jtag_ops.jtag_open = arc_jtag_open;
+    arc_jtag_ops.jtag_close = arc_jtag_close;
+    arc_jtag_ops.jtag_memory_write = arc_jtag_write_chunk;
+    arc_jtag_ops.jtag_memory_read = arc_jtag_read_chunk;
+    arc_jtag_ops.jtag_memory_chunk_write = arc_jtag_write_chunk;
+    arc_jtag_ops.jtag_memory_chunk_read = arc_jtag_read_chunk;
+    arc_jtag_ops.jtag_write_aux_reg = arc_jtag_write_aux_reg;
+    arc_jtag_ops.jtag_read_aux_reg = arc_jtag_read_aux_reg;
+    arc_jtag_ops.jtag_read_core_reg = arc_jtag_read_core_reg;
+    arc_jtag_ops.jtag_write_core_reg = arc_jtag_write_core_reg;
+    arc_jtag_ops.jtag_wait = arc_jtag_wait;
+    arc_jtag_ops.jtag_reset_board = arc_jtag_reset_board;
+    arc_jtag_ops.jtag_status = JTAG_CLOSED ;
+}
diff --git a/gdb/arc-jtag-ops.h b/gdb/arc-jtag-ops.h
new file mode 100644
index 0000000..dbf49e6
--- /dev/null
+++ b/gdb/arc-jtag-ops.h
@@ -0,0 +1,62 @@
+/* Target dependent code for ARC700, for GDB, the GNU debugger.
+
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Contributed by Codito Technologies Pvt. Ltd. (www.codito.com)
+
+   Authors: 
+      Sameer Dhavale <sameer.dhavale@codito.com>
+      Soam Vasani <soam.vasani@codito.com>
+
+   This file is part of GDB.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+
+
+#define ARC_NR_CORE_REGS        64
+#define MAX_ARC700_REG_SIZE     4
+#define JTAG_READ_FAILURE 0
+#define JTAG_WRITE_FAILURE 0
+enum arc_jtag_status
+  {
+    JTAG_OPENED,
+    JTAG_CLOSED, 
+    JTAG_RUNNING
+  };
+
+struct jtag_ops{
+  char *name;
+  void (*jtag_open) (void);
+  void (*jtag_close) (void);
+  int (*jtag_memory_write) (unsigned int, unsigned int *, int);
+  int (*jtag_memory_chunk_write) (unsigned int, unsigned int *, int);
+  int (*jtag_memory_read) (unsigned int, unsigned int *, int);
+  int (*jtag_memory_chunk_read) (unsigned int, unsigned int *, int);
+  int (*jtag_read_aux_reg) (unsigned int, unsigned int *);
+  int (*jtag_write_aux_reg) (unsigned int, unsigned int);
+  int (*jtag_read_core_reg) (unsigned int, unsigned int *);
+  int (*jtag_write_core_reg) (unsigned int, unsigned int);
+  void (*jtag_wait) (void);
+  void (*jtag_reset_board) (void);
+  enum arc_jtag_status jtag_status;
+  int arc_jtag_state_machine_debug;
+};
+
+
+#define IS_ARC700	(arc_get_architecture() == ARC700)
+#define IS_ARC600	(arc_get_architecture() == ARC600)
+#define IS_A5		(arc_get_architecture() == A5)
+#define IS_A4		(arc_get_architecture() == A4)
diff --git a/gdb/arc-jtag-tdep.c b/gdb/arc-jtag-tdep.c
new file mode 100644
index 0000000..8401538
--- /dev/null
+++ b/gdb/arc-jtag-tdep.c
@@ -0,0 +1,638 @@
+/* Target dependent code for ARC700, for GDB, the GNU debugger.
+
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Contributed by Codito Technologies Pvt. Ltd. (www.codito.com)
+
+   Authors: 
+      Soam Vasani <soam.vasani@codito.com>
+      Ramana Radhakrishnan <ramana.radhakrishnan@codito.com> 
+
+   This file is part of GDB.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+#include <string.h>
+
+#include "defs.h"
+#include "osabi.h"
+#include "frame.h"
+#include "regcache.h"
+#include "gdb_assert.h"
+#include "inferior.h"
+#include "gdbcmd.h"
+#include "reggroups.h"
+
+#include "arc-tdep.h"
+#include "arc-jtag.h"
+
+
+#ifdef ARC4_JTAG
+/* brk */
+unsigned int a4_jtag_breakpoint_size = 4;
+unsigned char a4_jtag_breakpoint_insn[4] = { 0x00, 0xfe, 0xff, 0x1f };
+#define A4_HALT_VALUE 0x02000000
+#else
+/* brk_s */
+unsigned int arc700_jtag_breakpoint_size = 2;
+unsigned char arc700_jtag_breakpoint_insn[2] = { 0xff, 0x7f };
+#endif
+
+
+
+struct arc_reg_info 
+{
+  char *name ;
+  int hw_regno;
+  char *description;
+#ifdef ARC4_JTAG
+  enum arc4_jtag_regnums gdbregno;
+#else
+  enum arc700_jtag_regnums gdbregno;
+#endif
+  enum ARCProcessorVersion arcVersionSupported;
+};
+
+
+
+static const char *
+arc_jtag_register_name (int regno)
+{
+  static char jtag_names[][30] = {
+    "r0", "r1", "r2", "r3", "r4", "r5", "r6",
+    "r7", "r8", "r9", "r10", "r11", "r12", "r13",
+    "r14", "r15", "r16", "r17", "r18", "r19", "r20",
+    "r21", "r22", "r23", "r24", "r25", "r26",
+    
+    "fp",
+    "sp",
+    "ilink1",
+    "ilink2",
+    "blink",
+    
+    /* Extension core regs are 32..59 inclusive.  */
+    "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
+    "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", "r48", "r49",
+    "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59",
+       
+    "lp_count",
+
+    /* 61 is reserved, 62 is not a real register.  */
+    /*FIXMEA: The following 3 are supposed to be registers
+     that are used only to encode immediate values in A4*/
+    "r61",
+    "r62",
+    
+    "pcl",
+
+    /* Now the aux registers.  */
+    
+    "status",
+    "semaphore",
+    "lp_start",
+    "lp_end",
+    "identity",
+    "debug",
+    
+#ifndef ARC4_JTAG
+    "pc",
+    "status32",
+    "status32_l1",
+    "status32_l2",
+
+    "count0",
+    "control0",
+    "limit0",
+    "int_vector_base",
+    "aux_macmode",
+    "aux_irq_lv12",
+
+
+    "count1",
+    "control1",
+    "limit1",
+    "aux_irq_lev",
+    "aux_irq_hint",
+    "eret",
+    "erbta",
+    "erstatus",
+    "ecr",
+    "efa",
+    "icause1",
+    "icause2",
+    "aux_ienable",
+    "aux_itrigger",
+    "xpu",
+    "bta",
+    "bta_l1",
+    "bta_l2",
+    "aux_irq_pulse_cancel",
+    "aux_irq_pending",
+
+    /* Build configuration registers.  */
+    "bcr_0",
+    "dccm_base_build",
+    "crc_base_build",
+    "bta_link_build",
+    "dvbf_build",
+    "tel_instr_build",
+    "bcr_6",
+    "memsubsys",
+    "vecbase_ac_build",
+    "p_base_address",
+    "bcr_a",
+    "bcr_b",
+    "bcr_c",
+    "bcr_d",
+    "bcr_e",
+    "mmu_build",
+    "arcangel_build",
+    "bcr_11",
+    "d_cache_build",
+    "madi_build",
+    "dccm_build",
+    "timer_build",
+    "ap_build",
+    "icache_build",
+    "iccm_build",
+    "dspram_build",
+    "mac_build",
+    "multiply_build",
+    "swap_build",
+    "norm_build",
+    "minmax_build",
+    "barrel_build",
+#endif
+    
+  };
+  
+  gdb_assert(ARRAY_SIZE (jtag_names) == NUM_REGS + NUM_PSEUDO_REGS);
+  gdb_assert(regno >=0 && regno < NUM_REGS + NUM_PSEUDO_REGS);
+
+  return jtag_names[regno];
+}
+
+int
+arc_jtag_register_reggroup_p (int regnum, struct reggroup *group)
+{
+  /* These registers don't exist, so they are not in any reggroup.  */
+  if ((regnum >= 32 && regnum <= 59) || (regnum == 61) || (regnum == 62))
+    return 0;
+
+  /* Which regs to save/restore ? */
+  if ((group == save_reggroup || group == restore_reggroup))
+    {
+      /* Save/restore:
+	 1. all core regs, except PCL (PCL is not writable)
+	 2. aux regs LP_START..LP_END (IDENTITY is not writable)
+	 3. aux regs PC_REGNUM..STATUS32_L2
+	 3. aux regs ERET..EFA */
+      return ( ( regnum >= 0 && regnum < ARC_PCL_REGNUM)
+	       || ( regnum >= ARC_LP_START_REGNUM && regnum<= ARC_LP_END_REGNUM)
+#ifdef ARC4_JTAG
+	       || ( regnum == ARC_STATUS_REGNUM)
+#else	       
+	       || ( regnum >= ARC_PC_REGNUM && regnum <= ARC_STATUS32_L2_REGNUM)
+	       || ( regnum >= ARC_ERET_REGNUM && regnum <= ARC_EFA_REGNUM)
+#endif
+	       );
+    }
+  
+  return -1;
+}
+
+static void
+arc_jtag_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
+			       struct frame_info *frame, int regnum, int all)
+{
+  int i;
+
+  if (regnum >= 0 )
+    {
+      default_print_registers_info (gdbarch, file, frame, regnum, all);
+      return;
+    }
+
+  /* if regnum < 0 , print all registers */
+
+  for (i=0; i <= 26; ++i)
+    default_print_registers_info (gdbarch, file, frame, i, all);
+  default_print_registers_info (gdbarch, file, frame, 
+				ARC_FP_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, 
+				ARC_SP_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, 
+				ARC_ILINK1_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, 
+				ARC_ILINK2_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, 
+				ARC_BLINK_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, 
+				ARC_LP_COUNT_REGNUM, all);
+  
+  /* now the aux registers */
+   if (!all)
+    {
+      default_print_registers_info (gdbarch, file, frame, 
+				    ARC_LP_START_REGNUM, all);
+      default_print_registers_info (gdbarch, file, frame, 
+				    ARC_LP_END_REGNUM, all);
+      
+#ifndef ARC4_JTAG 
+      default_print_registers_info (gdbarch, file,frame,
+				    ARC_STATUS32_REGNUM, all);
+      default_print_registers_info (gdbarch, file, frame, 
+				    ARC_BTA_REGNUM, all);
+      default_print_registers_info (gdbarch, file, frame, 
+				    ARC_EFA_REGNUM, all);
+      default_print_registers_info (gdbarch, file, frame, 
+				    ARC_ERET_REGNUM, all);
+      default_print_registers_info (gdbarch, file, frame, 
+				    ARC_STATUS32_L1_REGNUM, all);
+      default_print_registers_info (gdbarch, file, frame, 
+				    ARC_STATUS32_L2_REGNUM, all);
+      default_print_registers_info (gdbarch, file, frame, 
+				    ARC_ERSTATUS_REGNUM, all);
+      
+      
+      /* PC */
+      default_print_registers_info (gdbarch, file, frame, 
+				    ARC_PC_REGNUM, all);
+#endif
+    }
+   else
+     {
+       /* This part needs cleaning up. */
+       for (i = ARC_STATUS_REGNUM;
+#ifndef ARC4_JTAG
+	    i <= ARC_AUX_IRQ_PENDING_REGNUM;
+#else /*FIXMEA*/
+	    i <=  ARC_DEBUG_REGNUM;
+#endif
+	    i ++ )
+	 default_print_registers_info (gdbarch, file, frame , 
+				       i, all);
+
+       
+       for (i = ARC_STATUS_REGNUM ; 
+#ifndef ARC4_JTAG
+	    i <= ARC_AUX_IRQ_PENDING_REGNUM;
+#else /*FIXMEA*/
+	    i <=  ARC_DEBUG_REGNUM;
+#endif
+	    i ++ )
+	 default_print_registers_info (gdbarch, file, frame, 
+				       i, all);
+       
+#ifndef ARC4_JTAG
+       for (i = ARC_BCR_1_REGNUM ; 
+	    i <= ARC_BCR_5_REGNUM ;
+	    i ++ )
+	 default_print_registers_info (gdbarch, file , frame, 
+				       i , all);
+       
+       for (i = ARC_BCR_7_REGNUM ;
+	    i <= ARC_BCR_9_REGNUM;
+	    i ++ )
+	 default_print_registers_info (gdbarch, file, frame, 
+				       i , all);
+
+       for (i = ARC_BCR_F_REGNUM;
+	    i <= ARC_BCR_10_REGNUM;
+	    i ++ )
+	 default_print_registers_info (gdbarch, file, frame , 
+				       i , all);
+
+       for (i = ARC_BCR_12_REGNUM;
+	    i <= ARC_BCR_1F_REGNUM;
+	    i ++)
+	 default_print_registers_info (gdbarch, file, frame , 
+				       i , all);
+#endif //if no ARC4_JTAG
+
+
+     }
+}
+
+/* Command: aux-read <from> <to>
+
+   Read and display a range of aux registers.  Some of the aux registers
+   (pc, debug, etc.) are part of the register set, but this is a more
+   general interface.
+
+   We should eventually change this to use the ui_out stuff rather than
+   printf_filtered.  */
+static void
+arc_jtag_aux_read_command (char *arg, int from_tty)
+{
+  char *arg2 = 0;
+  struct expression *expr;
+  struct value *val;
+  struct cleanup *old_chain = 0;
+  int auxregno, auxregno2 = 0, nrregs;
+  unsigned int *buf;
+  int i, nrtransfered;
+
+  if (!arg)
+    {
+      printf_filtered ("aux-read <REG-FROM> [<REG-TO>]\n");
+      return;
+    }
+  
+  /* strip leading spaces */
+  while(*arg == ' ')
+    arg++;
+
+  /* two arguments ?  */
+  /* This assumes that the first arg cannot have spaces.  (The disas command
+     also seems to work this way.)  */
+  arg2 = strchr (arg, ' ');
+
+  /* get the second one */
+  if (arg2)
+    {
+      struct expression *expr2;
+      struct value *val2;
+
+      arg2[0] = 0;
+      arg2++;
+     
+      expr2 = parse_expression (arg2);
+      val2 = evaluate_expression (expr2);
+      xfree (expr2);
+
+      auxregno2 = *(int *)(VALUE_CONTENTS (val2));
+    }
+
+  /* first arg */
+  expr = parse_expression (arg);
+  val = evaluate_expression (expr);
+  old_chain = make_cleanup (free_current_contents, &expr);
+  
+  auxregno = *(int *)(VALUE_CONTENTS (val));
+
+  /* so, how many regs do we want ? */
+  if (arg2)
+    {
+      if (auxregno2 < auxregno)
+	{
+	  warning ("aux-read: %s < %s, showing one register", arg2, arg);
+	  nrregs = 1;
+	}
+      else
+	nrregs = auxregno2 - auxregno + 1;
+    }
+  else
+    nrregs = 1;
+
+  buf = xcalloc (nrregs, sizeof(int));
+  make_cleanup (free_current_contents, &buf);
+  
+  /* Go get 'em !  */
+  nrtransfered = target_read_aux_reg (buf, auxregno, nrregs);
+  if (nrtransfered <= 0)
+    {
+      do_cleanups (old_chain);
+      error ("aux-read: couldn't read any registers.");
+    }
+  else if (nrtransfered < nrregs)
+    {
+      warning ("aux-read: could only read %d registers", nrtransfered);
+    }
+  
+  gdb_assert (nrtransfered <= nrregs);
+
+  /* Show them.  */
+  for (i = auxregno; i - auxregno < nrtransfered; ++i)
+    {
+      if ((i - auxregno) % 4 == 0)
+	printf_filtered("%s%08x: ", ((i - auxregno) ? "\n" : ""), i);
+      
+      printf_filtered ("%08x ", buf[i - auxregno]);
+    }
+  printf_filtered ("\n");
+  
+  do_cleanups (old_chain);
+}
+
+/* aux-write <regnum> = <value>
+   Write VALUE to aux register REGNUM. */
+static void
+arc_jtag_aux_write_command (char *arg, int from_tty)
+{
+  char *value_arg = 0;
+  struct expression *regnum_expr, *value_expr;
+  struct value *regnum_val, *value_val;
+  struct cleanup *old_chain = 0;
+  unsigned int regnum, value;
+  int err;
+  
+  if (!arg)
+    {
+      printf_filtered ("aux-write <regnum> = <value>\n");
+      return;
+    }
+
+  value_arg = strchr(arg, '=');
+  if (!value_arg)
+    {
+      error ("aux-write: can't find second argument\n\
+Usage: aux-write <regnum> = <value>");
+      return;
+    }
+  value_arg[0] = 0;
+  value_arg++;
+
+  /* Regnum expression */
+  regnum_expr = parse_expression (arg);
+  regnum_val = evaluate_expression (regnum_expr);
+  old_chain = make_cleanup (free_current_contents, &regnum_expr);
+  regnum = *(unsigned int *)(VALUE_CONTENTS (regnum_val));
+
+  /* Value expression */
+  value_expr = parse_expression (value_arg);
+  value_val = evaluate_expression (value_expr);
+  make_cleanup (free_current_contents, &value_expr);
+  value = *(unsigned int *)(VALUE_CONTENTS (value_val));
+
+  /* Write it.  */
+  err = target_write_aux_reg (&value, regnum, 1);
+  if (err != 1)
+    {
+      do_cleanups (old_chain);
+      error ("aux-write: couldn't write to register 0x%x", regnum);
+    }
+
+  do_cleanups (old_chain);
+}
+
+#ifdef ARC4_JTAG
+//  gdbarch_write_pc_ftype *write_pc;
+/*
+  Write PC
+  Arguments:
+  1.CORE_ADDR val : Contains the value to be written into PC.
+  2.ptid_t ptid: Process id of the process.
+
+  Returns: void
+  Description: FIXMEA: Update
+      Reads the status register
+      Inserts the value (upper 24 bit) into the bits
+      0-23 in the status register
+      Write the status register
+ */
+void
+a4_jtag_write_pc (CORE_ADDR val, ptid_t ptid)
+{
+  CORE_ADDR insert_val = val >> 2;
+  unsigned int buffer;
+
+
+  if(debug_arc_jtag_target_message)
+      printf_filtered ("\n -----***------------ a4_jtag_write_pc Entered ---*%%*#\n");
+
+  
+  target_read_aux_reg (&buffer, ARC_HW_STATUS_REGNUM, 1);
+
+  if (!(buffer & A4_HALT_VALUE))
+    {
+      if(debug_arc_jtag_target_message)
+	printf_filtered ("\n***** Halting Processor... *********\n");
+      
+      buffer = buffer | A4_HALT_VALUE ;
+      target_write_aux_reg (&buffer, ARC_HW_STATUS_REGNUM, 1);
+      /* Now the A4 processor has halted*/
+    }
+  
+  if(debug_arc_jtag_target_message)
+    printf_filtered (" \nWriting value %u to PC\n", val);
+
+
+  target_read_aux_reg (&buffer, ARC_HW_STATUS_REGNUM, 1);
+  if(debug_arc_jtag_target_message)
+    printf_filtered (" \nValue of Status Register before writing %d\
+                     \n Value of PC: 0x%x\n", buffer, buffer & 0x00ffffff);
+
+  buffer = buffer & 0xff000000;
+  insert_val    = insert_val & 0x00ffffff;
+  buffer = buffer | insert_val ;
+  
+  if(debug_arc_jtag_target_message)
+    printf_filtered (" \nValue of Status Register to be written %d\
+                       \n Value of PC: 0x%x\n", buffer, buffer & 0x00ffffff);
+
+  //  jtag_ops.jtag_write_aux_reg (ARC_STATUS_REGNUM, buffer);
+  target_write_aux_reg (&buffer, ARC_HW_STATUS_REGNUM, 1);
+
+  if(debug_arc_jtag_target_message)
+    {
+      target_read_aux_reg (&buffer, ARC_HW_STATUS_REGNUM, 1);
+      printf_filtered (" \nValue of Status Register after reading again %d\
+                        \n Value of PC: 0x%x\n", buffer, buffer & 0x00ffffff);
+    }
+
+    if(debug_arc_jtag_target_message)
+      printf_filtered ("\n -----***------------ a4_jtag_write_pc Leaving ---*%%*#\n");
+
+}
+
+
+/*
+  Read PC
+  Arguments:
+  1.ptid_t ptid: Process id of the process.
+
+  Returns: CORE_ADDR 
+  Description:
+      Reads the status register
+      Extracts the PC value from it.
+      Right shift twice to get correct value of PC
+      return PC
+*/
+CORE_ADDR
+a4_jtag_read_pc (ptid_t ptid)
+{
+  unsigned int buffer;
+
+  if (debug_arc_jtag_target_message)
+    printf_filtered ("\n Entering a4_jtag_read_pc ()");
+  buffer = 0;
+  target_read_aux_reg (&buffer, ARC_HW_STATUS_REGNUM, 1);
+  if (debug_arc_jtag_target_message)
+    printf_filtered ("\n Value of Status Reg: 0x%x",buffer);
+  buffer = buffer & 0x00ffffff;
+  buffer = buffer << 2;
+
+  if (debug_arc_jtag_target_message)
+    printf_filtered ("\n Leaving a4_jtag_read_pc ()\
+                      \n Value of Pc: 0x%x\n", buffer);
+  
+  return buffer;
+}
+
+#endif // ARC4_JTAG
+
+ARCVariantsInfo arc_debug_processor_information;
+
+struct gdbarch *
+arc_jtag_init (struct gdbarch *gdbarch)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+#ifndef ARC4_JTAG
+  tdep->arc_breakpoint_size = arc700_jtag_breakpoint_size;
+  tdep->arc_breakpoint_insn = arc700_jtag_breakpoint_insn;
+#else
+  tdep->arc_breakpoint_size = a4_jtag_breakpoint_size;
+  tdep->arc_breakpoint_insn = a4_jtag_breakpoint_insn;
+#endif
+
+  set_gdbarch_num_regs (gdbarch, ARC_NR_REGS);
+#ifndef ARC4_JTAG
+  set_gdbarch_pc_regnum (gdbarch, ARC_PC_REGNUM);
+#else
+  //  set_gdbarch_pc_regnum (gdbarch, ARC_STATUS_REGNUM);
+  set_gdbarch_write_pc (gdbarch, a4_jtag_write_pc);
+  set_gdbarch_read_pc (gdbarch, a4_jtag_read_pc);
+#endif
+  set_gdbarch_register_name (gdbarch, arc_jtag_register_name);
+  
+  set_gdbarch_print_registers_info (gdbarch, arc_jtag_print_registers_info);
+
+  tdep->register_reggroup_p = arc_jtag_register_reggroup_p;
+
+  tdep->lowest_pc = 0;
+  
+  tdep->sigtramp_p = NULL;
+
+  tdep->arc_processor_variant_info = &arc_debug_processor_information;
+
+  /* Auxillary register commands.  */
+  add_cmd ("arc-aux-read", class_vars, arc_jtag_aux_read_command,
+	   "Read and show a range of auxillary registers.\n\
+Usage: arc-aux-read <REG-FROM> [<REG-TO>]\n\
+REG-FROM and REG-TO can be any expressions that evaluate to integers.\n\
+If REG-TO is not specified, one register is displayed.",
+	   &cmdlist);
+
+  add_cmd ("arc-aux-write", class_vars, arc_jtag_aux_write_command,
+	   "Write to an auxillary register.\n\
+Usage: arc-aux-write <REG> = <VALUE>\n\
+REG and VALUE can be any expressions that evaluate to integers.",
+	   &cmdlist);
+
+  return gdbarch;
+}
+
diff --git a/gdb/arc-jtag.c b/gdb/arc-jtag.c
new file mode 100644
index 0000000..9a86b6d
--- /dev/null
+++ b/gdb/arc-jtag.c
@@ -0,0 +1,1297 @@
+/* Target dependent code for ARC700, for GDB, the GNU debugger.
+
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Contributed by Codito Technologies Pvt. Ltd. (www.codito.com)
+
+   Authors: 
+      Sameer Dhavale <sameer.dhavale@codito.com>
+      Ramana Radhakrishnan <ramana.radhakrishnan@codito.com> 
+
+   This file is part of GDB.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+
+#include <stdio.h>
+#include <string.h>
+#include "defs.h"
+#include "inferior.h"
+#include "target.h"
+#include "breakpoint.h"
+
+#include "arc-tdep.h"
+
+#include <unistd.h>
+#include <stdlib.h>
+
+#include <sys/io.h>
+#include <sys/types.h>
+
+#include <assert.h>
+
+#include "arc-jtag.h"
+#include "arc-jtag-ops.h"
+#include "gdbcore.h"
+#include "gdbarch.h"
+#include "regcache.h"
+#include "command.h"
+#include "gdbcmd.h"
+#include <signal.h>
+
+/* Flag to print debug messages from here. */
+/* FIXMEA:
+static int debug_arc_jtag_target_message;
+*/
+
+#define ENTERMSG  \
+do {\
+if(debug_arc_jtag_target_message) \
+printf_filtered ("--- entered %s:%s()\n", __FILE__, __FUNCTION__); \
+} while(0)
+
+#define ENTERARGS(fmt, args...) \
+do { \
+if(debug_arc_jtag_target_message) \
+printf_filtered ("--- entered %s:%s(" fmt ")\n", __FILE__, __FUNCTION__, args);\
+} while(0)
+
+#define LEAVEMSG \
+do { \
+if(debug_arc_jtag_target_message) \
+printf_filtered ("--- exited %s:%s()\n", __FILE__, __FUNCTION__); \
+} while(0)
+
+/* The number of times a memory read/write operation should be attempted
+   before returning an error.
+*/
+#define MEMORY_TRANSFER_ATTEMPTS 10
+
+/* defined in arc-jtag-ops.c */
+extern unsigned int arcjtag_retry_count;
+
+struct target_ops arc_debug_ops;
+extern struct jtag_ops arc_jtag_ops;
+
+static void arc_debug_interrupt (int signo);
+static void arc_debug_interrupt_twice (int signo);
+static void arc_print_processor_variant_info (void);
+static int arc_debug_write_aux_register (int hwregno, int *buf);
+static int arc_debug_read_aux_register (int hwregno, int *buf);
+static int arc_debug_read_core_register (int hwregno, int *buf);
+
+
+/* Register Mapping information between GDB regnums
+   and actual hardware register numbers. 
+*/
+
+struct arc_reg_info 
+{
+  char *name ;
+  enum arc_hw_regnums hw_regno;
+  char *description;
+#ifdef ARC4_JTAG
+  enum arc4_jtag_regnums gdbregno;
+#else
+  enum arc700_jtag_regnums gdbregno;
+#endif
+  enum ARCProcessorVersion arcVersionSupported;
+};
+
+#define RBCR(name, hwregno , desc, gdbregno, version) { #name, hwregno , desc , gdbregno , version } ,
+
+#undef RAUX
+struct arc_reg_info arc_bcr_reg_info [] = 
+  {
+   #include "arc-regnums-defs.h"
+  };
+
+#undef RAUX
+#undef RBCR
+#define RAUX(name, hwregno , desc, gdbregno, version) { #name , hwregno , desc , gdbregno , version } ,
+struct arc_reg_info arc_aux_reg_map[] =
+  {
+    #include "arc-regnums-defs.h"
+  };
+
+
+
+static void 
+arc_update_architecture(void)
+{
+  unsigned int idinfo;
+  unsigned short tmp;
+  struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch);
+
+  if (IS_ARC700) {
+    tdep->arc_processor_variant_info->arcprocessorversion = ARC700;
+    set_gdbarch_decr_pc_after_break (current_gdbarch,0);
+  }
+  else if(IS_ARC600) {
+    tdep->arc_processor_variant_info->arcprocessorversion = ARC600;
+    set_gdbarch_decr_pc_after_break (current_gdbarch,2);
+  }
+  else if(IS_A5) {
+    warning ("A5 debugging is unsupported and may be buggy.");
+    tdep->arc_processor_variant_info->arcprocessorversion = A5;
+  }
+  else {
+    tdep->arc_processor_variant_info->arcprocessorversion = A4;
+    set_gdbarch_decr_pc_after_break (current_gdbarch,0);
+  }    
+}
+
+/* Get us out of user mode.  */
+static unsigned int
+clear_status32_user_bit ()
+{
+  int rd;
+#ifndef ARC4_JTAG  
+  if(arc_jtag_ops.jtag_read_aux_reg(ARC_HW_STATUS32_REGNUM, &rd) == JTAG_READ_FAILURE)
+    error("Failure reading auxillary register 0x%x:status32 register", ARC_HW_STATUS32_REGNUM);
+
+  if(arc_jtag_ops.jtag_write_aux_reg(ARC_HW_STATUS32_REGNUM, rd & ~0x80) == JTAG_READ_FAILURE)
+    error("Failure writing to auxillary register 0x%x:status32 register", ARC_HW_STATUS32_REGNUM);
+#endif
+  return rd;
+}
+
+/* Restore a saved status32; use with clear_status32_user_bit().  */
+static void
+restore_status32_user_bit (unsigned int status32)
+{
+#ifndef ARC4_JTAG
+  if(arc_jtag_ops.jtag_write_aux_reg(ARC_HW_STATUS32_REGNUM, status32) == JTAG_READ_FAILURE)
+    error("Failure writing to auxillary register 0x%x:status32 register", ARC_HW_STATUS32_REGNUM);
+#endif
+}
+
+/* UB bit in the debug register.  It allows brk_s to work in user mode.  */
+static void
+set_debug_user_bit ()
+{
+  if(is_arc700 ())
+    {
+      /* set UB = 1 */
+      unsigned int debug;
+      if (arc_jtag_ops.jtag_read_aux_reg (ARC_HW_DEBUG_REGNUM, &debug) == JTAG_READ_FAILURE)
+	error("Failure reading auxillary register 0x%x:debug register",ARC_HW_DEBUG_REGNUM);
+      debug |= 0x10000000;                     
+      arc_jtag_ops.jtag_write_aux_reg (ARC_HW_DEBUG_REGNUM, debug);
+    }
+}
+
+
+
+static void
+invalidateCaches (void)
+{
+    if(arc_jtag_ops.jtag_write_aux_reg ( ARC_HW_ICACHE_IVIC , 1)==JTAG_WRITE_FAILURE)
+	error("Failure writing 0x1 to auxillary register 0x%x:Icache invalidate\n",ARC_HW_ICACHE_IVIC);
+    if(arc_jtag_ops.jtag_write_aux_reg ( ARC_HW_DCACHE_IVIC , 1)==JTAG_WRITE_FAILURE)
+	error("Failure writing 0x1 to auxillary register 0x%x:Dcache invalidate\n",ARC_HW_DCACHE_IVIC);
+}
+
+static void
+disableCaches (void)
+{
+  /* Disabling Icache */
+    if(arc_jtag_ops.jtag_write_aux_reg( ARC_HW_ICACHE_CONTROL ,0x1)==JTAG_WRITE_FAILURE)
+      error("Failure writing 0x1 to auxillary register 0x%x:Icache control register\n",ARC_HW_ICACHE_CONTROL);
+  /* Disabling Dcache */
+    if(arc_jtag_ops.jtag_write_aux_reg( ARC_HW_DCACHE_CONTROL ,0x1)==JTAG_WRITE_FAILURE)
+	error("Failure writing 0x1 to auxillary register 0x%x:Dcache control register\n",ARC_HW_DCACHE_CONTROL);
+}
+
+
+/* Function: arc_debug_open
+ * Parameters :
+ * 1. args :
+ * 2. from_tty:
+ * Returns : void
+ * Description: 
+	1. Connect to the jtag target . 
+	2. Read the number of action points supported. 
+	3. Read the configuration of action points. 
+	4. Set up internal data structures for number of hardware
+	   breakpoints and watchpoints. 
+	5. Set the UB bit to 1 for ARC700 and not for ARC600.
+ * 
+ */
+
+void
+arc_debug_open (char *args, int from_tty)
+{
+  ENTERARGS("%s", args);
+  target_preopen(from_tty);
+  
+  reopen_exec_file ();
+  reread_symbols ();
+  
+  unpush_target (&arc_debug_ops);  
+  arc_jtag_ops.jtag_open();
+  push_target (&arc_debug_ops);
+
+  /* Call arc_update_architecture if opened successfully.  */
+  arc_update_architecture();
+  /* Fixme  :: Should these be in create_inferior or 
+     some place else ?. We would not like these here
+     when attach starts working. 
+  */
+  disableCaches();
+#ifdef ARC4_JTAG
+  if(arc_jtag_ops.jtag_write_aux_reg (ARC_HW_STATUS_REGNUM, 0x02000000)==JTAG_WRITE_FAILURE)
+          error("Failure writing 0x0200 0000 to auxillary register 0x%x:status register\n",ARC_HW_STATUS_REGNUM);
+
+  if (from_tty)
+    printf_filtered ("Connected to the arcjtag target.\n");  
+  
+#else
+  if(arc_jtag_ops.jtag_write_aux_reg (ARC_HW_STATUS32_REGNUM, 0x1)==JTAG_WRITE_FAILURE)
+
+    error("Failure writing 0x1 to auxillary register 0x%x:status32 register\n",ARC_HW_STATUS32_REGNUM);
+  
+  /* allow breakpoints in user mode.  */
+  set_debug_user_bit ();
+
+
+  if (from_tty)
+    printf_filtered ("Connected to the arcjtag target.\n");  
+#endif
+}
+
+void arc_debug_close()
+{
+    arc_jtag_ops.jtag_close();
+}
+
+/* Function: arc_debug_attach
+ * Parameters :
+ * 1. char *x:
+ * 2. int i:
+ * Returns : void
+ * Description: 
+ *  1. attach without resetting the board 
+ *  2. get all Board configuration registers of interest.
+ *  if ARC700 set the UB bit to 1. (This is invalid in the 
+ *  ARC600).
+ */
+
+
+void
+arc_debug_attach (char *x, int i)
+{
+
+  ENTERMSG;
+}
+
+
+/* Function: arc_debug_attach
+ * Parameters :
+ * 1. char *x:
+ * 2. int i:
+ * Returns : void
+ * Description: 
+ *  1. Detach without resetting the board. 
+ */
+void
+arc_debug_detach (char *x, int i)
+{
+	
+  ENTERMSG;
+
+  /* Let it continue.  */
+  target_resume (inferior_ptid, 0, 0);
+}
+
+
+/* Function: arc_debug_resume
+ * Parameters :
+ * 1. ptid_t ptid:
+ * 2. int step: 1 - single step , 0 run freely.
+ * 3. enum target_signal signal;
+ * Returns : void
+ * Description: 
+ *  	1. What about Pipecleaning?
+ *	2. Write 0 to the HALT bit in status32.
+ *      3. Send a signal (ignore) in this case. 
+ *      4. if(step) use hardware single step on the ARC700.
+ *          done by setting the IS bit in the debug register
+ *          and clearing the halt bit in status32. 
+ *	
+ */
+
+void
+arc_debug_resume (ptid_t ptid, int step, enum target_signal signal)
+{
+  
+  ENTERARGS("%d,%d,%d", ptid.pid, step, signal);
+  /* Make the inferior resume execution, sending a signal if necessary */
+  unsigned int rd;
+
+  /* Because breakpoints may have been set/removed.  */
+  invalidateCaches ();
+
+  /* This bit is required if breakpoints are to be allowed in user mode.  We
+     set it in target_open, but the operating system might clear it.  So we
+     set it every time we resume.  */
+  set_debug_user_bit ();
+
+  if(step)
+  {
+
+    /* reading debug reg */
+      if(arc_jtag_ops.jtag_read_aux_reg(ARC_HW_DEBUG_REGNUM,&rd)==JTAG_READ_FAILURE)
+	  error("Failure reading auxillary register 0x%x:debug register",ARC_HW_DEBUG_REGNUM);
+#ifdef ARC4_JTAG      
+      rd |= 0x801; /*Setting the IS and the SS bit in the status register
+		     for the A4 core to allow it to single step.  */
+#else
+      /* Mask for Single Stepping changes for ARC600 and ARC700. */
+      if(is_arc700())
+	rd |= 0x800;
+      else
+	if(is_arc600())
+	  rd |= 0x801;
+#endif
+      
+      /* Writing to IS bit in DEBUG register for 
+	 hardware single instruction stepping.  */
+      if(arc_jtag_ops.jtag_write_aux_reg(ARC_HW_DEBUG_REGNUM ,rd)==JTAG_WRITE_FAILURE)
+	  error("Failure writing 0x%x to auxillary register 0x%x:debug register\n",rd,ARC_HW_DEBUG_REGNUM);
+  }
+  else
+  {
+    /* Restarting the processor by clearing the 'H' bit in the status register*/
+#ifdef ARC4_JTAG    
+    /* reading the status reg */     
+    if(arc_jtag_ops.jtag_read_aux_reg(ARC_HW_STATUS_REGNUM,&rd)==JTAG_READ_FAILURE)
+      error("Failure reading auxillary register 0x%x:status register",ARC_HW_STATUS_REGNUM);
+  
+    rd = rd & ~(0x02000000);
+  
+    /* starting the halted processor */
+    if(arc_jtag_ops.jtag_write_aux_reg(ARC_HW_STATUS_REGNUM,rd)==JTAG_WRITE_FAILURE)
+      error("Failure writing 0x%x to auxillary register 0x%x:status register\n",rd,ARC_HW_STATUS_REGNUM);
+#else
+    /* reading the status32 reg */     
+    if(arc_jtag_ops.jtag_read_aux_reg(ARC_HW_STATUS32_REGNUM,&rd)==JTAG_READ_FAILURE)
+      error("Failure reading auxillary register 0x%x:status32 register",ARC_HW_STATUS32_REGNUM);
+  
+    rd = rd & ~(0x1);
+  
+    /* starting the halted processor */
+    if(arc_jtag_ops.jtag_write_aux_reg(ARC_HW_STATUS32_REGNUM,rd)==JTAG_WRITE_FAILURE)
+      error("Failure writing 0x%x to auxillary register 0x%x:status32 register\n",rd,ARC_HW_STATUS32_REGNUM);
+#endif
+  }
+}
+
+/* For the ^C signal handler.  */
+static  void (*ofunc) (int);
+
+/* The command line interface's stop routine.  This function is installed as
+   a signal handler for SIGINT.  The first time a user requests a stop, we
+   call target_stop to send a break or ^C.  If there is no response from the
+   target (it didn't stop when the user requested it), we ask the user if
+   he'd like to detach from the target.  */
+static void
+arc_debug_interrupt (int signo)
+{
+  /* If we get the signal twice, do something more drastic.  */
+  signal (signo, arc_debug_interrupt_twice);
+  
+  target_stop ();
+}
+
+/* The user typed ^C twice.  */
+static void
+arc_debug_interrupt_twice (int signo)
+{
+  signal (signo, ofunc);
+
+  if (query ("Interrupted while waiting for the program.\n\
+Give up (and stop debugging it)? "))
+    {
+      target_mourn_inferior ();
+      throw_exception (RETURN_QUIT);
+    }
+
+  signal (signo, arc_debug_interrupt);
+}
+
+/* Function: arc_debug_wait
+ * Parameters :
+ * 1. ptid_t ptid:
+ * 2. struct target_waitstatus *status: Indicates status at end
+                                        of wait for F.E.
+ * Returns : void
+ * Description: 
+ *        Poll status32 for the value of H bit.	
+ *        After H bit is set in status32. 
+ *        Wait till LD(load pending bit) in the DEBUG register
+ *        is cleared.
+ *        SH bit is set if flag instruction was used to halt the processor.
+ *        BH bit is set if the ARCompact processor stopped due to 
+ *        a brk_s instruction. Set the target_waitstatus (signal) to SIGTRAP
+ *        only in such a situation. 
+ *	
+ */
+
+ptid_t
+arc_debug_wait (ptid_t ptid, struct target_waitstatus *status)
+{
+  unsigned int debug;
+  ENTERMSG;
+
+  /* signal handler for Control-C.  */
+  ofunc = signal (SIGINT, arc_debug_interrupt);
+
+  arc_jtag_ops.jtag_wait();
+  /* put the old function back.  */
+  signal (SIGINT, ofunc);
+
+  /* If the SH ("self halt") bit is set, we stopped because of the flag
+     instruction, which is used by programs to exit.  */
+  if (arc_jtag_ops.jtag_read_aux_reg (ARC_HW_DEBUG_REGNUM,
+				      &debug) == JTAG_READ_FAILURE)
+    {
+      error ("Failure reading from debug register");
+    }
+
+  /* SH bit of debug register */
+  if (debug & ARC_DEBUG_REG_SH_BIT)
+    {
+      int exitcode;
+      status->kind = TARGET_WAITKIND_EXITED;
+
+      /* Exit code of the program.  */
+      if (arc_jtag_ops.jtag_read_core_reg (0, &exitcode) == JTAG_READ_FAILURE)
+	{
+	  warning ("Failure reading from register r0, assuming exit code = 0");
+	  status->value.integer = 0;
+	}
+      status->value.integer = exitcode;
+    }
+  else
+    {
+      status->kind = TARGET_WAITKIND_STOPPED;
+      status->value.sig = TARGET_SIGNAL_TRAP;
+    }
+
+#ifndef ARC4_JTAG
+  /* Bug #1311 (ARC600): Setting a breakpoint on the last instruction of a
+     ZOL causes GDB to stop at LP_START.  Detect this condition and warn the
+     user.  */
+  if (is_arc600 ())
+    {
+      unsigned int pc, lp_start, lp_end, lp_count;
+      arc_debug_read_core_register (ARC_LP_COUNT_REGNUM, &lp_count);
+      if (lp_count != 0)
+	{
+	  arc_debug_read_aux_register (ARC_HW_PC_REGNUM, &pc);
+	  arc_debug_read_aux_register (ARC_HW_LP_START_REGNUM, &lp_start);
+	  
+	  if (pc == lp_start)
+	    {
+	      extern struct breakpoint *breakpoint_chain;
+	      struct breakpoint *b;
+	      arc_debug_read_aux_register (ARC_HW_LP_END_REGNUM, &lp_end);
+
+	      for (b = breakpoint_chain; b; b = b->next)
+		{
+		  /* lp_end is the address of the last instruction + the
+		     size of the last instruction.  We could use the
+		     disassembler and find out the size, or just try both
+		     possible sizes.  */
+		  if ((b->enable_state == bp_enabled && !b->pending) &&
+		      b->loc->address == lp_end-4 || b->loc->address == lp_end-2)
+		    {
+		      warning ("Did you set a breakpoint on the last instruction of \n\
+a Zero Overhead Loop ?  Such breakpoints do not work properly.");
+		    }
+		}
+	    }
+	}
+    }
+#endif
+  return inferior_ptid;
+}
+
+static unsigned int 
+arc_get_hw_regnum_mapping ( int regno )
+{
+  int i;
+
+  if (regno >= ARC_STATUS_REGNUM 
+#ifdef ARC4_JTAG
+      && regno <= ARC_DEBUG_REGNUM
+#else
+      && regno <= ARC_AUX_IRQ_PENDING_REGNUM
+#endif      
+      )
+    return  arc_aux_reg_map[regno - ARC_STATUS_REGNUM].hw_regno;
+  
+  for ( i = 0 ; i < (sizeof(arc_bcr_reg_info) / sizeof (struct arc_reg_info)) ; i++)
+    {
+      if (regno == arc_bcr_reg_info[i].gdbregno)
+	return arc_bcr_reg_info[i].hw_regno;
+    }
+
+  return -1;
+}
+
+
+/* Function: arc_debug_fetch_regs.
+ * Parameters :
+ * 1. int regnum: Register number. If register number is -1.Fetch
+ *                all the registers.Read all core registers here.
+ * Returns : void
+ * Description: 
+ *          Set up regcache_raw_supply(current_regcache,regno)
+ *
+ */
+void
+arc_debug_fetch_regs (int regno)
+{
+	/* Read all core registers */
+  ENTERARGS("%d",regno);
+
+  int dummyvalue = 0xABCDABCD;
+  unsigned int hw_regno;
+  unsigned int read_buf;
+
+  if( regno < ARC_NR_CORE_REGS )
+  {
+      hw_regno = regno;
+      if(arc_jtag_ops.jtag_read_core_reg(regno,&read_buf)==JTAG_READ_FAILURE)
+	  error("Failure reading from core register 0x%x\n",regno);
+  }
+  else
+  {
+#ifndef ARC4_JTAG    
+    if( regno > ARC_NR_REGS)
+      error("Invalid Register Number\n");
+#endif
+    
+    hw_regno  = arc_get_hw_regnum_mapping (regno);
+    if(arc_jtag_ops.jtag_read_aux_reg(hw_regno,&read_buf)==JTAG_READ_FAILURE)
+	error("Failure reading auxillary register 0x%x",hw_regno);
+  }
+  
+  if(debug_arc_jtag_target_message)
+    {
+      printf_filtered("HW_Regno=0x%x",hw_regno);
+      printf_filtered("Read Regno 0x%x the value 0x%x\n",hw_regno,read_buf);
+    }
+  regcache_raw_supply(current_regcache,regno,&read_buf);
+
+  LEAVEMSG;
+}
+
+
+/* Function: arc_debug_fetch_regs.
+ * Parameters :
+ * 1. int regnum: Register number. If register number is -1.Fetch
+ *                all the registers.Read all core registers here.
+ * Returns : void
+ * Description: 
+ *          Use deprecated register information for this or regcache_read_unsigned .
+ * FIXME: would need to change to use regcache_raw_supply instead.
+ */
+
+
+void
+arc_debug_store_regs (int regno)
+{
+  /* write_all core registers */
+  ENTERARGS("%d", regno);
+  unsigned int hw_regno;
+  unsigned int write_buf;
+
+  if(debug_arc_jtag_target_message)
+    printf_filtered("\n%d",regno);
+
+  regcache_raw_collect(current_regcache,regno,&write_buf);
+  if( regno < ARC_NR_CORE_REGS )
+  {
+      if(arc_jtag_ops.jtag_write_core_reg(regno,write_buf)==JTAG_WRITE_FAILURE)
+	  error("Failure writing 0x%x to core register 0x%x",write_buf,regno);
+  }
+  else
+  {
+#ifndef ARC4_JTAG    
+    if (regno > ARC_NR_REGS)
+      error ("Invalid register number \n");
+#endif
+
+    hw_regno = arc_get_hw_regnum_mapping (regno);
+
+    if(debug_arc_jtag_target_message)
+	printf_filtered("Writing to regno 0x%x the value 0x%x",
+			hw_regno,write_buf);
+    if(arc_jtag_ops.jtag_write_aux_reg(hw_regno,write_buf)==JTAG_WRITE_FAILURE)
+	error("Failure writing 0x%x to auxillary register 0x%x\n",write_buf,hw_regno);
+  }
+
+}
+
+
+/* Function: arc_debug_prepare_to_store.
+ * Parameters :
+ * 1. int regnum: Register number. If register number is -1.Fetch
+ *                all the registers.Read all core registers here.
+ * Returns : void
+ * Description: 
+ *          Use deprecated register information for this. 
+ * FIXME: would need to change to use regcache_raw_supply instead.
+ */
+
+/* This gets called just before store_regs */
+void
+arc_debug_prepare_to_store (void)
+{
+	/* does nothing . Why is this around ? */
+  ENTERMSG;
+}
+
+/* Read or write memory */
+
+
+
+/* Function: arc_debug_xfer_memory. 
+ * Parameters : 
+ * 1. int regnum: Register number. If register number is -1.Fetch
+ *                all the registers.Read all core registers here.
+ * Returns : void
+ * Description: 
+ *    This has been superceded by target_xfer_memory_partial.
+ *
+ */
+int
+arc_debug_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write,
+		      struct mem_attrib *attrib, struct target_ops *target)
+{
+	/* There is no xfer_memory . Its been deprecated in 6.3 .Replace	
+	 * this by target_xfer_memory_partial .
+	 */
+  ENTERARGS("memaddr=%lx, myaddr=%lx, len=%d, write=%d",
+	    memaddr, (unsigned long)myaddr, len, write);
+  
+  return len; /* success */
+}
+
+
+    
+
+LONGEST 
+arc_debug_xfer_partial (struct target_ops *ops,
+			enum target_object object, 
+			const char *annex,
+			void *readbuf, 
+			const void *writebuf,
+			ULONGEST offset, 
+			LONGEST len)
+{
+
+  int i=0, read_num=0, temp_len=0;
+  unsigned int small_buf;
+  char query_type;
+  ULONGEST temp_offset=0;
+  if(debug_arc_jtag_target_message)
+    printf("..Entered arc_debug_xfer_partial()...with offset 0x%x\n",(unsigned int)offset);
+  /* Handle memory */
+  if (object == TARGET_OBJECT_MEMORY)
+    {
+      int saved_status32;
+      int xfered=0;
+      int attempts;
+      errno = 0;
+
+      /* Get out of user mode so that we can read/write anything anywhere.  */
+      saved_status32 = clear_status32_user_bit ();
+
+      if (writebuf != NULL)
+	{
+	    char *buffer=(char *)xmalloc(4);
+	    char *temp_buf = (char *)writebuf;
+
+	    /* Address alignment to integral multiple of four */
+	    temp_offset = offset;
+	    temp_len = temp_offset % 4;
+	    
+	    i = 0;
+	    if(temp_len)
+	    {
+		temp_offset = offset - temp_len;
+		if(debug_arc_jtag_target_message)
+		  {
+		    printf("---- Aligning-----------\n");
+		    printf("calling write_chunk at 0x%x where \
+offset = 0x%x\n",
+			   (unsigned int)temp_offset,(unsigned int)offset);
+		  }
+
+		attempts = 0;
+		do{
+		    if (attempts++ == MEMORY_TRANSFER_ATTEMPTS)
+		      return 0;
+		    xfered = arc_jtag_ops.jtag_memory_chunk_read(temp_offset,
+								 (unsigned int *)buffer,4);
+		}while(xfered != 4);
+		
+		for(i=0;i<len && i<(4-temp_len);i++)
+		    
+		    buffer[i+temp_len]=temp_buf[i];
+
+		attempts = 0;
+		do{
+		    if (attempts++ == MEMORY_TRANSFER_ATTEMPTS)
+		      return 0;
+		    xfered = arc_jtag_ops.jtag_memory_chunk_write(temp_offset,
+								  (unsigned int *)buffer,4);
+		}while(xfered != 4);
+
+		
+		temp_buf = (char *)writebuf + i;
+		temp_offset = offset + i;
+		len = len - i;
+	    }
+	    if(len>0)
+	      len =arc_jtag_ops.jtag_memory_chunk_write(temp_offset,
+							(unsigned int *)temp_buf,len);
+	    if(debug_arc_jtag_target_message)
+	      printf("...leaving arc_debug_xfer_partial() write.. \
+with return value %d",(int)len);
+
+	    restore_status32_user_bit (saved_status32);
+	  return (len + i);
+	}
+      else
+      {
+	  char *buffer=(char *)xmalloc(4);
+	  char *temp_buf = (char *)readbuf;
+	  /* Address alignment to integral multiple of four */
+	  temp_offset= offset;
+	  temp_len= temp_offset % 4 ;
+
+	  i = 0;
+	  if(temp_len)
+	    {
+	      temp_offset = offset - temp_len;
+	      if(debug_arc_jtag_target_message)
+		{
+		  printf("---- Aligning-----------\n");
+		  printf("calling read_chunk at 0x%x where offset =0x%x \n",
+			 (unsigned int)temp_offset,(unsigned int)offset);
+		}
+
+	      attempts = 0;
+	      do{
+		if (attempts++ == MEMORY_TRANSFER_ATTEMPTS)
+		  return 0;
+		xfered = arc_jtag_ops.jtag_memory_chunk_read(temp_offset,(unsigned int *)buffer,4);
+	      }while(xfered != 4);
+	      
+	      for(i=0;i<len && i<(4-temp_len);i++)
+		temp_buf[i]=buffer[i+temp_len];
+	      
+	      temp_buf = (char *)readbuf + i;
+	      temp_offset = offset + i;
+	      len = len - i;
+	    }
+	  if(len>0)
+	    len = arc_jtag_ops.jtag_memory_chunk_read(temp_offset,(unsigned int *)temp_buf,len);
+	  if(debug_arc_jtag_target_message)
+	    {
+	      printf("\nlen=%d",(int)len + temp_len);
+	      printf("...leaving arc_debug_xfer_partial() read.. \
+with return value %d",
+		     (int)len + temp_len);
+	    }
+
+	  restore_status32_user_bit (saved_status32);
+	  return (len + i);
+	  
+      }
+
+    }
+
+  /* ARC auxillary registers: they are 32bits wide and are in a 32 bit
+     address space, although only part of the address space is used.  */
+  else if (object == ARC_TARGET_OBJECT_AUXREGS)
+    {
+      unsigned int regno;
+
+      if (readbuf)
+	{
+	  for (regno = offset; regno < offset+len; ++regno)
+	    {
+	      unsigned int rd;
+
+	      if (arc_jtag_ops.jtag_read_aux_reg (regno, &rd) == JTAG_READ_FAILURE)
+		{
+		  return (regno - offset);
+		}
+	      ((int *)readbuf)[regno - offset] = rd;
+	    }
+	}
+      else if (writebuf)
+	{
+	  for (regno = offset; regno < offset+len; ++regno)
+	    {
+	      if (arc_jtag_ops.jtag_write_aux_reg (regno, ((int*)writebuf)[regno - offset]) ==
+		  JTAG_WRITE_FAILURE)
+		{
+		  return (regno - offset);
+		}
+	    }
+	}
+
+      /* success */
+      return (LONGEST)len;
+    }
+    else
+    {
+	printf("\nRequested target_object not yet supported with arc-jtag");
+    }
+
+  return -1;
+
+}
+
+
+
+
+void
+arc_debug_files_info (struct target_ops *target)
+{
+	/* Do nothing. Just say its a remote target */
+  ENTERMSG;
+}
+
+
+/* Function: arc_debug_insert_breakpoint
+ * Parameters : 
+ * 1. CORE_ADDR addr: Address for breakpoint.
+ * 2. char * contents: Contents for the breakpoint.
+ * Returns : int
+ * Description: 
+ * See if you can insert a hardware breakpoint using the actionpoints
+ * interface. Use brk_s if architecture is ARC700 and you need to use
+ * a software breakpoint.The gdbarch breakpoint should be initialized to
+ * the right value if used with target_arc_debug.
+ *
+ */
+
+
+int
+arc_debug_insert_breakpoint (CORE_ADDR addr, char *contents)
+{
+	
+  ENTERARGS("%x", (unsigned int)addr);
+#ifndef ARC4_JTAG
+  unsigned int bp = 0x20207fff; /*FIXMEA: what does 0x2020 stand for ?*/
+#else
+  unsigned int bp = 0x1ffffe00;
+#endif
+  unsigned int r;
+  int instr_size;
+  const unsigned char *breakpt_instr;
+  breakpt_instr=BREAKPOINT_FROM_PC(&addr,&instr_size);
+
+  /* save the existing value */
+  /* r==0 means the read succeeded */
+  if(debug_arc_jtag_target_message)
+    printf_filtered ("instrcution size = %d and instruction 0x%x",
+	   instr_size, *(unsigned int *)breakpt_instr);
+  r = target_read_memory (addr, contents, instr_size);
+  /* put the breakpoint */
+  if(r==0)
+    r = target_write_memory (addr, (char *)&bp, instr_size);
+  return r;
+}
+
+
+/* Function: arc_debug_remove_breakpoint. 
+ * Parameters : 
+ * 1. CORE_ADDR addr: Address. 
+ * 2. char * contents : contents. 
+ * Returns : int.
+ * Description: 
+ *  Write the old contents back for the breakpoint.
+ *
+ */
+
+int
+arc_debug_remove_breakpoint (CORE_ADDR addr, char *contents)
+{
+  ENTERARGS("%x, %lx", (unsigned int)addr, *(unsigned long *)contents);
+
+  /* write the old value back */
+#ifdef ARC4_JTAG
+  return target_write_memory (addr, contents, 4);
+#else
+  return target_write_memory (addr, contents, 2);
+#endif
+}
+
+
+
+/* Function: arc_debug_kill
+ * Parameters : void.
+
+ * Returns : void.
+ * Description: Heavy duty arsenal.Kill the process. 
+ * Maybe we do a board reset and kill it. Write 1 to Halt
+ * in Status32. 
+ */
+
+void
+arc_debug_kill (void)
+{
+  ENTERMSG;
+
+  /* Do stuff */
+
+  target_mourn_inferior ();
+}
+
+/* Function: arc_debug_load
+ * Parameters :
+ * 1. char * args: Arguments. 
+ * 2. int from_tty: Which terminal.
+ * Returns : void.
+ * Description: Load the program into jtag.
+ */
+
+void
+arc_debug_load (char *args, int from_tty)
+{
+	/* Write to RAM of the ARC700 board by running through the sections .*/
+  asection *bss_section;
+  CORE_ADDR bss_addr;
+  bfd_size_type bss_size;
+  char *zero_buf;
+  int target_errno;
+
+  ENTERARGS("%s", args);
+
+  generic_load(args, from_tty);
+
+  /* Zero the bss, if it exists.  */
+  bss_section = bfd_get_section_by_name (exec_bfd, ".bss");
+  if (bss_section)
+    {
+      bss_addr = bfd_section_lma (exec_bfd, bss_section);
+      bss_size = bfd_get_section_size (bss_section);
+      zero_buf = (char *)xcalloc (bss_size, 1);
+      
+      if (debug_arc_jtag_target_message)
+	printf_filtered("%s: bss at %x, size = %x\n", __FUNCTION__, (unsigned int)bss_addr,(unsigned int)bss_size);
+      
+      target_errno = target_write_memory (bss_addr, zero_buf, bss_size);
+      free (zero_buf);
+      if (target_errno)
+	{
+	  error ("load: error zeroing bss: %s\n", strerror(target_errno));
+	}
+    }
+  else
+    {
+      if (debug_arc_jtag_target_message)
+	printf_filtered("%s: no bss\n", __FUNCTION__);
+    }
+      
+  clear_symtab_users();
+}
+
+/* Function: arc_debug_create_inferior
+ * Parameters :
+ * 1. char * exec_file:
+ * 2. char * args: 
+ * 3. char ** env;
+ * Returns : void.
+ * Description: Set up sanity values for arc_debug_create_inferior. More thought
+ * needed for this. 
+ */
+
+
+void
+arc_debug_create_inferior (char *exec_file, char *args, char **env,int dummy)
+{
+  ENTERARGS("%s,%s", exec_file, args);
+
+  /* If no exec file handed to us, get it from the exec-file command
+     -- with a good, common error message if none is specified.  */
+  if (exec_file == 0)
+    exec_file = get_exec_file (1);
+
+  /* We dont really have a PID or anything, but GDB uses this value to check
+     if the program is running. */
+  inferior_ptid.pid = 42;
+
+  clear_proceed_status();
+  /* -1 means resume from current place
+     TARGET_SIGNAL_0 means dont give it any signal
+     Last arg should be true if you want to single step */
+  //proceed ((CORE_ADDR) -1, TARGET_SIGNAL_0, 0);
+  proceed (bfd_get_start_address (exec_bfd), TARGET_SIGNAL_0, 0);
+}
+
+
+/* Function: arc_debug_mourn_inferior
+ * Parameters :void.
+ * Returns : void.
+ * Description: Set up sanity values for arc_debug_create_inferior. More thought
+ * needed for this. 
+ */
+
+void
+arc_debug_mourn_inferior (void)
+{
+  ENTERMSG;
+
+  unpush_target (&arc_debug_ops);
+
+  generic_mourn_inferior ();
+}
+
+
+/* Function: arc_debug_mourn_inferior
+ * Parameters :ptid_t ptid.
+ * Returns : 1 always. 
+ * Description: Checks for return values .
+ */
+
+
+int
+arc_debug_thread_alive (ptid_t ptid)
+{
+  ENTERMSG;
+  return 1;
+}
+
+
+/* Function: arc_debug_stop
+ * Parameters: void
+ * Returns: void.
+ * Description: Stop the Processor. We stop by writing FH bit to Debug Register . 
+ *	write 1 to the FH bit in the Debug register after 
+ *	polling for the DEBUG register to have no loads pending .
+ */
+void
+arc_debug_stop (void)
+{
+
+  ENTERMSG;
+  int val = 0x2;
+  /* Stop using the FH bit in the debug register. */
+  arc_debug_write_aux_register (ARC_HW_DEBUG_REGNUM, &val);
+  
+}
+
+/* Read core register.  Return 0 on success.  */
+static int
+arc_debug_read_core_register (int hwregno, int *buf)
+{
+  int rd;
+  if(arc_jtag_ops.jtag_read_core_reg(hwregno,&rd)==JTAG_READ_FAILURE)
+      error("Failure reading auxillary register 0x%x",hwregno);
+  *buf = rd;
+  return 0;
+}
+
+/* Read aux register.  Return 0 on success.  */
+static int
+arc_debug_read_aux_register (int hwregno, int *buf)
+{
+  int rd;
+  if(arc_jtag_ops.jtag_read_aux_reg(hwregno,&rd)==JTAG_READ_FAILURE)
+      error("Failure reading auxillary register 0x%x",hwregno);
+  *buf = rd;
+  return 0;
+}
+
+/* Write aux register.  Return 0 on success.  */
+static int
+arc_debug_write_aux_register (int hwregno, int *buf)
+{
+    if(arc_jtag_ops.jtag_write_aux_reg(hwregno, *buf)==JTAG_WRITE_FAILURE)
+	error("Failure writing 0x%x to auxillary register 0x%x\n",*buf,hwregno);
+  return 0;
+}
+
+/* Helper routine for commands added.  */
+/* Print Processor Variant Info.  */
+static void
+arc_print_processor_variant_info (void)
+{
+  struct gdbarch_tdep *tdep  = gdbarch_tdep (current_gdbarch);
+  
+#ifdef ARC4_JTAG
+  if (tdep->arc_processor_variant_info && 
+      tdep->arc_processor_variant_info->arcprocessorversion == A4)
+    {
+      printf_filtered ("A4\n");
+    }
+#else
+  if (tdep->arc_processor_variant_info)
+    {
+      if(tdep->arc_processor_variant_info->arcprocessorversion == ARC700)
+	printf_filtered ("ARC700\n");
+      else
+	printf_filtered ("ARC600\n");
+    }
+#endif
+  else
+    {
+      printf_filtered ("ARC Processor Information not available \n");
+    }
+
+}
+
+
+static void 
+arc_print_bcr_regs (void)
+{
+  int i = 0;
+  unsigned int bcrval = 0;
+  for ( i = 0 ; i < (sizeof(arc_bcr_reg_info) / sizeof (struct arc_reg_info)) ; i++)
+    {
+	if(arc_jtag_ops.jtag_read_aux_reg (arc_bcr_reg_info[i].hw_regno, &bcrval)==JTAG_READ_FAILURE)
+	    error("Failure reading auxillary register 0x%x",arc_bcr_reg_info[i].hw_regno);
+      printf_filtered ("[%02x] %-15s : 0x%02x\n",arc_bcr_reg_info[i].hw_regno,
+		       arc_bcr_reg_info[i].name, bcrval );
+    }
+
+}
+
+static void
+arc_debug_jtag_reset_board (void)
+{
+  arc_jtag_ops.jtag_reset_board();
+}
+
+
+/* Function: init_arc_debug_ops
+ * Parameters: void
+ * Returns: void.
+ * Description: Initialize the jtag operations. 
+ */
+
+void
+init_arc_debug_ops (void)
+{
+  ENTERMSG;
+#ifdef ARC4_JTAG
+  arc_debug_ops.to_shortname = "arcjtag";
+  arc_debug_ops.to_longname = "Target for debugging an A4 board with JTAG.";
+  arc_debug_ops.to_doc = "Debug a remote A4 board via a JTAG"; /* to_doc */
+#else
+  arc_debug_ops.to_shortname = "arcjtag";
+  arc_debug_ops.to_longname = "Target for debugging an ARC700 board with JTAG.";
+  arc_debug_ops.to_doc = "Debug a remote ARC700 board via a JTAG"; /* to_doc */
+#endif
+
+
+  arc_debug_ops.to_open = arc_debug_open;
+  arc_debug_ops.to_close = arc_debug_close;
+  arc_debug_ops.to_attach = arc_debug_attach;
+  arc_debug_ops.to_detach = arc_debug_detach;
+  arc_debug_ops.to_resume = arc_debug_resume;
+  arc_debug_ops.to_wait = arc_debug_wait;
+
+  arc_debug_ops.to_fetch_registers = arc_debug_fetch_regs;
+  arc_debug_ops.to_store_registers = arc_debug_store_regs;
+  arc_debug_ops.to_prepare_to_store = arc_debug_prepare_to_store;
+  //arc_debug_ops.to_xfer_memory = arc_debug_xfer_memory;
+  arc_debug_ops.to_xfer_partial = arc_debug_xfer_partial;
+  arc_debug_ops.to_files_info = arc_debug_files_info;
+  arc_debug_ops.to_insert_breakpoint = arc_debug_insert_breakpoint;
+  arc_debug_ops.to_remove_breakpoint = arc_debug_remove_breakpoint;
+  arc_debug_ops.to_kill = arc_debug_kill;
+  arc_debug_ops.to_load = arc_debug_load;
+
+  arc_debug_ops.to_create_inferior = arc_debug_create_inferior;
+
+  arc_debug_ops.to_mourn_inferior = arc_debug_mourn_inferior;
+  arc_debug_ops.to_thread_alive = arc_debug_thread_alive;
+  arc_debug_ops.to_stop = arc_debug_stop;
+
+  arc_debug_ops.to_terminal_inferior = NULL;
+
+  
+  arc_debug_ops.to_stratum = process_stratum;
+  
+  arc_debug_ops.to_has_all_memory = 1;
+  arc_debug_ops.to_has_memory = 1;
+  arc_debug_ops.to_has_stack = 1;
+  arc_debug_ops.to_has_registers = 1;
+  arc_debug_ops.to_has_execution = 1;
+
+  arc_debug_ops.to_magic = OPS_MAGIC;
+}
+
+
+
+void
+_initialize_arc_debug (void)
+{
+  ENTERMSG;
+  init_arc_debug_ops ();
+  add_target (&arc_debug_ops);
+  add_setshow_boolean_cmd("arcjtag-debug-target",no_class, 
+			  &debug_arc_jtag_target_message,
+			  "Set whether to print arc jtag debug messages.\n",
+			  "Show whether to print arc jtag debug messages.\n",
+			  "If set the jtag debug messages from the target are \
+printed.\n",
+			  "Whether to print debug jtag messages is %s.\n",		  
+			  NULL,NULL,&setlist,&showlist);
+
+  add_setshow_boolean_cmd("arcjtag-debug-statemachine",no_class, 
+			  &(arc_jtag_ops.arc_jtag_state_machine_debug),
+			  "Set whether to print JTAG state machine \
+debug messages \n",
+			  "Show whether to print JTAG state machine \
+debug messages \n",
+			  "If set the JTAG state machine messages are \
+printed.\n",
+			  "Whether to print JTAG state machine debug \
+messages is %s\n",
+			  NULL,NULL,&setlist,&showlist);
+
+  add_setshow_uinteger_cmd("arcjtag-retry-count",no_class, &arcjtag_retry_count,
+			   "Set the number of attempts to be made for \
+a JTAG operation.\n",
+			   "Show the number of attempts to be made for \
+a JTAG operation.\n",
+			   "Indicates the number of times a JTAG operation \
+is attempted before returning a failure.\n",
+			   "The number of times a JTAG operation is attempted \
+before returning a failure is %s.\n",
+			   NULL, NULL, &setlist, &showlist);
+
+  add_cmd ("arc-configuration", class_info, arc_print_processor_variant_info,
+	   "Show ARC configuration information." , &infolist);
+
+  add_cmd ("arc-bcr-registers", class_info, arc_print_bcr_regs,
+           "Show BCR Registers in the ARC Processor Variant", &infolist);
+
+  add_cmd ("arc-reset-board", class_obscure, arc_debug_jtag_reset_board,
+           "Reset the board.", &cmdlist);
+
+}
diff --git a/gdb/arc-jtag.h b/gdb/arc-jtag.h
new file mode 100644
index 0000000..b770a53
--- /dev/null
+++ b/gdb/arc-jtag.h
@@ -0,0 +1,76 @@
+/* Target dependent code for ARC700, for GDB, the GNU debugger.
+
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Contributed by Codito Technologies Pvt. Ltd. (www.codito.com)
+
+   Authors: 
+      Soam Vasani <soam.vasani@codito.com>
+
+   This file is part of GDB.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+
+#define ARC_DEBUG_REG_SH_BIT 	0x40000000
+
+#define RAUX(name, hwregno , desc, gdbregno, version)  ARC_HW_##name##_REGNUM = hwregno , 
+#define RBCR(name, hwregno , desc, gdbregno, version)  ARC_HW_##name##_REGNUM = hwregno , 
+
+
+enum arc_hw_regnums
+  {
+    #include "arc-regnums-defs.h"
+    /* Specific ARCAngel Registers for Caches.  */
+    ARC_HW_ICACHE_IVIC = 0x10 , /* Invalidate Cache. */
+    ARC_HW_ICACHE_CONTROL = 0x11 , /* Disable ICache. ICache control. */
+    ARC_HW_DCACHE_IVIC = 0x47, /* Invalidate Cache. */
+    ARC_HW_DCACHE_CONTROL = 0x48 , /* Disable DCache. DCache Control. */
+  };
+
+#undef RBCR
+#undef RAUX
+
+#define ARC_TARGET_OBJECT_AUXREGS 	-1
+
+#define target_read_aux_reg(readbuf, offset, len)               \
+         (current_target.to_xfer_partial(&current_target,        \
+                                         ARC_TARGET_OBJECT_AUXREGS, NULL, readbuf, NULL, offset, len))
+	  
+#define target_write_aux_reg(writebuf, offset, len)             \
+         (current_target.to_xfer_partial(&current_target,        \
+                                         ARC_TARGET_OBJECT_AUXREGS, NULL, NULL, writebuf, offset, len))
+
+
+static inline int 
+is_arc700 (void)
+{
+  struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch);
+  if(tdep->arc_processor_variant_info->arcprocessorversion == ARC700)
+    return 1;
+  return 0;
+  
+}
+
+static inline int 
+is_arc600 (void)
+{
+  struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch);
+  if(tdep->arc_processor_variant_info->arcprocessorversion == ARC600)
+    return 1;
+  return 0;
+  
+}
+ int debug_arc_jtag_target_message;
diff --git a/gdb/arc-linux-tdep.c b/gdb/arc-linux-tdep.c
new file mode 100644
index 0000000..14d34a6
--- /dev/null
+++ b/gdb/arc-linux-tdep.c
@@ -0,0 +1,506 @@
+/* Target dependent code for ARC700, for GDB, the GNU debugger.
+
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Authors: 
+      Soam Vasani <soam.vasani@codito.com>
+      Ramana Radhakrishnan <ramana.radhakrishnan@codito.com> 
+
+   This file is part of GDB.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+
+#include <string.h>
+
+#include "defs.h"
+#include "osabi.h"
+#include "frame.h"
+#include "regcache.h"
+#include "gdb_assert.h"
+#include "inferior.h"
+#include "reggroups.h"
+#include "solib-svr4.h"
+#include "symtab.h"
+#include "objfiles.h"
+#include "block.h"
+
+#include "arc-tdep.h"
+#include "regset.h"
+
+//#define ARC_DEBUG 1
+
+/* Default Breakpoint instructions used for 
+   ARC700 Linux 
+*/
+unsigned int arc700_linux_breakpoint_size = 2;
+unsigned char arc700_linux_breakpoint_insn[2] = { 0x3e,0x78 } ;
+
+static const char *
+arc_linux_register_name (int regno)
+{
+  static char linux_names[][10] = {"r0", "r1", "r2", "r3", "r4", "r5", "r6",
+				   "r7", "r8", "r9", "r10", "r11", "r12", "r13",
+				   "r14", "r15", "r16", "r17", "r18", "r19", "r20",
+				   "r21", "r22", "r23", "r24", "r25", "r26",
+				   
+				   "bta",
+				   "lp_start", "lp_end", "lp_count",
+				   "status32", "blink",
+				   "fp", "sp", "efa",
+				   /* linux-only registers */
+				   "ret", "orig_r8", "pc",
+
+				   /* pseudo-regs */
+				   "ilink1", "ilink2", "eret",
+				   "status_l1", "status_l2", "erstatus" };
+
+  gdb_assert(ARRAY_SIZE (linux_names) == NUM_REGS + NUM_PSEUDO_REGS);
+  gdb_assert(regno >=0 && regno < NUM_REGS + NUM_PSEUDO_REGS);
+
+  return linux_names[regno];
+}
+
+/*
+ * The kernel stores only one of (ilink1,ilink2,eret).  This is stored in
+ * the ret "register".  ilink1 is stored when the kernel has been entered
+ * because of a level 1 interrupt, etc.
+ *
+ * Same story for (status_l1, status_l2, erstatus).
+ *
+ * This disambiguity has been fixed by adding orig_r8 to pt_regs.
+ * It will take the following values -
+ *    1. if an exception of any kind occurs then orig_r8 >= 0
+ *    2. Int level 1 : -1
+ *    3. Int level 2 : -2
+ *
+ * Registers whose value we don't know are given the value zero.
+ */
+static void
+arc_linux_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
+				int regno, void *buf)
+{
+  int status32, ret, orig_r8;
+  regcache_cooked_read (current_regcache, ARC_ORIG_R8_REGNUM, &orig_r8);
+
+  if(regno == ARC_ILINK1_REGNUM ||
+     regno == ARC_ILINK2_REGNUM ||
+     regno == ARC_ERET_REGNUM)
+    {
+      regcache_cooked_read (current_regcache, ARC_RET_REGNUM, &ret);
+
+      if(regno == ARC_ILINK1_REGNUM)
+	*((unsigned int *)buf) = ((orig_r8 == -1) ? ret : 0);
+      else if(regno == ARC_ILINK2_REGNUM)
+	*((unsigned int *)buf) = ((orig_r8 == -2) ? ret : 0);
+      else if(regno == ARC_ERET_REGNUM)
+	*((unsigned int *)buf) = ((orig_r8 >= 0) ? ret : 0);
+
+    }
+  else if(regno == ARC_STATUS32_L1_REGNUM ||
+	  regno == ARC_STATUS32_L2_REGNUM ||
+	  regno == ARC_ERSTATUS_REGNUM)
+    {
+      regcache_cooked_read (current_regcache, ARC_STATUS32_REGNUM, &status32);
+
+      if(regno == ARC_STATUS32_L1_REGNUM)
+	*((unsigned int *)buf) = ((orig_r8 == -1) ? status32 : 0);
+      else if(regno == ARC_STATUS32_L2_REGNUM)
+	*((unsigned int *)buf) = ((orig_r8 == -2) ? status32 : 0);
+      else if(regno == ARC_ERSTATUS_REGNUM)
+	*((unsigned int *)buf) = ((orig_r8 >= 0) ? status32 : 0);
+    }
+  else
+    internal_error(__FILE__, __LINE__, "arc_pseudo_register_read: bad register number (%d)", regno);
+}
+
+static void
+arc_linux_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
+				 int regno, const void *buf)
+{
+  /* none of our pseudo-regs are writable */
+  internal_error(__FILE__, __LINE__, "arc_pseudo_register_write: bad register number");
+}
+
+/*
+ * print registers in the correct order.
+ *
+ * Why not have the regnums in the right order in the first place ?
+ * Because some of the registers have to be pseudo-registers because of
+ * the way the kernel is written, and because gdb assumes that
+ * pseudo-registers have regnums greater than real register regnums.
+ */
+static void
+arc_linux_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
+				struct frame_info *frame, int regnum, int all)
+{
+  int i;
+
+  if (regnum >= 0)
+    {
+      default_print_registers_info (gdbarch, file, frame, regnum, all);
+      return;
+    }
+
+  /* print all registers */
+
+  /* r0..r26 */
+  for (i=0; i <= 26; ++i)
+    default_print_registers_info (gdbarch, file, frame, i, all);
+
+  default_print_registers_info (gdbarch, file, frame, ARC_FP_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_SP_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_ILINK1_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_ILINK2_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_BLINK_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_LP_COUNT_REGNUM, all);
+  
+  /* now the aux registers */
+  
+  default_print_registers_info (gdbarch, file, frame, ARC_BTA_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_LP_START_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_LP_END_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_EFA_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_ERET_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_STATUS32_L1_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_STATUS32_L2_REGNUM, all);
+  default_print_registers_info (gdbarch, file, frame, ARC_ERSTATUS_REGNUM, all);
+
+  /* show the pc */
+  default_print_registers_info (gdbarch, file, frame, ARC_STOP_PC_REGNUM, all);
+}
+
+
+/*
+ * mov r8,nr_sigreturn
+ * swi 
+ */
+static char arc_sigtramp_insn[] = { 0x8a, 0x20, 0xc1, 0x1d, 0x6f, 0x22, 0x3f, 0x00 };
+
+/* Return whether the frame preceding NEXT_FRAME corresponds to a
+   GNU/Linux sigtramp routine.  */
+static int
+arc_linux_sigtramp_p (struct frame_info *next_frame)
+{
+  CORE_ADDR pc = frame_pc_unwind (next_frame);
+  unsigned char buf[8];
+
+  if (!safe_frame_unwind_memory (next_frame, pc, buf, 8))
+    return 0;
+
+  if (memcmp(buf, arc_sigtramp_insn, 8) == 0)
+    return 1;
+  else
+    {
+      pc -= 4;
+      
+      if (!safe_frame_unwind_memory (next_frame, pc, buf, 8))
+	return 0;
+
+      if (memcmp(buf, arc_sigtramp_insn, 8) == 0)
+	return 1;
+    }
+
+  return 0;
+}
+
+/* Assuming NEXT_FRAME is a frame following a GNU/Linux sigtramp
+   routine, return the address of the associated sigcontext structure.  */
+static CORE_ADDR
+arc_linux_sigcontext_addr (struct frame_info *next_frame)
+{
+  char buf[4];
+  CORE_ADDR sp;
+  
+  frame_unwind_register (next_frame, ARC_SP_REGNUM, buf);
+  sp = extract_unsigned_integer (buf, 4);
+
+  return sp;
+}
+
+int
+arc_linux_register_reggroup_p (int regnum, struct reggroup *group)
+{
+  if(regnum == ARC_ORIG_R8_REGNUM && group == system_reggroup)
+    return 1;
+
+  if(regnum == ARC_RET_REGNUM && group == general_reggroup)
+    return 0;
+
+  return -1;
+}
+
+/* Mapping between the general-purpose registers in `struct
+   sigcontext' format and GDB's register cache layout.
+   arc_linux_sc_reg_offset[i] is the sigcontext offset of GDB regnum `i'.  */
+
+/* From <asm/sigcontext.h>.  */
+static int arc_linux_sc_reg_offset[] =
+{
+  23 * 4,				     /* r0 */
+  22 * 4,				     /* r1 */
+  21 * 4,				     /* r2 */
+  20 * 4,				     /* r3 */
+  19 * 4,				     /* r4 */
+  18 * 4,				     /* r5 */
+  17 * 4,				     /* r6 */
+  16 * 4,				     /* r7 */
+  15 * 4,				     /* r8 */
+  14 * 4,				     /* r9 */
+  13 * 4,				     /* r10 */
+  12 * 4,				     /* r11 */
+  11 * 4,				     /* r12 */
+  -1,					     /* r13 */
+  -1,					     /* r14 */
+  -1,					     /* r15 */
+  -1,					     /* r16 */
+  -1,					     /* r17 */
+  -1,					     /* r18 */
+  -1,					     /* r19 */
+  -1,					     /* r20 */
+  -1,					     /* r21 */
+  -1,					     /* r22 */
+  -1,					     /* r23 */
+  -1,					     /* r24 */
+  -1,					     /* r25 */
+  10 * 4,				     /* r26 */
+  2 * 4,				     /* bta */
+  3 * 4,				     /* lp_start */
+  4 * 4,				     /* lp_end */
+  5 * 4,				     /* lp_count */
+  6 * 4,				     /* status32 */
+  8 * 4,				     /* blink */
+  9 * 4,				     /* fp */
+  1 * 4,				     /* sp */
+  -1,					     /* efa */
+  7 * 4,				     /* ret */
+  -1,					     /* orig_r8 */
+  -1, 					     /* stop_pc */
+};
+
+
+/* Set the program counter for process PTID to PC.  */
+
+static void
+arc700_linux_write_pc (CORE_ADDR pc, ptid_t ptid)
+{
+  ULONGEST val;
+  write_register_pid (PC_REGNUM, pc, ptid);
+
+  /* We must be careful with modifying the program counter.  If we
+     just interrupted a system call, the kernel might try to restart
+     it when we resume the inferior.  On restarting the system call,
+     the kernel will try backing up the program counter even though it
+     no longer points at the system call.  This typically results in a
+     SIGSEGV or SIGILL.  We can prevent this by writing `-1' in the
+     "orig_r8" pseudo-register.
+
+     Note that "orig_r8" is saved when setting up a dummy call frame.
+     This means that it is properly restored when that frame is
+     popped, and that the interrupted system call will be restarted
+     when we resume the inferior on return from a function call from
+     within GDB.  In all other cases the system call will not be
+     restarted.  */
+  write_register_pid (ARC_ORIG_R8_REGNUM, -3, ptid);
+}
+
+
+/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c.
+
+   This is called on every single step thru the PLT and runtime resolver.
+
+   This function:
+   1) decides whether a PLT has sent us into the linker to resolve
+      a function reference, and 
+   2) if so, tells us where to set a temporary breakpoint that will
+      trigger when the dynamic linker is done.  */
+
+CORE_ADDR
+arc_linux_skip_solib_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
+{
+  /* For uClibc 0.9.26.
+
+     An unresolved PLT entry points to "__dl_linux_resolve", which calls
+     "__dl_linux_resolver" to do the resolving and then eventually jumps to
+     the function.
+
+     So we look for the symbol `_dl_linux_resolver', and if we are there,
+     we set a breakpoint at the return address, and continue.  */
+
+  /* lookup_minimal_symbol didn't work, for some reason.  */
+  struct symbol *resolver 
+    = lookup_symbol_global ("_dl_linux_resolver", 0, VAR_DOMAIN, 0);
+  
+#ifdef ARC_DEBUG
+  printf("--- arc_linux_skip_solib_resolver: pc = %x, resolver at %x\n", pc,
+	 resolver ? BLOCK_START (SYMBOL_BLOCK_VALUE (resolver)) : 0);
+#endif
+  
+  if (resolver && (BLOCK_START (SYMBOL_BLOCK_VALUE (resolver))) == pc)
+    {
+	return frame_pc_unwind (get_current_frame ());
+    }
+
+  return 0;
+}      
+
+
+/* arcompact_linux_core_reg_offsets[i] is the offset in the .reg section of GDB
+   regnum i .
+   
+   From include/asm-arc/user.h in the ARC Linux sources.  */
+static int arcompact_linux_core_reg_offsets[] = {
+  22 * 4,    /* r0 */
+  21 * 4,    /* r1 */
+  20 * 4,    /* r2 */
+  19 * 4,    /* r3 */
+  18 * 4,    /* r4 */
+  17 * 4,    /* r5 */
+  16 * 4,    /* r6 */
+  15 * 4,    /* r7 */
+  14 * 4,    /* r8 */
+  13 * 4,    /* r9 */
+  12 * 4,    /* r10 */
+  11 * 4,    /* r11 */
+  10 * 4,    /* r12 */
+  39 * 4,    /* r13 */
+  38 * 4,    /* r14 */
+  37 * 4,    /* r15 */
+  36 * 4,    /* r16 */
+  35 * 4,    /* r17 */
+  34 * 4,    /* r18 */
+  33 * 4,    /* r19 */
+  32 * 4,    /* r20 */
+  31 * 4,    /* r21 */
+  30 * 4,    /* r22 */
+  29 * 4,    /* r23 */
+  28 * 4,    /* r24 */
+  27 * 4,    /* r25 */
+   9 * 4,    /* r26 */
+   1 * 4,    /* bta */
+   2 * 4,    /* lp_start */
+   3 * 4,    /* lp_end */
+   4 * 4,    /* lp_count */
+   5 * 4,    /* status32 */
+   7 * 4,    /* blink */
+   8 * 4,    /* fp */
+  25 * 4,    /* sp */
+  -1,        /* efa */
+   6 * 4,    /* ret */
+  24 * 4,    /* orig_r8 */
+  40 * 4,    /* stop_pc */
+};
+
+/* Extract the register values found in the ABI GREGSET, storing their
+   values in REGCACHE.  */
+static void
+arcompact_linux_supply_gregset (struct regcache *regcache,
+				int regnum, const void *gregs, size_t size)
+{
+  int regi;
+  int arc_num_gprs = ARRAY_SIZE (arcompact_linux_core_reg_offsets);
+  const bfd_byte *buf = gregs;
+
+  for (regi = 0; regi < arc_num_gprs; regi++)
+    {
+      if (arcompact_linux_core_reg_offsets[regi] > 0)
+	regcache_raw_supply (regcache, regi,
+			     buf + arcompact_linux_core_reg_offsets[regi]);
+    }
+}
+
+/* Call the right architecture variant's supply_gregset function.  For now,
+   we only have ARCompact.  */
+static void
+arc_linux_supply_gregset (const struct regset *regset,
+			  struct regcache *regcache,
+			  int regnum, const void *gregs, size_t size)
+{
+  arcompact_linux_supply_gregset (regcache, regnum, gregs, size);
+}
+
+/* Functions for handling core files.
+   The first element is a parameter to pass the rest of the functions.  We
+   don't need it.
+   supply_gregset is for reading the core file.
+   collect_regset, which we haven't defined, would be for writing the core
+   file.  */
+static struct regset arc_linux_gregset = {
+  NULL, arc_linux_supply_gregset
+};
+
+/* This is called through gdbarch.  */
+static const struct regset *
+arc_linux_regset_from_core_section (struct gdbarch *core_arch,
+				    const char *sect_name, size_t sect_size)
+{
+  if (strcmp (sect_name, ".reg") == 0)
+    return &arc_linux_gregset;
+
+  return NULL;
+}
+
+/* Add the signal stuff to gdbarch->tdep.  */
+static void
+arc_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+  
+  tdep->sigtramp_p = arc_linux_sigtramp_p;
+  tdep->sigcontext_addr = arc_linux_sigcontext_addr;
+  tdep->sc_reg_offset = arc_linux_sc_reg_offset;
+  tdep->sc_num_regs = ARRAY_SIZE (arc_linux_sc_reg_offset);
+
+  tdep->arc_breakpoint_size = arc700_linux_breakpoint_size;
+  tdep->arc_breakpoint_insn = arc700_linux_breakpoint_insn;
+
+  set_gdbarch_num_regs (gdbarch, ARC_NR_REGS);
+  set_gdbarch_num_pseudo_regs (gdbarch, ARC_NR_PSEUDO_REGS);
+  
+  set_gdbarch_pc_regnum (gdbarch, ARC_STOP_PC_REGNUM);
+  set_gdbarch_register_name (gdbarch, arc_linux_register_name);
+
+  set_gdbarch_software_single_step (gdbarch, arc_software_single_step);
+
+  set_gdbarch_write_pc (gdbarch, arc700_linux_write_pc);
+
+  tdep->pc_regnum_in_sigcontext = ARC_RET_REGNUM;
+
+
+  set_gdbarch_pseudo_register_read (gdbarch, arc_linux_pseudo_register_read);
+  set_gdbarch_pseudo_register_write (gdbarch, arc_linux_pseudo_register_write);
+
+  set_gdbarch_print_registers_info (gdbarch, arc_linux_print_registers_info);
+
+  tdep->register_reggroup_p = arc_linux_register_reggroup_p;
+  
+  tdep->lowest_pc = 0x74;
+
+  tdep->arc_processor_variant_info = NULL;
+  set_gdbarch_regset_from_core_section (gdbarch, 
+					arc_linux_regset_from_core_section);
+  /* GNU/Linux uses SVR4-style shared libraries.  */
+  set_solib_svr4_fetch_link_map_offsets
+    (gdbarch, svr4_ilp32_fetch_link_map_offsets);
+
+  set_gdbarch_skip_solib_resolver (gdbarch, arc_linux_skip_solib_resolver);
+}
+
+void
+_initialize_arc_linux_tdep (void)
+{
+  gdbarch_register_osabi (bfd_arch_arc, 0, GDB_OSABI_LINUX,
+			  arc_linux_init_abi);
+}
diff --git a/gdb/arc-regnums-defs.h b/gdb/arc-regnums-defs.h
new file mode 100644
index 0000000..6071ee4
--- /dev/null
+++ b/gdb/arc-regnums-defs.h
@@ -0,0 +1,108 @@
+/* Target dependent code for ARC700, for GDB, the GNU debugger.
+
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Contributed by Codito Technologies Pvt. Ltd. (www.codito.com)
+
+   Authors: 
+      Ramana Radhakrishnan <ramana.radhakrishnan@codito.com> 
+
+   This file is part of GDB.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+
+#ifdef RAUX
+#ifdef ARC4_JTAG
+
+RAUX ( STATUS , 0x0, "Status Regnum " , ARC_STATUS_REGNUM , A4 )
+RAUX ( SEMAPHORE ,  0x1, "Semaphore Regnum ", ARC_SEMAPHORE_REGNUM , A4  ) 
+RAUX ( LP_START , 0x2, "Loop Start" , ARC_LP_START_REGNUM , A4  )
+RAUX ( LP_END , 0x3, "Loop End", ARC_LP_END_REGNUM , A4 )
+RAUX ( IDENTITY , 0x4, "Identity", ARC_IDENTITY_REGNUM , A4 )
+RAUX ( DEBUG , 0x5, "Debug" , ARC_DEBUG_REGNUM , A4 )
+
+#else
+
+RAUX ( STATUS , 0x0, "Status Regnum (obsolete)" , ARC_STATUS_REGNUM , ARCompact )
+RAUX ( SEMAPHORE ,  0x1, "Semaphore Regnum ", ARC_SEMAPHORE_REGNUM , ARCompact  ) 
+RAUX ( LP_START , 0x2, "Loop Start" , ARC_LP_START_REGNUM , ARCompact  )
+RAUX ( LP_END , 0x3, "Loop End", ARC_LP_END_REGNUM , ARCompact )
+RAUX ( IDENTITY , 0x4, "Identity", ARC_IDENTITY_REGNUM , ARCompact )
+RAUX ( DEBUG , 0x5, "Debug" , ARC_DEBUG_REGNUM , ARCompact )
+RAUX ( PC, 0x6,"PC" , ARC_PC_REGNUM ,ARCompact )
+RAUX ( STATUS32 ,0xA,"STATUS32", ARC_STATUS32_REGNUM , ARCompact ) 
+RAUX ( STATUS32_L1 , 0xB, "STATUS32 register in case of L1 interrupts" ,ARC_STATUS32_L1_REGNUM , ARCompact )
+RAUX ( STATUS32_L2 , 0xC, "STATUS32 register in case of L2 interrupts" ,ARC_STATUS32_L2_REGNUM , ARCompact )
+RAUX ( COUNT0 , 0x21, "Processor Timer 1 Count Value", ARC_COUNT0_REGNUM , ARCompact )
+RAUX ( CONTROL0 , 0x22, "Processor Timer 1 Control Value" , ARC_CONTROL0_REGNUM, ARCompact)
+RAUX ( LIMIT0 , 0x23, "Processor Timer 1 Limit Value" , ARC_LIMIT0_REGNUM, ARCompact )
+RAUX ( INT_VECTOR_BASE , 0x25, "Interrupt Vector Base Register", ARC_INT_VECTOR_BASE_REGNUM , ARCompact )
+RAUX ( AUX_IRQ_MACMODE , 0x41, "Aux IRQ MAC Mode " , ARC_AUX_MACMODE_REGNUM , ARCompact )
+RAUX ( AUX_IRQ_LV12 , 0x42, "Aux IRQ Level 2 " , ARC_AUX_IRQ_LV12_REGNUM , ARCompact )
+RAUX ( COUNT1 , 0x100, "Processor Timer 1 Count Value", ARC_COUNT1_REGNUM , ARCompact )
+RAUX ( CONTROL1 , 0x101, "Processor Timer 1 Control Value" , ARC_CONTROL1_REGNUM , ARCompact)
+RAUX ( LIMIT1 , 0x102, "Processor Timer 1 Limit Value", ARC_LIMIT1_REGNUM , ARCompact)
+RAUX ( AUX_IRQ_LEV , 0x200, "Interrupt Level programming. ", ARC_AUX_IRQ_LEV_REGNUM , ARCompact)
+RAUX ( AUX_IRQ_HINT , 0x201, "Software Triggered Interrupt" , ARC_AUX_IRQ_HINT_REGNUM, ARCompact )
+RAUX ( ERET , 0x400, "Exception Return " , ARC_ERET_REGNUM, ARC700 )
+RAUX ( ERBTA , 0x401, "Exception BTA ", ARC_ERBTA_REGNUM, ARC700 )
+RAUX ( ERSTATUS , 0x402, "Exception Return Status" , ARC_ERSTATUS_REGNUM, ARC700 )
+RAUX ( ECR , 0x403, "Exception Cause Register" , ARC_ECR_REGNUM, ARC700 )
+RAUX ( EFA , 0x404, "Exception Fault Address" , ARC_EFA_REGNUM, ARC700 )
+RAUX ( ICAUSE1 , 0x40A, "Interrupt Cause (Level 1)", ARC_ICAUSE1_REGNUM,ARC700 )
+RAUX ( ICAUSE2 , 0x40B, "Interrupt Cause (Level 2)", ARC_ICAUSE2_REGNUM, ARC700)
+RAUX ( AUX_IENABLE , 0x40C, "Interrupt Mask Programming", ARC_AUX_IENABLE_REGNUM, ARC700 )
+RAUX ( AUX_ITRIGGER , 0x40D, "Interrupt Sensitivity Programming", ARC_AUX_ITRIGGER_REGNUM, ARC700 )
+RAUX ( XPU , 0x410, "User Mode Extension Permissions", ARC_XPU_REGNUM, ARC700 )
+RAUX ( BTA , 0x412, "Branch Target Address", ARC_BTA_REGNUM, ARC700 )
+RAUX ( BTA_L1 , 0x413, "Branch Target Address in Level 1", ARC_BTA_L1_REGNUM, ARC700 )
+RAUX ( BTA_L2 , 0x414, "Branch Target Address in Level 2", ARC_BTA_L2_REGNUM, ARC700 )
+RAUX ( AUX_IRQ_PULSE_CANCEL , 0x415, "Interrupt Pulse Cancel", ARC_AUX_IRQ_PULSE_CANCEL_REGNUM, ARC700 )
+RAUX ( AUX_IRQ_PENDING , 0x416, "Interrupt Pending Register", ARC_AUX_IRQ_PENDING_REGNUM, ARC700 )
+#endif // ARC4_JTAG
+#endif // RAUX
+
+#ifdef RBCR
+#ifndef ARC4_JTAG
+
+RBCR ( DCCM_BASE_BUILD , 0x61, "Base address for DCCM.", ARC_BCR_1_REGNUM, ARCompact)
+RBCR ( CRC_BASE_BUILD , 0x62, "BCRBCR for CRC Unit.", ARC_BCR_2_REGNUM , ARCompact)
+RBCR ( BTA_LINK_BUILD , 0x63, "Interrupt Link Registers Available for BTA",ARC_BCR_3_REGNUM, ARCompact )
+RBCR ( DVBF_BUILD , 0x64, "BCRBCR for Dual Viterbi Instruction.",ARC_BCR_4_REGNUM, ARCompact )
+RBCR ( TEL_INSTR_BUILD , 0x65, "BCRBCR for Extended Arithmetic Instructions. ",ARC_BCR_5_REGNUM, ARCompact)
+RBCR ( MEMSUBSYS , 0x67, "BCRBCR for Memory Subsystem. ",ARC_BCR_7_REGNUM, ARCompact)
+RBCR ( VECBASE_AC_BUILD ,0x68, "BCRBCR for Interrupt Vector Base. ", ARC_BCR_8_REGNUM,ARCompact) 
+RBCR ( P_BASE_ADDRESS , 0x69, "Peripheral Base Address" , ARC_BCR_9_REGNUM , ARCompact) 
+RBCR ( MMU_BUILD , 0x6F, "MMU Build. " , ARC_BCR_F_REGNUM, ARCompact)
+RBCR ( ARCANGEL_BUILD , 0x70, "ARC Angel Build config. ", ARC_BCR_10_REGNUM, ARCompact)
+RBCR ( D_CACHE_BUILD , 0x72, "D Cache Build Config. ", ARC_BCR_12_REGNUM , ARCompact )
+RBCR ( MADI_BUILD , 0x73 , "Multiple ARC Debug Interface. " , ARC_BCR_13_REGNUM , ARCompact)
+RBCR ( DCCM_BUILD , 0x74, "BCRBCR for DCCM.(Data Closely coupled Memory", ARC_BCR_14_REGNUM, ARCompact)
+RBCR ( TIMER_BUILD , 0x75, "BCRBCR for Timers. " , ARC_BCR_15_REGNUM , ARCompact)
+RBCR ( AP_BUILD, 0x76, "Actionpoints build. ", ARC_BCR_16_REGNUM , ARCompact )
+RBCR ( ICACHE_BUILD , 0x77, "Instruction Cache BCR", ARC_BCR_17_REGNUM , ARCompact )
+RBCR ( ICCM_BUILD , 0x78, "ICCM BCRBCR (Instruction Closely Coupled Memory.", ARC_BCR_18_REGNUM , ARCompact)
+RBCR ( DSPRAM_BUILD , 0x79, "DSP RAM Build", ARC_BCR_19_REGNUM , ARCompact)
+RBCR ( MAC_BUILD , 0x7A, "MAC Unit Build", ARC_BCR_1A_REGNUM , ARCompact)
+RBCR ( MULTIPLY_BUILD , 0x7B, "(32 X 32) Multiply Unit Build", ARC_BCR_1B_REGNUM , ARCompact)
+RBCR ( SWAP_BUILD , 0x7C, "SWAP Build", ARC_BCR_1C_REGNUM , ARCompact)
+RBCR ( NORM_BUILD , 0x7D ,"NORM Unit Build", ARC_BCR_1D_REGNUM, ARCompact)
+RBCR ( MINMAX_BUILD , 0x7E, "Minmax Unit Build", ARC_BCR_1E_REGNUM, ARCompact)
+RBCR ( BARREL_BUILD , 0x7F, "Barrel Shifter Build", ARC_BCR_1F_REGNUM , ARCompact) 
+
+
+#endif // ARC4_JTAG
+#endif // RBCR 
diff --git a/gdb/arc-tdep.c b/gdb/arc-tdep.c
new file mode 100644
index 0000000..8b54257
--- /dev/null
+++ b/gdb/arc-tdep.c
@@ -0,0 +1,1999 @@
+/* Target dependent code for ARC700, for GDB, the GNU debugger.
+
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Contributed by Codito Technologies Pvt. Ltd. (www.codito.com)
+
+   Authors: 
+      Soam Vasani <soam.vasani@codito.com>
+      Ramana Radhakrishnan <ramana.radhakrishnan@codito.com> 
+
+   This file is part of GDB.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+#include <string.h>
+
+#include "defs.h"
+#include "arch-utils.h"
+#include "dis-asm.h"
+#include "gdbtypes.h"
+#include "frame.h"
+#include "frame-unwind.h"
+#include "target.h"
+#include "breakpoint.h"
+#include "inferior.h"
+#include "regcache.h"
+#include "reggroups.h"
+#include "trad-frame.h"
+#include "dwarf2-frame.h"
+#include "gdbtypes.h"
+#include "gdb_assert.h"
+#include "gdbcore.h"
+#include "observer.h"
+#include "osabi.h"
+
+#include "opcode/arc.h"
+
+#include "arc-tdep.h"
+
+
+//#define ARC_DEBUG 1
+
+#if ARC_DEBUG
+#  define ENTERMSG printf ("--- entered %s:%s()\n", __FILE__, __FUNCTION__)
+#  define ENTERARGS(fmt, args...) printf ("--- entered %s:%s(" fmt ")\n", __FILE__, __FUNCTION__, args)
+#  define LEAVEMSG printf ("--- exited %s:%s()\n", __FILE__, __FUNCTION__)
+#else
+#  define ENTERMSG
+#  define ENTERARGS(fmt, args...) 
+#  define LEAVEMSG
+#endif
+
+#define ARC_STATUS32_A1 0x8
+#define ARC_STATUS32_A2 0x10
+#define ARC_STATUS32_AE 0x20
+#define ARC_STATUS32_L  0x100
+
+
+static CORE_ADDR arc_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp);
+/* The frame unwind cache for the ARC 
+ */
+
+struct arc_unwind_cache
+{
+  /* blink offset in stack */
+  int blink_offset ;
+
+  /* Caller's PC */
+  CORE_ADDR prev_pc;
+
+  
+  /* The stack pointer at the time this frame was created; i.e. the
+     caller's stack pointer when this function was called.  It is used
+     to identify this frame.  */
+  
+  CORE_ADDR prev_sp;
+  /* The frame base */
+  CORE_ADDR frame_base;
+  /* Frame size */
+  int framesize;
+  
+  /* offset of sp from the stack frame base */
+  LONGEST sp_offset;
+  /* offset of fp from the stack frame base */
+  LONGEST fp_offset;
+  /* Is this a leaf function */
+  int is_leaf ;
+  /* Is there a frame pointer */
+  int uses_fp;
+  
+  
+  /* Offsets for each register in the stack frame */
+  struct trad_frame_saved_reg *saved_regs;
+};
+
+
+
+
+/* Function Prototypes */
+
+static CORE_ADDR arc_unwind_sp (struct gdbarch *gdbarch, 
+			       struct frame_info *next_frame);
+
+static CORE_ADDR arc_unwind_pc (struct gdbarch *gdbarch, 
+			       struct frame_info *next_frame);
+
+static struct arc_unwind_cache * arc_frame_unwind_cache (struct frame_info *next_frame, 
+							 void ** this_prologue);
+
+static CORE_ADDR arc_scan_prologue (CORE_ADDR pc, 
+				     struct frame_info *next_frame,
+				     struct arc_unwind_cache *info);
+
+
+static int arc_binutils_reg_to_regnum (int reg);
+
+extern struct arcDisState arcAnalyzeInstr (  bfd_vma address,disassemble_info* info );
+extern struct arcDisState a4AnalyzeInstr (  bfd_vma address,disassemble_info* info );
+
+/* defined in opcodes, but there's no header file with this prototype... */
+disassembler_ftype arcompact_get_disassembler (void *);
+
+/*  Standard register type for the ARC platform . 
+ *  It would be builtin_type_uint32 until 
+ *  we consider the DSP extensions 
+ */
+
+static struct type *
+arc_register_type (struct gdbarch *gdbarch, int regnum)
+{
+  return builtin_type_uint32;
+}
+
+
+void printFrameInfo(struct arc_unwind_cache * info)
+{
+#ifdef ARC_DEBUG
+  printf("-------------------\n");
+  printf("%lx \n",info );
+  printf("prev_sp = %lx \n",info->prev_sp);
+  printf("prev_pc = %lx \n",info->prev_pc);
+  printf("frame_base is %lx \n",info->frame_base);
+  printf("framesize is %lx \n",info->framesize);
+  printf("Blink offset %lx \n",info->blink_offset);
+  printf("sp_offset = %lx \n",info->sp_offset );
+  printf("fp_offset is %lx \n",info->fp_offset);
+  printf("is_leaf = %d, uses_fp=%d",info->is_leaf, info->uses_fp);
+#endif
+}
+
+/* Print the instruction state returned 
+   by the disassembler . Used for internal
+   debugging only 
+*/
+
+void printInsnState(struct arcDisState state)
+{
+#ifdef ARC_DEBUG
+  printf("---------------------------------\n");
+  printf("Instruction Length %d\n", state.instructionLen);
+  printf("Opcode [0x%x] : Cond [%x]\n", state._opcode, state._cond);
+  printf("Words 1 [%lx] : 2 [%lx]\n", state.words[0], state.words[1]);
+  printf("ea present [%x] : memload [%x]\n", state._ea_present, state._mem_load);
+  printf("Load length [%d]:\n", state._load_len);
+  printf("Address writeback [%d]\n", state._addrWriteBack);
+  printf("ea reg1 is [%x] offset [%x] \n", state.ea_reg1, state._offset);
+  printf("ea reg2 is [%x] \n", state.ea_reg2);
+  printf("operands buffer is %s \n", state.operandBuffer);
+  printf("SourceType is %d \n",state.sourceType);
+  printf("Flow is %d\n",state.flow);
+  printf("Branch is %d,'%c'\n",state.isBranch, state.isBranch);
+#endif
+}
+
+
+/* Scan the prologue and update the 
+ * corresponding frame cache for the frame unwinder for unwinding
+ * frames without debug info . In such a situation GDB attempts to 
+ * parse the prologue for this purpose . This currently would attempt
+ * to parse the prologue generated by our gcc 2.95 .(We should support 
+ * Metaware generated binaries at some suitable point of time )
+ * This function is called with the pc where gdb stopped , the next_frame 
+ * to be filled in (if need be?) and the existing cached info . 
+
+ * scan_prologue is called by our unwinder as well 
+ * as from skip_prologue in the case that it cannot detect 
+ * the end of the prologue. next_frame is set to NULL if we are called from 
+ * arc_skip_prologue in an attempt to discover the end of the prologue. In
+ * such a case we don't fill the frame info that is passed to us :-)
+
+ * Todos. 
+ * 1. Support 32 bit normal frames generated by GCC 2.95 .
+ * 2. Support 16 and 32 bit mixed frames generated by GCC 2.95
+ * 3. Support 32 bit normal variadic function frames by GCC 2.95
+ * 4. Support 32 bit normal frames from GCC 3.4.x with variadic args
+ * 5. Support 16 and 32 bit normal frames from GCC 3.4.x with variadic args
+ * 6. Support 16 and 32 bit mixed frames generated by GCC 3.4.x 
+ * 7. Support Metaware generated prologues .( The difference is 
+ * in the use of thunks to identify the saving and restoring of 
+ * callee saves :-) May have to do some hackery even in next_pc. 
+ * since the call is going to create its own set of problems 
+ * with our stack setup :-( 
+ * We attempt to use the disassembler interface from the opcodes
+ * library to do our disassembling .
+
+ * The usual 32 bit normal 
+ * gcc -O0 prologue looks like this. 
+
+ * Complete Prologue for all GCC frames (Cases #1 to #6 in Todos above)
+
+ * sub  sp, sp, limm    ; space for variadic arguments.
+ * st.a blink, [sp,-4]  ; push blink (if not a leaf function) 
+ * sub  sp, sp , limm   ; (optional space creation for callee saves )
+ * st   r13, [sp]    ; pushes of all callee saves.
+ * st   r14, [sp,4]  ; pushes of more callee saves.
+ * XXXX
+ * st.a fp , [sp,-4]  ; push fp (if fp has to be saved ) 
+ * mov  fp , sp ; Set the current frame up correctly 
+ * sub  sp , sp , #immediate ; Create space for local vars on the stack.
+ */
+
+
+
+/* Macros to be used with disassembling the prologue 
+ * and update the frame info.The *FI macros are to update
+ * the frame info and the ACT macros are to actually do the 
+ * action on a corresponding match. 
+ *
+*/
+#define CHECKOPDSTRING(targetcheck,searchstring)  \
+                               if(strstr(targetcheck,searchstring) == targetcheck)  \
+                                     {continue;}
+
+#define CHECKOPDSTRINGANDACT(targetcheck,searchstring,action)  \
+                               if(strstr(targetcheck,searchstring) == targetcheck)  \
+                                     {\
+                                       action;\
+				       continue;}
+
+
+/* The frame info changes by changing the decrementing
+   the sp_offset and setting the leaf function to be NIL; 
+   Also the offset of the blink register from the previous
+   value of sp is calculated. Finally this can be updated 
+   as 
+   info->blink_offset = info-> prev_sp + info->blink_offset ;
+   Also the addition below is coz the offsets are usually negative 
+*/
+
+#define PUSHBLINKACT do { \
+                          if(info) \
+                            {      \
+                              info->sp_offset += current_instr._offset; \
+                              info->blink_offset = info->sp_offset ; \
+                              info->is_leaf = 0;\
+                            }}while(0);
+                      
+
+#define ISPUSHBLINK(state) CHECKOPDSTRING(state.operandBuffer,"blink") 
+#define ISPUSHBLINKFI(state) CHECKOPDSTRINGANDACT(state.operandBuffer,"blink",PUSHBLINKACT) 
+
+
+#define PUSHFPACT    do { \
+                          if(info)  \
+                            {       \
+                               info->sp_offset += current_instr._offset ; \
+                               info->fp_offset = -info->sp_offset; \
+                            }}while(0);
+                             
+#define ISPUSHFP(state)    CHECKOPDSTRING(state.operandBuffer,"fp")
+#define ISPUSHFPFI(state)    CHECKOPDSTRINGANDACT(state.operandBuffer,"fp",PUSHFPACT)
+#define ISINSTRUCTION(insnname,searchstring)    !strcmp(insnname,searchstring)
+
+
+
+#define UPDATEFPACT    do {\
+                             if(info) {\
+					 info->uses_fp = 1;\
+			       }}while(0);
+
+
+
+#define ISUPDATEFPFI(state)  \
+ if(ISINSTRUCTION(state.instrBuffer,"mov")) \
+{ \
+  CHECKOPDSTRINGANDACT(state.operandBuffer,"fp,sp",UPDATEFPACT); \
+}
+
+
+
+#define ISUPDATEFP(state)  \
+ if(ISINSTRUCTION(state.instrBuffer,"mov")) \
+{ \
+  CHECKOPDSTRING(state.operandBuffer,"fp,sp") \
+}
+
+
+
+#define ISSUBSP(state)   \
+if(ISINSTRUCTION(state.instrBuffer,"sub"))\
+{ \
+  CHECKOPDSTRING(state.operandBuffer,"sp,sp") \
+}
+
+#define UPDATESTACKSPACE(state) do { \
+                                 if(info){ \
+/* Eat up sp,sp */  \
+                                      int tmp = atoi(state.operandBuffer + 6); \
+                                      info->sp_offset -= tmp; \
+                                        }}while(0);
+
+
+#define ISSUBSPFI(state)   \
+if(ISINSTRUCTION(state.instrBuffer,"sub") \
+   || ISINSTRUCTION(state.instrBuffer,"sub_s"))\
+{ \
+  CHECKOPDSTRINGANDACT(state.operandBuffer,"sp,sp",UPDATESTACKSPACE(state)) \
+}
+
+/*Function to scan the prologue of a A4 binary
+
+ARCtangent-A4 Prolog
+ The stack back-trace data structure is a 16-byte structure which is
+  used to save the return register (blink, 4 bytes), the frame pointer
+  register (fp, 4-bytes) and 8-bytes is reserved.
+ 
+ The compiler-generated prolog code does the following:
+  --> Allocates space for register arguments in case of variadic function
+        (functions with variable argument lists)
+  --> Saves the return address register (blink)
+  --> Saves the caller's frame pointer (fp), if required, and
+        sets the new frame pointer to this location
+  --> Decrements the stack pointer to account for the new stack frame
+  --> Saves required non-volatile general-purpose registers into the
+        register save area
+  --> Stores the arguments above the stack back-trace data structure
+
+
+  Demo Patterns:
+     st         blink,[sp,4] ; Saves the return address
+     st         fp,[sp] ; Saves the callers frame pointer
+     mov        fp,sp   ; Saves 
+     sub        sp,sp,24
+
+0xa  538e7e20     sub        sp,sp,32     ; Space for variadic args
+0x2  100e3e04     st         blink,[sp,4] ; Saves the return address
+0x2  100e3600     st         fp,[sp]      ; Saves the callers frame pointer
+0xc  636e3800     mov        fp,sp        ; Resets stack pointer to fp
+0xa  538e7e18     sub        sp,sp,24     ; Decrements sp to add for new
+                                          ; stack frame
+0x2  100d81fc     st         r0,[fp,-4]   ; Stores the args 
+0x2  100d83f8     st         r1,[fp,-8]   ; ----"-------
+     ...
+
+*/
+
+/* FIXMEA:
+called from arc_skip_prologue as
+     skip_pc = arc_scan_prologue(pc,NULL,NULL);
+        Then it is supposed to return the first valid pc
+	after the prologue
+
+   Prologue analysis does the rest...  
+   Currently our scan prologue does not
+    support getting input for the frame unwinder
+
+  
+  pc = frame_func_unwind(next_frame);
+  arc_scan_prologue (pc, next_frame, info);
+
+*/
+
+#ifdef ARC4_JTAG
+static CORE_ADDR 
+a4_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
+		    struct arc_unwind_cache *info)
+{
+  /* End of prologue */
+  CORE_ADDR prologue_ends_pc = pc;
+  int i = 0;
+  struct arcDisState current_instr, instr_in_delay;
+  int insn_length;
+
+  /* Initializations to use the opcodes 
+   * library .
+   */
+  
+  struct disassemble_info di;
+
+  unsigned int saved_regs_mask = 0;
+  /* An arbitrary length on the length of the 
+     prologue. If next_frame is NULL this means that there was 
+     no debug info and we are called from arc_skip_prologue
+  */
+  /*FIXMEANOW: pc + 64 is probably the max size of the prologue*/
+  CORE_ADDR final_pc = (next_frame)?frame_pc_unwind(next_frame):pc+(16*4);
+  
+  
+
+
+  if (info)
+    {
+      /* All functions start as leaf functions until 
+	 we identify push blink 
+      */
+      info->is_leaf = 1;
+    }
+  
+
+
+  /* Initializations to use the opcodes 
+   * library .
+   */
+  init_disassemble_info(&di, gdb_stderr, fprintf_unfiltered);
+  di.arch = gdbarch_bfd_arch_info(current_gdbarch)->arch;
+  di.mach = gdbarch_bfd_arch_info(current_gdbarch)->mach;
+  di.endian = gdbarch_byte_order(current_gdbarch);
+  di.read_memory_func = target_read_memory;
+  
+  
+  for (prologue_ends_pc= pc;
+       prologue_ends_pc< final_pc; 
+       prologue_ends_pc += current_instr.instructionLen ) /*FIXMEA: This could as
+							    well be 4 */
+    {
+      current_instr = a4AnalyzeInstr(prologue_ends_pc, &di);
+      printInsnState(current_instr);
+#ifdef ARC_DEBUG
+      printf("Prologue PC: %d\n", prologue_ends_pc);
+      printf("Final PC: %d\n", final_pc);
+#endif
+
+
+      if (current_instr._opcode == 0x2)
+	{
+	  // Saves the return address    st blink,[sp,4]   0x100e3e04
+	  // Save the callers fp         st fp,[sp]        0x100e3600
+	  // Saves the args              st rX,[fp, #imm]  0x100d8xxx
+	  if (current_instr.ea_reg1 == 28)
+	    {
+	      if( strstr(current_instr.operandBuffer,"blink") == current_instr.operandBuffer)
+		{
+                  if(info)
+		    {      
+		      info->sp_offset += current_instr._offset;
+ //		      info->blink_offset = info->sp_offset ;
+		      info->blink_offset = current_instr._offset;
+		      info->is_leaf = 0;
+
+#ifdef ARC_DEBUG
+		      printf("Blink instruction:\n");
+		      printFrameInfo(info);
+#endif
+		    }
+		  continue;
+		}
+	      else
+		if(strstr(current_instr.operandBuffer,"fp") == current_instr.operandBuffer)
+		{
+		  if(info)
+		    {
+/* 		      info->sp_offset += current_instr._offset ; */
+/* 		      info->fp_offset = info->sp_offset; */
+		      info->fp_offset = 0;
+		    }
+		  continue;
+		}
+	    }
+	  else if (current_instr.ea_reg1 == 27)
+	    {
+	      /* Saving of arguments onto the stack using the
+		 frame pointer (r27).  */
+	      if(info)
+		{
+		  // Save regs offsets 
+		}
+#ifdef ARC_DEBUG	      
+	      printf(" Saving registers onto stack\n%s\n",current_instr.operandBuffer);
+#endif	      
+	      continue;
+	    }
+	  //	  ISPUSHBLINK(current_instr);
+	}
+      else if (current_instr._opcode == 0xc)
+	{
+	  // Resets stack pointer to fp
+	  // 0x636e3800
+	  //	  636e3800     mov        fp,sp
+	  if (current_instr.words[0] == 0x636e3800)
+	    {
+	      if (info)
+		{
+		  info->uses_fp = 1;
+		}
+	      continue;
+	    }
+	}
+      else if (current_instr._opcode == 0xa)
+	{
+	  // Decrements stackpointer to add for new stack frame
+	  // 0x538e7e18   sub        sp,sp,#imm
+	  // 538e7e20     sub        sp,sp,32
+	  if( current_instr.words[0] == 0x538e7e20)
+	    {
+	      //sub sp,sp, 32  //// variadic
+	      if (info)
+		{
+		  int tmp = atoi(current_instr.operandBuffer + 6); 
+		  info->sp_offset -= tmp; 
+		}
+	      continue;
+	    }
+	  else if((current_instr.words[0] & 0xffffff00) == 0x538e7e00)
+	    {
+	      // sub sp,sp,xx
+	      if(info)
+		{
+		  int tmp = atoi(current_instr.operandBuffer + 6); 
+		  info->sp_offset -= tmp; 
+		}
+	      continue;
+	    }
+	}
+
+      /* Found a instruction that is not in
+         the prologue*/
+#ifdef ARC_DEBUG
+      printf("End of Prologue reached \n");
+#endif
+      break;
+    }
+
+  /* Means we were called from skip_prologue */
+  if((next_frame == NULL)&& (info == NULL))
+    {
+      return prologue_ends_pc;
+    }
+
+
+  info->framesize = -info->sp_offset;
+  /* Compute the previous frame's stack pointer (which is also the
+     frame's ID's stack address), and this frame's base pointer.  */
+  if(info->uses_fp)
+    {
+
+      ULONGEST this_base;
+      /* The SP was moved to the FP.  This indicates that a new frame
+         was created.  Get THIS frame's FP value by unwinding it from
+         the next frame.  */
+      frame_unwind_unsigned_register(next_frame, ARC_FP_REGNUM,
+				     &this_base);
+      info->frame_base = this_base;
+      info->saved_regs[ARC_FP_REGNUM].addr = info->frame_base;
+
+      /* The previous sp is the current frame base + the offset of the
+	 fp in the current frame */
+      info->prev_sp = info->frame_base + info->fp_offset;
+      for(i = 13; i < 26 ; i++ )
+	{
+	  if(saved_regs_mask & (1 << i))
+	    info->saved_regs[i].addr += info->frame_base ;
+	}
+      
+      printFrameInfo(info);
+   
+    }
+  else
+    {
+      ULONGEST this_base;
+      /* Assume that the FP is this frame's SP but with that pushed
+         stack space added back.  */
+      frame_unwind_unsigned_register (next_frame, ARC_SP_REGNUM, &this_base);
+      info->frame_base = this_base;
+
+      /* In such a case it would be the previous SP + the size of the current frame */
+      info->prev_sp = info->frame_base + info->framesize;
+     
+    }
+  
+
+  if(!info->is_leaf)
+    {
+
+      /* Usually blink is saved before the callee save registers and
+	 below the space created for variadic arguments  . We maintain
+	 info->blink_offset as negative when we stored it initially
+       */
+      info->saved_regs[ARC_BLINK_REGNUM].addr = info->prev_sp + info->blink_offset;
+#ifdef ARC_DEBUG
+      printf("blink offset is [%x] \n",info->blink_offset);
+#endif
+    }
+      
+    /* The PC is found in blink (the actual register or located on the stack).  */
+  // FIXMEA:
+  //info->saved_regs[ARC_STATUS_REGNUM] |= (info->saved_regs[ARC_BLINK_REGNUM] & 0xffffff)>>2;
+  info->saved_regs[ARC_STATUS_REGNUM] = info->saved_regs[ARC_BLINK_REGNUM];
+  return prologue_ends_pc;
+
+}
+#endif
+
+static CORE_ADDR 
+arc_scan_prologue (CORE_ADDR pc, struct frame_info *next_frame,
+		    struct arc_unwind_cache *info)
+{
+#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf("\narc_scan_prologue called\n");
+#endif
+#else
+  /* End of prologue */
+  CORE_ADDR prologue_ends_pc = pc;
+  int i = 0;
+  struct arcDisState current_instr, instr_in_delay;
+  int insn_length;
+
+  /* Initializations to use the opcodes 
+   * library .
+   */
+  
+  struct disassemble_info di;
+
+  unsigned int saved_regs_mask = 0;
+  /* An arbitrary length on the length of the 
+     prologue. If next_frame is NULL this means that there was 
+     no debug info and we are called from arc_skip_prologue
+  */
+  CORE_ADDR final_pc = (next_frame)?frame_pc_unwind(next_frame):pc+64; 
+  
+  
+
+
+  if (info)
+    {
+      /* All functions start as leaf functions until 
+	 we identify push blink 
+      */
+      info->is_leaf = 1;
+      
+    }
+  
+
+
+  /* Initializations to use the opcodes 
+   * library .
+   */
+  init_disassemble_info(&di, gdb_stderr, fprintf_unfiltered);
+  di.arch = gdbarch_bfd_arch_info(current_gdbarch)->arch;
+  di.mach = gdbarch_bfd_arch_info(current_gdbarch)->mach;
+  di.endian = gdbarch_byte_order(current_gdbarch);
+  di.read_memory_func = target_read_memory;
+  
+  
+  for(prologue_ends_pc= pc; prologue_ends_pc< final_pc; 
+      prologue_ends_pc += current_instr.instructionLen )
+    {
+      current_instr = arcAnalyzeInstr(prologue_ends_pc, &di);
+      printInsnState(current_instr);
+        /* Might be a push or a pop */
+      if(current_instr._opcode == 0x3)
+	{
+	  if(current_instr._addrWriteBack)
+	    {
+	      /* This is a st.a  */
+	      if((current_instr.ea_reg1 == 28) &&
+		 (current_instr._offset == -4))
+		{
+		  
+		  /* This is a push something at sp */
+		  /* Is it a push of the blink */
+		  ISPUSHBLINKFI(current_instr);
+		  /* Is it a push for fp */
+		  ISPUSHFPFI(current_instr);
+		  
+		}
+	      
+	    } 
+	  else
+	    {
+	      /* Is this a store of some register onto 
+		 the stack using the stack pointer.*/
+	      if(current_instr.ea_reg1 == 28)
+		{
+		  if(current_instr.sourceType == ARC_REGISTER )
+		    {
+		      /* R13..R26 are the callee saved registers.  [R27 (fp)
+			 is also a callee saved register, but it's usually
+			 pushed using st.a and so handled in the st.a case
+			 above.]  */
+		      if((current_instr.source_operand.registerNum > 12 
+			  && current_instr.source_operand.registerNum <= 26))
+			{
+			  if(info)
+			    {
+			      printFrameInfo(info);
+			      /* Save up the offsets for the correct instruction */
+			      info->saved_regs[current_instr.source_operand.registerNum].addr
+				= - info->sp_offset - current_instr._offset;
+			      saved_regs_mask |= (1 << current_instr.source_operand.registerNum);
+			    }
+			  continue;
+			}
+		      
+		    }		  
+		  
+		}
+	      /* Is this the store of some register on the 
+		 stack using the frame pointer. We check 
+		 for argument registers getting saved and
+		 restored.
+	      */
+	      if(current_instr.ea_reg1 == 27)
+		if((current_instr.source_operand.registerNum <= 7))
+		  {
+		    /* Saving argument registers.Don't save them in saved_regs, just skip. 
+		     */
+		    continue;
+		  }
+		
+	      
+	      
+	    }
+	}
+
+      if(current_instr._opcode == 0x4)
+	{
+	  /* A major opcode 0x4 instruction */
+	  /* We are usually interested in a 
+	     mov or a sub */
+	  ISUPDATEFPFI(current_instr);
+	  ISSUBSPFI(current_instr);
+	}
+      if(current_instr._opcode == 0x18)
+	{
+	  /* sub_s sp,sp,constant */
+	  ISSUBSPFI(current_instr);
+	  /* push_s blink */
+	  if(strcmp(current_instr.instrBuffer,"push_s") == 0)
+	    {
+	      if(strcmp(current_instr.operandBuffer,"blink") == 0)
+		{
+		  if(info) 
+		    {   
+		      info->sp_offset += 4; 
+		      info->blink_offset = info->sp_offset ; 
+		      info->is_leaf = 0;
+		    }
+		  continue;
+		}
+	    }
+	}
+
+      /* If we reach here . we have 
+       * reached end of the prologue
+       */
+      break;
+      
+    }
+  
+  /* Means we were called from skip_prologue */
+  if((next_frame == NULL)&& (info == NULL))
+    {
+      return prologue_ends_pc;
+    }
+  
+  
+  info->framesize = -info->sp_offset;
+  /* Compute the previous frame's stack pointer (which is also the
+     frame's ID's stack address), and this frame's base pointer.  */
+  if(info->uses_fp)
+    {
+
+      ULONGEST this_base;
+      /* The SP was moved to the FP.  This indicates that a new frame
+         was created.  Get THIS frame's FP value by unwinding it from
+         the next frame.  */
+      frame_unwind_unsigned_register(next_frame, ARC_FP_REGNUM,
+				     &this_base);
+      info->frame_base = this_base;
+      info->saved_regs[ARC_FP_REGNUM].addr = info->frame_base;
+
+      /* The previous sp is the current frame base + the offset of the 
+	 fp in the current frame */
+      info->prev_sp = info->frame_base + info->fp_offset;
+      for(i = 13; i < 26 ; i++ )
+	{
+	  if(saved_regs_mask & (1 << i))
+	    info->saved_regs[i].addr += info->frame_base ;
+	}
+      
+      printFrameInfo(info);
+   
+    }
+  else
+    {
+      ULONGEST this_base;      
+      /* Assume that the FP is this frame's SP but with that pushed
+         stack space added back.  */
+      frame_unwind_unsigned_register (next_frame, ARC_SP_REGNUM, &this_base);
+      info->frame_base = this_base;
+
+      /* In such a case it would be the previous SP + the size of the current frame */
+      info->prev_sp = info->frame_base + info->framesize;
+     
+    }
+  
+
+  if(!info->is_leaf)
+    {
+
+      /* Usually blink is saved before the callee save registers and 
+	 below the space created for variadic arguments  . We maintain
+	 info->blink_offset as negative when we stored it initially
+       */
+      info->saved_regs[ARC_BLINK_REGNUM].addr = info->prev_sp + info->blink_offset;
+#ifdef ARC_DEBUG
+      printf("blink offset is [%x] \n",info->blink_offset);
+#endif
+    }
+      
+    /* The PC is found in blink (the actual register or located on the stack).  */
+  info->saved_regs[PC_REGNUM] = info->saved_regs[ARC_BLINK_REGNUM];
+  /*info->saved_regs[ARC_PC_REGNUM] = info->saved_regs[ARC_BLINK_REGNUM];*/
+  return prologue_ends_pc;
+#endif
+}
+
+
+/* Skip the prologue for the function at pc. 
+ * This is done by checking from the line  
+ * information picked up during dwarf reading
+ * FIXME: more stuff to be added when we 
+ * parse the prologue.
+ */
+
+static CORE_ADDR
+arc_skip_prologue (CORE_ADDR pc)
+{
+  //#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_skip_prologue called\n");
+#endif
+  // FIXMEA: cleanup #else
+  unsigned long inst;
+  unsigned long addend = 4;
+  CORE_ADDR skip_pc = pc;
+  CORE_ADDR func_addr, func_end = 0;
+  char *func_name;
+  struct symtab_and_line sal;
+
+  /* If we're in a dummy frame, don't even try to skip the prologue.  */
+  if (deprecated_pc_in_call_dummy (pc))
+    return pc;
+
+  /* See what the symbol table says.  */
+
+  if (find_pc_partial_function (pc, &func_name, &func_addr, &func_end))
+    {
+      struct symbol *sym;
+
+      /* Found a function.  */
+      sym = lookup_symbol (func_name, NULL, VAR_DOMAIN, NULL, NULL);
+      if (sym && SYMBOL_LANGUAGE (sym) != language_asm)
+        {
+	  /* Don't use this trick for assembly source files.  */
+	  sal = find_pc_line (func_addr, 0);
+	  if ((sal.line != 0) && (sal.end < func_end))
+	    return sal.end;
+        }
+    }
+  
+#ifdef ARC4_JTAG 
+  skip_pc = a4_scan_prologue(pc, NULL, NULL);
+#else
+  skip_pc = arc_scan_prologue(pc,NULL,NULL);
+#endif  
+  return skip_pc;		/* End of prologue */
+
+  //#endif
+}
+
+/* Breakpoint from pc. Return whatever is in the tdep 
+ * structure. The tdep structure is changed depending 
+ * on the correct target / architecture chosen. 
+ */
+
+static const unsigned char *
+arc_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
+{
+
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  *lenptr = tdep->arc_breakpoint_size;
+  return tdep->arc_breakpoint_insn;
+}
+
+
+/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
+   dummy frame.  The frame ID's base needs to match the TOS value
+   saved by save_dummy_frame_tos(), and the PC match the dummy frame's
+   breakpoint. */
+
+static struct frame_id
+arc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+  return frame_id_build (arc_unwind_sp (gdbarch, next_frame),
+			 frame_pc_unwind (next_frame));
+}
+
+/* The workhorse : frame_unwind_cache for the ARC700 platform .
+ */
+static struct arc_unwind_cache *
+arc_frame_unwind_cache  (struct frame_info *next_frame,
+			 void **this_prologue_cache)
+{
+  //#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_frame_unwind_cache called\n ");
+#endif
+  //#else
+  CORE_ADDR pc;
+  struct arc_unwind_cache *info;
+  int i;
+
+ 
+  if ((*this_prologue_cache))
+    return (*this_prologue_cache);
+  
+  info = FRAME_OBSTACK_ZALLOC (struct arc_unwind_cache);
+  (*this_prologue_cache) = info;
+  info->saved_regs = trad_frame_alloc_saved_regs (next_frame);
+
+  /* Zero all fields.  */
+  info->blink_offset = 0;
+  info->prev_pc = 0;
+  info->prev_sp = 0;
+  info->frame_base = 0;
+  info->framesize = 0;
+  info->sp_offset = 0;
+  info->fp_offset = 0;
+  info->prev_pc = 0;
+  info->is_leaf = 0;
+  info->uses_fp = 0;
+
+  /* Prologue analysis does the rest...  */
+  /* Currently our scan prologue does not
+   * support getting input for the frame unwinder
+   */ 
+  
+  pc = frame_func_unwind(next_frame);
+#ifdef ARC4_JTAG
+  a4_scan_prologue (pc, next_frame, info);
+#else
+  arc_scan_prologue (pc, next_frame, info);
+#endif
+
+  return info;
+  //#endif
+}
+
+
+
+/*
+ * Construct frame id for the normal frame 
+ */
+
+static void
+arc_frame_this_id (struct frame_info *next_frame,
+		    void **this_prologue_cache,
+		    struct frame_id *this_id)
+{
+  // FIXMEA: cleanup #ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\n arc_frame_this_id called()\n  ");
+#endif
+  //#else
+
+  struct arc_unwind_cache *info
+    = arc_frame_unwind_cache (next_frame, this_prologue_cache);
+  CORE_ADDR base;
+  CORE_ADDR func;
+  struct frame_id id;
+
+  /* The FUNC is easy.  */
+  func = frame_func_unwind (next_frame);
+
+ /* This is meant to halt the backtrace at the entry point (_start).  */
+  if (func <= gdbarch_tdep (current_gdbarch)->lowest_pc)
+    return;
+  
+  /* Hopefully the prologue analysis either correctly determined the
+     frame's base (which is the SP from the previous frame), or set
+     that base to "NULL".  */
+  base = info->prev_sp;
+  if (base == 0)
+    return;
+
+  id = frame_id_build (base, func);
+
+  (*this_id) = id;
+  //#endif
+
+}
+
+
+/* 
+ * Unwind and obtain the register information 
+ */
+static void
+arc_frame_prev_register (struct frame_info *next_frame,
+			  void **this_prologue_cache,
+			  int regnum, int *optimizedp,
+			  enum lval_type *lvalp, CORE_ADDR *addrp,
+			  int *realnump, void *bufferp)
+{
+  // FIXMEA:
+  //#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\n arc_frame_prev_register() called for regnum %d\n ",regnum );
+#endif
+  //#else
+  struct arc_unwind_cache *info
+    = arc_frame_unwind_cache (next_frame, this_prologue_cache);
+
+
+  /* If we are asked to unwind the PC, then we need to return blink
+     instead.  The saved value of PC points into this frame's
+     prologue, not the next frame's resume location.  */
+#ifdef ARC4_JTAG
+  if (regnum == ARC_STATUS_REGNUM)
+#else
+  if (regnum == PC_REGNUM)
+#endif
+    regnum = ARC_BLINK_REGNUM;
+
+  /* SP is generally not saved to the stack, but this frame is
+     identified by NEXT_FRAME's stack pointer at the time of the call.
+     The value was already reconstructed into PREV_SP.  */
+  if (regnum == ARC_SP_REGNUM)
+    {
+      *lvalp = not_lval;
+      if (bufferp)
+	store_unsigned_integer (bufferp, 4, info->prev_sp);
+      return;
+    }
+
+
+  trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
+				optimizedp, lvalp, addrp, realnump, bufferp);
+
+
+#ifdef ARC_DEBUG
+  printf("-*-*-*\n Regnum =%d, realnump=%d,%d \n",regnum, (char *)(bufferp), *((char*)bufferp));
+#endif
+  //#endif
+}
+
+
+
+
+static const struct frame_unwind arc_frame_unwind = {
+  NORMAL_FRAME,
+  arc_frame_this_id,
+  arc_frame_prev_register
+};
+
+const struct frame_unwind *
+arc_frame_sniffer (struct frame_info *next_frame)
+{
+  return &arc_frame_unwind;
+}
+
+
+/* read-only registers */
+static int
+arc_cannot_store_register (int regno)
+{
+  if(
+#ifndef ARC4_JTAG
+     regno == ARC_EFA_REGNUM ||
+     regno == ARC_ERET_REGNUM ||
+     regno == ARC_STATUS32_L1_REGNUM ||
+     regno == ARC_STATUS32_L2_REGNUM ||
+     regno == ARC_ERSTATUS_REGNUM ||
+#endif
+     regno == ARC_ILINK1_REGNUM ||
+     regno == ARC_ILINK2_REGNUM 
+     )
+    {
+      /* No warning should be printed.  arc_cannot_store_register being
+	 called does not imply that someone is actually writing to regnum.  */
+
+      /*warning("writing to read-only register: %s\n", arc_register_name(regno));*/
+      return 1;
+    }
+  return 0;
+}
+
+/* Returns true if the insn at PC is a branch. *fall_thru is the address of
+   the next insn.  *target is the branch target. */
+static int
+arc_next_pc(CORE_ADDR pc, CORE_ADDR *fall_thru, CORE_ADDR *target)
+{
+#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_next_pc called\n");
+#endif
+#else
+  struct arcDisState instr, instr_d;
+  int insn_length;
+  struct disassemble_info di;
+  int two_targets = 0;
+  
+  init_disassemble_info(&di, NULL, NULL);
+  di.arch = gdbarch_bfd_arch_info(current_gdbarch)->arch;
+  di.mach = gdbarch_bfd_arch_info(current_gdbarch)->mach;
+  di.endian = gdbarch_byte_order(current_gdbarch);
+  di.read_memory_func = target_read_memory;
+  
+  instr = arcAnalyzeInstr(pc, &di);
+
+  *fall_thru = pc + instr.instructionLen;
+
+#ifdef ARC_DEBUG
+  printf("--- arc_next_pc(%x) = %x, isBranch = %d, tcnt = %d [%x], flow = %s (%d), "
+	 "reg for indirect jump = %d, nullifyMode = %s\n",
+	 pc, *fall_thru, instr.isBranch, instr.tcnt, instr.targets[0],
+	 (instr.flow == direct_jump || instr.flow == direct_call) ? "direct" : "indirect",
+	 instr.flow,
+	 instr.register_for_indirect_jump,
+	 (instr.nullifyMode == BR_exec_always ? "delay slot" : "no delay"));
+#endif
+
+  if(instr.isBranch)
+    {
+      two_targets = 1;
+      
+      if(instr.flow == direct_jump || instr.flow == direct_call)
+	*target = instr.targets[0];
+      else
+	regcache_cooked_read(current_regcache,
+			     arc_binutils_reg_to_regnum(instr.register_for_indirect_jump),
+			     target);
+    }
+
+  /* for instructions with delay slots, the fall thru is not the instruction
+     immediately after the branch instruction, but the one after that */
+  if(instr.isBranch && instr.nullifyMode == BR_exec_always)
+    {
+      instr_d = arcAnalyzeInstr(*fall_thru, &di);
+      *fall_thru += instr_d.instructionLen;
+    }
+
+  /* zero-overhead loops:
+        if(status32[L] == 0 && next_pc == lp_end && lp_count > 1)
+          next_pc = lp_start;
+  */
+  {
+    unsigned int lp_end, lp_start, lp_count, status32;
+
+    regcache_cooked_read(current_regcache, ARC_LP_START_REGNUM, &lp_start);
+    regcache_cooked_read(current_regcache, ARC_LP_END_REGNUM, &lp_end);
+    regcache_cooked_read(current_regcache, ARC_LP_COUNT_REGNUM, &lp_count);
+#ifndef ARC4_JTAG    
+    regcache_cooked_read(current_regcache, ARC_STATUS32_REGNUM, &status32);
+#endif
+
+    if( !(status32 & ARC_STATUS32_L) && *fall_thru == lp_end && lp_count > 1)
+      {
+	two_targets = 1;
+	*target = lp_start;
+      }
+  }
+  
+  return two_targets;
+#endif //
+}
+
+/* this is called with insert_breakpoints_p = 1 before single-stepping and
+   with insert_breakpoints_p = 0 after the step */
+void
+arc_software_single_step(enum target_signal ignore, int insert_breakpoints_p)
+{
+#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_software_single_step called\n" );
+#endif
+#else
+  typedef char binsn_quantum[BREAKPOINT_MAX];
+
+  static CORE_ADDR fall_thru, branch_target;
+  static binsn_quantum break_mem[2];
+  static char two_breakpoints;
+  CORE_ADDR pc;
+
+  {
+#ifdef ARC_DEBUG
+    unsigned int efa, ret;
+    regcache_cooked_read(current_regcache, ARC_EFA_REGNUM, &efa);
+    //    regcache_cooked_read(current_regcache, ARC_RET_REGNUM, &ret);
+    
+    printf("--- arc_software_single_step, efa = %x, ret = %x, (%s)\n", efa, ret,
+	   (insert_breakpoints_p ? "add" : "remove"));
+#endif
+  }
+  
+  if (insert_breakpoints_p)
+    {
+      pc = read_pc ();
+      two_breakpoints = arc_next_pc (pc, &fall_thru, &branch_target);
+
+      if (two_breakpoints && branch_target == pc) 
+	{
+	  warning ("Cannot single-step branch-to-self or single instruction zero overhead loop,\n"
+		   "    Stepping across it.");
+	  /* Don't insert/remove the branch-target breakpoint.  */
+	  two_breakpoints = 0;
+	}
+      
+      target_insert_breakpoint (fall_thru, break_mem[0]);
+      if(two_breakpoints)
+	target_insert_breakpoint (branch_target, break_mem[1]);
+    }
+  else
+    {
+      target_remove_breakpoint (fall_thru, break_mem[0]);
+      if(two_breakpoints)
+	target_remove_breakpoint (branch_target, break_mem[1]);
+    }
+#endif
+}
+
+/*
+ * mapping from binutils/gcc register number to
+ * GDB register number ("regnum")
+ */
+static int
+arc_binutils_reg_to_regnum (int reg)
+{
+#ifdef ARC4_JTAG
+    if (reg >= 0 && reg <= 26)
+    return reg;
+  else if (reg == 27)			     /* fp */
+    return ARC_FP_REGNUM;
+  else if (reg == 28)			     /* sp */
+    return ARC_SP_REGNUM;
+  else if (reg == 29)			     /* ilink1 */
+    return ARC_ILINK1_REGNUM;
+  else if (reg == 30)			     /* ilink2 */
+    return ARC_ILINK2_REGNUM;
+  else if (reg == 31)			     /* blink */
+    return ARC_BLINK_REGNUM;
+
+#else
+  /* from gcc/config/arc/arc.h */
+
+  if (reg >= 0 && reg <= 26)
+    return reg;
+  else if (reg == 27)			     /* fp */
+    return ARC_FP_REGNUM;
+  else if (reg == 28)			     /* sp */
+    return ARC_SP_REGNUM;
+  else if (reg == 29)			     /* ilink1 */
+    return ARC_ILINK1_REGNUM;
+  else if (reg == 30)			     /* ilink2 */
+    return ARC_ILINK2_REGNUM;
+  else if (reg == 31)			     /* blink */
+    return ARC_BLINK_REGNUM;
+  else if (reg >= 32 && reg <= 59)	     /* reserved */
+    ;
+  else if (reg == 60)			     /* lp_count */
+    return ARC_LP_COUNT_REGNUM;
+  else if (reg == 61)			     /* reserved */
+    ;
+  else if (reg == 62)			     /* no such register */
+    ;
+/*   else if (reg == 63)			     /\* PCL *\/ */
+/*     return ARC_RET_REGNUM; */
+
+#endif
+  warning ("Unmapped register #%d encountered\n", reg);
+  return -1; 
+}
+
+
+static void
+arc_add_reggroups (struct gdbarch *gdbarch)
+{
+  reggroup_add (gdbarch, general_reggroup);
+  reggroup_add (gdbarch, all_reggroup);
+  reggroup_add (gdbarch, system_reggroup);
+}
+
+int
+arc_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
+			  struct reggroup *group)
+{
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  int tdep_answer;
+  
+  tdep_answer = tdep->register_reggroup_p (regnum, group);
+  if(tdep_answer != -1)
+    return tdep_answer;
+  
+  if (group == all_reggroup)
+    return 1;
+  else if (group == save_reggroup || group == restore_reggroup)
+    {
+      /* don't save/restore read-only registers. */
+      return (!arc_cannot_store_register(regnum)); 
+    }
+  else if (group == general_reggroup)
+    {
+#ifndef ARC4_JTAG
+      if (regnum == ARC_STATUS32_REGNUM)
+	return 0;
+#endif
+      return 1;
+    }
+  else
+    {
+      internal_error(__FILE__, __LINE__, "bad register group");
+    }
+}
+
+
+
+static void
+arc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
+                            struct dwarf2_frame_state_reg *reg)
+{
+#ifdef ARC4_JTAG
+  // FIXMEA: Clean up.  if ( debug_arc_jtag_target_message)
+#ifdef ARC_DEBUG  
+  printf ("\n arc_dwarf2_frame_init_reg called.\n Regno no:%d,0x%x\n",regnum,regnum);
+#endif
+    /* The return address column.  */
+  if (regnum == ARC_STATUS_REGNUM)
+    reg->how = DWARF2_FRAME_REG_RA;
+  
+  /* The call frame address.  */
+  if (regnum == ARC_SP_REGNUM)
+    reg->how = DWARF2_FRAME_REG_CFA;
+
+#else
+  /* The return address column.  */
+  if (regnum == PC_REGNUM)
+    reg->how = DWARF2_FRAME_REG_RA;
+  
+  /* The call frame address.  */
+  if (regnum == ARC_SP_REGNUM)
+    reg->how = DWARF2_FRAME_REG_CFA;
+#endif
+}
+
+static CORE_ADDR
+arc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+  ULONGEST pc;
+#ifdef ARC4_JTAG
+  frame_unwind_unsigned_register (next_frame, ARC_STATUS_REGNUM, &pc);
+  pc = pc & 0x00ffffff;
+  pc = pc << 2;
+#else
+  frame_unwind_unsigned_register (next_frame, PC_REGNUM, &pc);
+#endif
+  return pc;
+}
+
+static CORE_ADDR
+arc_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
+{
+  ULONGEST sp;
+  frame_unwind_unsigned_register (next_frame, SP_REGNUM, &sp);
+  return sp;
+}
+
+
+
+static void
+arc_extract_return_value (struct type *type, struct regcache *regcache,
+			  void *valbuf)
+{
+  //#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_extract_return_value called\n");
+#endif
+  //#else
+  ULONGEST val;
+  int len = TYPE_LENGTH (type);
+  
+  if (len <= 4)
+    {
+      /* Get the return value from R0.  */
+      regcache_cooked_read_unsigned (regcache, ARC_RETURN1_REGNUM, &val);
+      store_unsigned_integer (valbuf, len, val);
+    }
+  else if (len <= 8)
+    {
+      /* Get the return value from R0 and R1.  */
+      /* R0 holds the lower-order bytes */
+      regcache_cooked_read_unsigned (regcache, ARC_RETURN1_REGNUM, &val);
+      store_unsigned_integer (valbuf, 4, val);
+      regcache_cooked_read_unsigned (regcache, ARC_RETURN2_REGNUM, &val);
+      store_unsigned_integer ((char *)valbuf + 4, len - 4, val);
+    }
+  else
+    error ("arc_extract_return_value: type length too large");
+  //#endif
+}
+
+static void
+arc_store_return_value (struct type *type, struct regcache *regcache,
+			const void *valbuf)
+{
+  //#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_store_return_value called\n ");
+#endif
+  //#else
+  ULONGEST val;
+  int len = TYPE_LENGTH (type);
+  
+  if (len <= 4)
+    {
+      /* Put the return value in R0.  */
+      val = extract_unsigned_integer (valbuf, len);
+      regcache_cooked_write_unsigned (regcache, ARC_RETURN1_REGNUM, val);
+    }
+  else if (len <= 8)
+    {
+      /* Put the return value in R10 and R11.  */
+      val = extract_unsigned_integer (valbuf, 4);
+      regcache_cooked_write_unsigned (regcache, ARC_RETURN1_REGNUM, val);
+      val = extract_unsigned_integer ((char *)valbuf + 4, len - 4);
+      regcache_cooked_write_unsigned (regcache, ARC_RETURN2_REGNUM, val);
+    }
+  else
+    error ("arc_store_return_value: type length too large.");
+  //#endif
+}
+
+
+static enum return_value_convention
+arc_return_value (struct gdbarch *gdbarch, struct type *valtype,
+		  struct regcache *regcache, void *readbuf,
+		  const void *writebuf)
+{
+  //#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_return_value called");
+#endif
+  //#else
+  /* This will change with the ABI */
+  int struct_return = (TYPE_CODE (valtype) == TYPE_CODE_STRUCT ||
+		       TYPE_CODE (valtype) == TYPE_CODE_UNION ||
+		       TYPE_LENGTH (valtype) > 8);
+  
+
+  if (writebuf != NULL)
+    {
+      gdb_assert (!struct_return);
+      arc_store_return_value (valtype, regcache, writebuf);
+    }
+
+  if (readbuf != NULL)
+    {
+      gdb_assert (!struct_return);
+      arc_extract_return_value (valtype, regcache, readbuf);
+    }
+
+  if (struct_return)
+    return RETURN_VALUE_STRUCT_CONVENTION;
+  else
+    return RETURN_VALUE_REGISTER_CONVENTION;
+  //#endif
+}
+
+/* Signal Trampoline Frame Unwinder. These 
+ * unwinders allow frame unwinding to happen 
+ * from within signal handlers. 
+ */
+
+static struct arc_unwind_cache *
+arc_sigtramp_frame_cache (struct frame_info *next_frame,
+			  void **this_cache)
+{
+  // FIXMEA: cleanup#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_sigtramp_frame_cache called");
+#endif
+  //#else
+  struct arc_unwind_cache *cache;
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+  CORE_ADDR addr;
+  char buf[4];
+
+  if (*this_cache)
+    return *this_cache;
+
+  cache = FRAME_OBSTACK_ZALLOC (struct arc_unwind_cache);
+  (*this_cache) = cache;
+  cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
+
+  /* Zero all fields.  */
+  cache->blink_offset = 0;
+  cache->prev_pc = 0;
+  cache->prev_sp = 0;
+  cache->frame_base = 0;
+  cache->framesize = 0;
+  cache->sp_offset = 0;
+  cache->fp_offset = 0;
+  cache->prev_pc = 0;
+  cache->is_leaf = 0;
+  cache->uses_fp = 0;
+
+  
+  frame_unwind_register (next_frame, SP_REGNUM, buf);
+  cache->frame_base = extract_unsigned_integer (buf, 4);
+
+  addr = tdep->sigcontext_addr (next_frame);
+  if (tdep->sc_reg_offset)
+    {
+      int i;
+      
+      for (i = 0; i < tdep->sc_num_regs; i++)
+	if (tdep->sc_reg_offset[i] != -1)
+	  cache->saved_regs[i].addr = addr + tdep->sc_reg_offset[i];
+    }
+
+  return cache;
+  //#endif
+}
+
+static void
+arc_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
+			    struct frame_id *this_id)
+{
+  //FIXMEA: cleanup #ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_sigtramp_frame_this_id called");
+#endif
+  //#else
+  struct arc_unwind_cache *cache = 
+    arc_sigtramp_frame_cache (next_frame, this_cache);
+  
+  (*this_id) = frame_id_build (cache->frame_base, frame_pc_unwind (next_frame));
+  //#endif
+}
+
+static void
+arc_sigtramp_frame_prev_register (struct frame_info *next_frame,
+				  void **this_cache,
+				  int regnum, int *optimizedp,
+				  enum lval_type *lvalp, CORE_ADDR *addrp,
+				  int *realnump, void *valuep)
+{
+  // FIXMEA: cleanup#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_sigtramp_frame_prev_register called");
+#endif
+  //#else
+  struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+
+  /* Make sure we've initialized the cache.  */ 
+  struct arc_unwind_cache *cache = 
+    arc_sigtramp_frame_cache (next_frame, this_cache);
+
+  /* on a signal, the PC is in ret */
+#ifdef ARC4_JTAG
+  if (regnum == ARC_STATUS_REGNUM)
+#else
+  if(regnum == PC_REGNUM)
+#endif
+    regnum = tdep->pc_regnum_in_sigcontext;
+  
+  trad_frame_get_prev_register (next_frame, cache->saved_regs, regnum,
+				optimizedp, lvalp, addrp, realnump, valuep);
+  //#endif
+}
+
+
+static const struct frame_unwind arc_sigtramp_frame_unwind =
+{
+  SIGTRAMP_FRAME,
+  arc_sigtramp_frame_this_id,
+  arc_sigtramp_frame_prev_register
+};
+
+const struct frame_unwind *
+arc_sigtramp_frame_sniffer (struct frame_info *next_frame)
+{
+  //FIXMEA: cleanup#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG  
+  printf ("\narc_sigtramp_frame_sniffer called() ");
+#endif
+  //#else
+  CORE_ADDR pc = frame_pc_unwind (next_frame);
+  struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame));
+
+  /* We shouldn't even bother if we don't have a sigcontext_addr
+     handler.  */
+  if (tdep->sigcontext_addr == NULL)
+    return NULL;
+
+  if (tdep->sigtramp_p != NULL)
+    {
+      if (tdep->sigtramp_p (next_frame))
+	{
+	  return &arc_sigtramp_frame_unwind;
+	}
+    }
+
+  return NULL;
+  //#endif
+}
+
+
+
+/* Allow calls to be made to functions defined in the debuggee. 
+   a.k.a dummy calls 
+*/
+/* When arguments must be pushed onto the stack, they go on in reverse
+   order.  The below implements a FILO (stack) to do this.  
+   Copied from d10v-tdep.c.  */
+
+struct stack_item
+{
+  int len;
+  struct stack_item *prev;
+  void *data;
+};
+
+static struct stack_item *
+push_stack_item (struct stack_item *prev, void *contents, int len)
+{
+  struct stack_item *si;
+  si = xmalloc (sizeof (struct stack_item));
+  si->data = xmalloc (len);
+  si->len = len;
+  si->prev = prev;
+  memcpy (si->data, contents, len);
+  return si;
+}
+
+static struct stack_item *
+pop_stack_item (struct stack_item *si)
+{
+  struct stack_item *dead = si;
+  si = si->prev;
+  xfree (dead->data);
+  xfree (dead);
+  return si;
+}
+
+
+
+
+/* arc_push_dummy_call :
+ *  gdbarch  : gdbarch structure for the backend to use if needed.
+ *  function : 
+ *  regcache : 
+ *  bp_addr  : Return address for the breakpoint.
+ *  sp       : Current value of sp.
+ *  struct_return: struct_return is 1 if structures are returned by 
+ *                 the function.
+ *  struct_addr: Hidden address for returning a struct.
+ */
+
+
+static CORE_ADDR
+arc_push_dummy_call(struct gdbarch *gdbarch, struct value *function,
+		     struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
+		     struct value **args, CORE_ADDR sp, int struct_return,
+		     CORE_ADDR struct_addr)
+
+{
+  //#ifdef ARC4_JTAG
+#ifdef ARC_DEBUG
+  printf ("\narc_push_dummy_call called");
+#endif
+  // #else
+  int stack_alloc;
+  int stack_offset;
+  int argreg;
+  int argnum;
+
+  CORE_ADDR regval;
+  struct stack_item *si = NULL;
+
+
+  /* Push the return address.  */
+#ifdef ARC4_JTAG
+  CORE_ADDR modified_bp_addr;
+  modified_bp_addr = arc_debug_fetch_regs(ARC_STATUS_REGNUM);
+  regcache_raw_collect(regcache, ARC_STATUS_REGNUM, &modified_bp_addr);
+  modified_bp_addr = modified_bp_addr & 0xff000000;
+  bp_addr = bp_addr >>2;
+  modified_bp_addr |= bp_addr;
+  regcache_cooked_write_unsigned (regcache, ARC_BLINK_REGNUM, modified_bp_addr);
+#else
+  regcache_cooked_write_unsigned (regcache, ARC_BLINK_REGNUM, bp_addr);
+#endif
+
+  /* Are we returning a value using a structure return or a normal value
+     return?  struct_addr is the address of the reserved space for the return
+     structure to be written on the stack.
+  */
+  /* FIXME:: Ramana :: What about 4 byte structures returned in r0 as
+     claimed by Metaware. 
+  */
+  
+  /* Now load as many as possible of the first arguments into registers,
+     and push the rest onto the stack.  */
+  argreg = ARC_ARG0_REGNUM;
+ 
+  if (struct_return)
+    {
+      regcache_cooked_write_unsigned (regcache, ARC_ARG0_REGNUM, struct_addr);
+      argreg++;
+#ifdef ARC4_JTAG
+      sp = sp - 16;
+#endif
+    }
+
+  stack_offset = 0;
+
+  for (argnum = 0; argnum < nargs; argnum++)
+    {
+      int len;
+      char *val;
+      int reg_demand;
+      int i;
+      
+      len = TYPE_LENGTH (VALUE_TYPE (args[argnum]));
+      val = (char *) VALUE_CONTENTS (args[argnum]);
+      
+      /* How may registers worth of storage do we need for this argument?  */
+      reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0);
+        
+      if (argreg + reg_demand - 1 <= ARC_ARG7_REGNUM)
+        {
+          /* Data passed by value.  Fits in available register(s).  */
+          for (i = 0; i < reg_demand; i++)
+            {
+              regcache_cooked_write_unsigned (regcache, argreg, 
+					      *(unsigned long *) val);
+              argreg++;
+              val += 4;
+            }
+        }
+      else if (argreg <= ARC_ARG7_REGNUM)
+        {
+          /* Data passed by value. Does not fit in available register(s).
+             Use the register(s) first, then the stack.  */
+          for (i = 0; i < reg_demand; i++)
+            {
+              if (argreg <= ARC_ARG7_REGNUM)
+                {
+		  regcache_cooked_write_unsigned (regcache, argreg, 
+						  *(unsigned long *) val);
+                  argreg++;
+                  val += 4;
+                }
+              else
+                {
+		  /* Push item for later so that pushed arguments
+		     come in the right order.  */
+		  si = push_stack_item (si, val, 4);
+                  val += 4;
+                }
+            }
+        }
+      else if (len > (2 * 4))
+        {
+	  /* FIXME */
+	  internal_error (__FILE__, __LINE__, "We don't do this");
+        }
+      else
+        {
+          /* Data passed by value.  No available registers.  Put it on
+             the stack.  */
+	   si = push_stack_item (si, val, len);
+        }
+    }
+
+  while (si)
+    {
+      /* fp_arg must be word-aligned (i.e., don't += len) to match
+	 the function prologue.  */
+      sp = (sp - si->len) & ~3;
+#ifdef ARC4_JTAG
+      write_memory (sp + 16, si->data, si->len);
+#else
+      write_memory (sp, si->data, si->len);
+#endif
+      si = pop_stack_item (si);
+    }
+
+  /* Finally, update the SP register.  */
+  regcache_cooked_write_unsigned (regcache, ARC_SP_REGNUM, sp);
+
+  return sp;
+  //#endif
+}
+
+/* Align Frame */
+static CORE_ADDR
+arc_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
+{
+  /* Align to the normal alignment on the stack).  */
+  return sp & ~3;
+}
+
+
+/* Print interesting information about the floating point processor
+   (if present) or emulator.  */
+static void
+arc_print_float_info (struct gdbarch *gdbarch, struct ui_file *file,
+		      struct frame_info *frame, const char *args)
+{
+  printf("Software FPU \n");
+}
+
+
+/* Set the main_name to "_main" if required.
+   This is set as an observer of inferior_created.  */
+static void
+arc_set_main_name (struct target_ops *objfile, int from_tty)
+{
+  struct minimal_symbol *umainsym, *mainsym;
+
+  /* Old ARC toolchains prepend an underscore to symbol names.  If there is
+     an _main but no main, then we're probably debugging a binary that was
+     made with the old toolchain.  */
+  umainsym = lookup_minimal_symbol ("_main", NULL, NULL);
+  mainsym = lookup_minimal_symbol ("main", NULL, NULL);
+  if(umainsym && !mainsym)
+    {
+      set_main_name ("_main");
+    }
+
+  /* If we don't have any symbols, the default, i.e. "main", will get used.  */
+}
+
+
+/* The following piece of code is borrowed from d10v */
+static void
+a4_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr)
+{
+#ifdef ARC4_JTAG
+  if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
+      || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD)
+    store_unsigned_integer (buf, TYPE_LENGTH (type), (addr>>2) & 0xffffff);
+  else
+    store_unsigned_integer (buf, TYPE_LENGTH (type), addr);
+#endif
+}
+
+static CORE_ADDR
+a4_pointer_to_address (struct type *type, const void *buf)
+{
+#ifdef ARC4_JTAG  
+  CORE_ADDR addr = extract_unsigned_integer (buf, TYPE_LENGTH(type));
+  /* Is it a code address?  */
+  if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
+      || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
+      || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type)))
+    return ((addr<<2) & 0x2ffffff);
+  else
+    return addr;
+#endif
+}
+
+static struct gdbarch *
+arc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+{
+  struct gdbarch_tdep *tdep;
+  struct gdbarch *gdbarch;
+
+  tdep = xmalloc (sizeof (struct gdbarch_tdep));
+  gdbarch = gdbarch_alloc (&info, tdep);
+  
+  /* Fixme :: Worry about default initialization of breakpoints 
+     for the ARC platform. In our case currently this is handled
+     out of arc-linux-tdep.c for default arc linux breakpoints.
+  */
+
+  info.osabi = CONFIG_OSABI;
+  gdbarch_init_osabi(info, gdbarch);
+  
+  /* Put stuff in gdbarch. */
+
+  /* Characters are unsigned by default */
+  set_gdbarch_char_signed (gdbarch, 0);
+
+  set_gdbarch_print_float_info (gdbarch, arc_print_float_info);
+  set_gdbarch_sp_regnum (gdbarch, ARC_SP_REGNUM);
+  set_gdbarch_register_type (gdbarch, arc_register_type);  
+
+  set_gdbarch_cannot_store_register (gdbarch, arc_cannot_store_register);
+
+
+  /* Advance PC across function entry code.  */
+  set_gdbarch_skip_prologue (gdbarch, arc_skip_prologue);
+
+  
+  /* Hook in the Dwarf-2 frame sniffer.  */
+  set_gdbarch_dwarf2_reg_to_regnum (gdbarch, arc_binutils_reg_to_regnum);
+  dwarf2_frame_set_init_reg (gdbarch, arc_dwarf2_frame_init_reg);
+  frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
+
+  /* signal frames */
+  frame_unwind_append_sniffer (gdbarch, arc_sigtramp_frame_sniffer);
+
+
+
+  /* The stack grows downward.  */
+  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+
+  set_gdbarch_unwind_pc (gdbarch, arc_unwind_pc);
+  set_gdbarch_unwind_sp (gdbarch, arc_unwind_sp);
+  set_gdbarch_unwind_dummy_id (gdbarch, arc_unwind_dummy_id);
+  frame_unwind_append_sniffer (gdbarch, arc_frame_sniffer);
+ 
+
+  set_gdbarch_return_value (gdbarch, arc_return_value);
+
+  /* Add the arc register groups.  */
+  arc_add_reggroups (gdbarch);
+  set_gdbarch_register_reggroup_p (gdbarch, arc_register_reggroup_p);
+  
+  /* Breakpoint manipulation.  */
+  set_gdbarch_breakpoint_from_pc (gdbarch, arc_breakpoint_from_pc);
+  set_gdbarch_frame_align(gdbarch,arc_frame_align);
+
+  /* Dummy Frame handling */
+  set_gdbarch_push_dummy_call (gdbarch, arc_push_dummy_call);
+  set_gdbarch_call_dummy_location (gdbarch,AT_ENTRY_POINT);
+  
+  /* Disassembly.  */
+  {
+    /* the arc libopcodes wants abfd so that it can find out what CPU
+       extensions are there */
+    bfd abfd;
+    abfd.sections = NULL;
+
+
+#ifndef ARC4_JTAG
+    set_gdbarch_print_insn(gdbarch, arcompact_get_disassembler(&abfd));
+#else
+    set_gdbarch_print_insn(gdbarch, arc_get_disassembler(&abfd));
+#endif
+  }
+
+#ifdef ARC4_JTAG  
+  set_gdbarch_address_to_pointer (gdbarch, a4_address_to_pointer);
+  set_gdbarch_pointer_to_address (gdbarch, a4_pointer_to_address);
+#endif
+  //#ifndef ARC4_JTAG
+  /* Set main_name to _main if necessary.  Ideally we'd want a hook that
+     gets called when symbols are loaded, but it seems there isn't one; so
+     we'll use this.  This will not work if the user does "target remote
+     ..." and then "add-symbol-file ..."  */
+  observer_attach_inferior_created (arc_set_main_name);
+  //#endif
+
+#ifdef ARC4_JTAG
+  //  set_gdbarch_write_pc (gdbarch, a4_write_pc);
+#endif
+
+  CONFIG_INIT_TDEP (gdbarch);
+  
+  return gdbarch;
+}
+
+static void
+arc_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
+{
+}
+
+void
+_initialize_arc_tdep (void)
+{
+  gdbarch_register (bfd_arch_arc, arc_gdbarch_init, arc_dump_tdep);
+}
+
diff --git a/gdb/arc-tdep.h b/gdb/arc-tdep.h
new file mode 100644
index 0000000..4251eb4
--- /dev/null
+++ b/gdb/arc-tdep.h
@@ -0,0 +1,109 @@
+/* Target dependent code for ARC700, for GDB, the GNU debugger.
+
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Contributed by Codito Technologies Pvt. Ltd. (www.codito.com)
+
+   Authors: 
+      Soam Vasani <soam.vasani@codito.com>
+      Ramana Radhakrishnan <ramana.radhakrishnan@codito.com> 
+
+   This file is part of GDB.
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+*/
+enum arc700_api_regnums
+  {
+    ARC_ARG0_REGNUM     =        0,
+    ARC_ARG1_REGNUM     =        1,
+    ARC_ARG2_REGNUM     =        2,
+    ARC_ARG3_REGNUM     =        3,
+    ARC_ARG4_REGNUM     =        4,
+    ARC_ARG5_REGNUM     =        5,
+    ARC_ARG6_REGNUM     =        6,
+    ARC_ARG7_REGNUM     =        7,
+
+    /* When a return value is stored in registers, is in either r0 or in
+       (r1,r0).  Used in arc_extract_return_value */
+    ARC_RETURN1_REGNUM	=	 0,
+    ARC_RETURN2_REGNUM 	=	 1
+  };
+
+
+
+enum ARCProcessorVersion
+  {
+    UNSUPPORTED,
+    ARCompact,
+    ARC600,
+    ARC700,
+    A5,
+    A4,
+  };
+
+
+enum ARCExtensionsSupportedInformation
+  {
+    ARC700_MMU
+  };
+
+
+
+typedef struct ARCProcessorInformation
+{
+  enum ARCProcessorVersion arcprocessorversion;
+  enum ARCExtensionsSupportedInformation extensionsSupported;
+
+}ARCVariantsInfo;
+
+struct gdbarch_tdep
+{
+  /* Detect sigtramp.  */
+  int (*sigtramp_p) (struct frame_info *);
+  
+  /* Get address of sigcontext for sigtramp.  */
+  CORE_ADDR (*sigcontext_addr) (struct frame_info *);
+
+  /* Offset of registers in `struct sigcontext'.  */
+  int *sc_reg_offset;
+  int sc_num_regs;
+
+  /* In our linux target, gdbarch_pc_regnum points to stop_pc, which is a
+     register that's made-up by the kernel and does not actually exist.
+     stop_pc is NOT saved in the sigcontext; what is saved is the ret
+     "register".  Since ret is a linux-only register, it's regnum is visible
+     only in arc-linux-tdep.c; hence initialize pc_regnum_in_sigcontext in
+     arc-linux-tdep.c.  */
+  int pc_regnum_in_sigcontext;
+
+  /* Returns false, true, or -1; -1 means the tdep has nothing to say about this
+     register and group.  */
+  int (*register_reggroup_p) (int, struct reggroup *);
+  
+  /* Breakpoint instruction to be used */
+  unsigned char * arc_breakpoint_insn;
+  int arc_breakpoint_size;
+
+  /* For stopping backtraces.  */
+  CORE_ADDR lowest_pc;
+  
+  /* ARC Processor variant information.  */
+  ARCVariantsInfo * arc_processor_variant_info ;
+
+};
+
+
+void arc_software_single_step(enum target_signal ignore, int insert_breakpoints_p);
+
diff --git a/gdb/doc/ChangeLog.codito b/gdb/doc/ChangeLog.codito
new file mode 100644
index 0000000..0a335d9
--- /dev/null
+++ b/gdb/doc/ChangeLog.codito
@@ -0,0 +1,7 @@
+2005-05-16  Soam Vasani  <soam.vasani@codito.com>
+
+	* gdb.texinfo (Embedded Processors): Add a menu item for ARC and
+	include arc.texi.
+	* arc.texi: New file.  ARC specific commands etc.
+	* Makefile.in (GDB_DOC_SOURCE_INCLUDES): Add arc.texi to the list.
+
diff --git a/gdb/doc/arc.texi b/gdb/doc/arc.texi
new file mode 100644
index 0000000..9a00571
--- /dev/null
+++ b/gdb/doc/arc.texi
@@ -0,0 +1,155 @@
+@c \input texinfo
+@c %**start of header
+@c @setfilename arc-cmds.info
+@c @settitle ARC specific commands
+@c @setchapternewpage off
+@c %**end of header
+
+@node ARC
+@subsection ARC
+
+GDB for ARC supports the ARC600 and ARC700 cores.
+
+On ARC700, you can debug linux applications using gdbserver.  On
+ARC700 and ARC600, you can debug any program using the arcjtag target.
+
+
+@menu
+* ARC specific commands::        ARC specific commands
+@end menu
+
+@node ARC specific commands, , , ARC
+@subsection ARC specific commands
+
+These commands can only be used when GDB has been build for ARC.
+
+
+@menu
+* target arcjtag::                  Use the JTAG target
+* arc-reset-board::                 Reset the ARC board
+* arc-aux-read::                    Read a range of auxillary registers
+* arc-aux-write::                   Write an auxillary register
+* info arc-bcr-registers::          Show build configuration registers
+
+Debugging:
+* set arcjtag-debug-statemachine::  JTAG state machine debugging messages
+* set arcjtag-debug-target::        arcjtag target debugging messages
+@end menu
+
+@node target arcjtag
+@subsubsection target arcjtag
+
+Usage: @code{target arcjtag}
+
+Connect to the arcjtag target.
+
+This target expects the ARC board to be connected to the parallel port
+on the host.  Currently we support debugging only on GNU/Linux hosts.
+
+This target uses the gpio device to access the parallel.  You must
+have the gpio driver installed and you must have read/write privileges
+to /dev/gpio.
+
+
+@node arc-reset-board
+@subsubsection arc-reset-board
+
+Usage: @code{arc-reset-board}
+
+Reset the board.
+
+For this command to work, you must be connected to the arcjtag target,
+by using the command @code{target arcjtag}.
+
+
+@node arc-aux-read
+@subsubsection arc-aux-read
+
+Usage: @code{arc-aux-read <REG-FROM> [<REG-TO>]}
+
+Read and show a range of auxillary registers.
+REG-FROM and REG-TO can be any expressions that evaluate to integers.
+REG-TO is optional; if it is not specified, only one register is displayed.
+
+For example:
+@example
+(gdb) arc-aux-read 0x400 0x406
+00000400: 00000100 80001abc 00001620 00200000
+00000404: 00000100 00000000 00000000
+@end example
+
+For this command to work, you must be connected to the arcjtag target,
+by using the command @code{target arcjtag}.
+
+
+
+@node arc-aux-write
+@subsubsection arc-aux-write
+
+Usage: @code{arc-aux-write <REG> = <VALUE>}
+
+Write to an auxillary register.
+REG and VALUE can be any expressions that evaluate to integers.
+
+For example:
+@example
+(gdb) arc-aux-write 6 = 0x123
+@end example
+
+For this command to work, you must be connected to the arcjtag target,
+by using the command @code{target arcjtag}.
+
+@node info arc-bcr-registers
+@subsubsection info arc-bcr-registers
+
+Usage: @code{info arc-bcr-registers}
+
+Show all the build configuration registers.
+
+For example:
+@example
+(gdb) info arc-bcr-registers
+[61] DCCM_BASE_BUILD : 0x1010121
+[62] CRC_BASE_BUILD  : 0x00
+[63] BTA_LINK_BUILD  : 0x1010121
+[64] DVBF_BUILD      : 0x00
+[65] TEL_INSTR_BUILD : 0x00
+[67] MEMSUBSYS       : 0x01
+[68] VECBASE_AC_BUILD : 0x01
+[69] P_BASE_ADDRESS  : 0xfc0001
+[6f] MMU_BUILD       : 0x1010121
+[70] ARCANGEL_BUILD  : 0x1010121
+[72] D_CACHE_BUILD   : 0x12001
+[73] MADI_BUILD      : 0x00
+[74] DCCM_BUILD      : 0x00
+[75] TIMER_BUILD     : 0x303
+[76] AP_BUILD        : 0x00
+[77] ICACHE_BUILD    : 0x22001
+[78] ICCM_BUILD      : 0x1010121
+[79] DSPRAM_BUILD    : 0x1203
+[7a] MAC_BUILD       : 0x00
+[7b] MULTIPLY_BUILD  : 0x01
+[7c] SWAP_BUILD      : 0x01
+[7d] NORM_BUILD      : 0x02
+[7e] MINMAX_BUILD    : 0x00
+[7f] BARREL_BUILD    : 0x02
+@end example
+
+For this command to work, you must be connected to the arcjtag target,
+by using the command @code{target arcjtag}.
+
+@node set arcjtag-debug-statemachine
+@subsubsection set arcjtag-debug-statemachine
+
+Usage: @code{set arcjtag-debug-statemachine ARG}
+
+Switch on JTAG state machine debugging messages if ARG is non-zero.
+Switch them off if it is zero.
+
+@node set arcjtag-debug-target
+@subsubsection set arcjtag-debug-target
+
+Usage: @code{set arcjtag-debug-target ARG}
+
+Switch on JTAG target debugging messages if ARG is non-zero.
+Switch them off if it is zero.
diff --git a/gdb/gdbserver/ChangeLog.codito b/gdb/gdbserver/ChangeLog.codito
new file mode 100644
index 0000000..e36df7c
--- /dev/null
+++ b/gdb/gdbserver/ChangeLog.codito
@@ -0,0 +1,34 @@
+2005-05-14  Soam Vasani  <soam.vasani@codito.com>
+
+	* proc-service.c (ps_pglobal_lookup): First look for NAME, then
+	for NAME with an underscore prepended.  The toolchain no longer
+	prepends underscores, but we should still work with older
+	toolchains.
+
+2005-05-14  Soam Vasani  <soam.vasani@codito.com>
+
+	* linux-arc-low.c (arg_regmap): Offsets were wrong, correct them.
+
+2005-05-14  Soam Vasani  <soam.vasani@codito.com>
+
+	* linux-arc-low.c: Remove #include reg.h.  Include linux/user.h to
+	get offsets of registers in the struct ptrace.
+
+2005-04-11  Soam Vasani  <soam.vasani@codito.com>
+
+	* linux-arc-low.c (arc_get_pc): Return stop_pc, not EFA.
+
+2005-04-09  Soam Vasani  <soam.vasani@codito.com>
+
+	* proc-service.c (ps_pglobal_lookup): Prepend underscore to symbol
+	names, because the toolchain does that.  Remove this hack when we
+	change the toolchain.
+	* linux-arc-low.c (arc_get_pc): Return EFA's value instead of RET,
+	so that gdbserver can do it's own breakpoints correctly.
+	(arc_reinsert_addr): Return blink's value.
+
+2005-04-07  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* configure.srv: Change arc-*-elf* to arc-linux .Include 
+	thread debugging for the ARC platform. 
+
diff --git a/gdb/gdbserver/linux-arc-low.c b/gdb/gdbserver/linux-arc-low.c
new file mode 100644
index 0000000..28c7ead
--- /dev/null
+++ b/gdb/gdbserver/linux-arc-low.c
@@ -0,0 +1,149 @@
+/* GNU/Linux/ARC specific low level interface, for the remote server for GDB.
+   Copyright 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004
+   Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#include "server.h"
+#include "linux-low.h"
+
+#include <linux/user.h>
+
+#define OFFSET(member,structure) (int)(&( ((struct structure *)0)->member ))
+
+#define arc_num_regs 39
+
+/* arc_regmap[i] is the offset of Ri in Linux's user struct */
+static int arc_regmap[] = {
+    OFFSET(r0, user_regs_struct),
+    OFFSET(r1, user_regs_struct),
+    OFFSET(r2, user_regs_struct),
+    OFFSET(r3, user_regs_struct),
+    OFFSET(r4, user_regs_struct),
+    OFFSET(r5, user_regs_struct),
+    OFFSET(r6, user_regs_struct),
+    OFFSET(r7, user_regs_struct),
+    OFFSET(r8, user_regs_struct),
+    OFFSET(r9, user_regs_struct),
+    OFFSET(r10, user_regs_struct),
+    OFFSET(r11, user_regs_struct),
+    OFFSET(r12, user_regs_struct),
+    OFFSET(r13, user_regs_struct),
+    OFFSET(r14, user_regs_struct),
+    OFFSET(r15, user_regs_struct),
+    OFFSET(r16, user_regs_struct),
+    OFFSET(r17, user_regs_struct),
+    OFFSET(r18, user_regs_struct),
+    OFFSET(r19, user_regs_struct),
+    OFFSET(r20, user_regs_struct),
+    OFFSET(r21, user_regs_struct),
+    OFFSET(r22, user_regs_struct),
+    OFFSET(r23, user_regs_struct),
+    OFFSET(r24, user_regs_struct),
+    OFFSET(r25, user_regs_struct),
+    OFFSET(r26, user_regs_struct),
+    OFFSET(bta, user_regs_struct),
+    OFFSET(lp_start, user_regs_struct),
+    OFFSET(lp_end, user_regs_struct),
+    OFFSET(lp_count, user_regs_struct),
+    OFFSET(status32, user_regs_struct),
+    OFFSET(blink, user_regs_struct),
+    OFFSET(fp, user_regs_struct),
+    OFFSET(sp, user_regs_struct),
+    OFFSET(efa, user_regs_struct),
+    OFFSET(ret, user_regs_struct),
+    OFFSET(orig_r8, user_regs_struct),
+    OFFSET(stop_pc, user_regs_struct)
+};
+
+static int
+arc_cannot_store_register (int regno)
+{
+  return (regno == 35 || regno >= arc_num_regs); /* FIXME, this is dirty */
+}
+
+static int
+arc_cannot_fetch_register (int regno)
+{
+  return (regno >= arc_num_regs);
+}
+
+extern int debug_threads;
+
+static CORE_ADDR
+arc_get_pc ()
+{
+  unsigned long pc;
+  collect_register_by_name ("stop_pc", &pc);
+  if (debug_threads)
+    fprintf (stderr, "stop pc is %08lx\n", pc);
+  return pc;
+}
+
+static void
+arc_set_pc (CORE_ADDR pc)
+{
+  unsigned long newpc = pc;
+  supply_register_by_name ("ret", &newpc);
+}
+
+
+/* trap_s 1 */
+/* FIXME: dependent on target endianness */
+static const unsigned long arc_breakpoint = 0x783E;
+#define arc_breakpoint_len 2
+
+static int
+arc_breakpoint_at (CORE_ADDR where)
+{
+  unsigned long insn;
+
+  (*the_target->read_memory) (where, (char *) &insn, arc_breakpoint_len);
+  if (insn == arc_breakpoint)
+    return 1;
+
+  /* If necessary, recognize more trap instructions here.  GDB only uses the
+     one.  */
+  return 0;
+}
+
+
+/* We only place breakpoints in empty marker functions, and thread locking
+   is outside of the function.  So rather than importing software single-step,
+   we can just run until exit.  */
+static CORE_ADDR
+arc_reinsert_addr ()
+{
+  unsigned long pc;
+  collect_register_by_name ("blink", &pc);
+  return pc;
+}
+
+struct linux_target_ops the_low_target = {
+  arc_num_regs,
+  arc_regmap,
+  arc_cannot_fetch_register,
+  arc_cannot_store_register,
+  arc_get_pc,
+  arc_set_pc,
+  (const char *) &arc_breakpoint,
+  arc_breakpoint_len,
+  arc_reinsert_addr,
+  0,
+  arc_breakpoint_at,
+};
diff --git a/gdb/gpio.h b/gdb/gpio.h
new file mode 100644
index 0000000..86aa4ca
--- /dev/null
+++ b/gdb/gpio.h
@@ -0,0 +1,38 @@
+struct GPIO_ioctl {
+    // This is used for general input and output in the same ioctl.
+    // inlen is replaced by the number of input bytes consumed.
+    // inlen is always even and represents a number of pairs:
+    //	[0/1/2,value]: write value to port_base+0/1/2.
+    //	[0x80/0x81/0x82, --]: read value from port_base+0/1/2
+    //	and append result to outbuf.
+    // Thus one can intermix read and write in the same ioctl.
+    unsigned inlen; char *inbuf;
+    // outlen is replaced by # of output bytes written.
+    unsigned outlen; char *outbuf;
+    };
+
+// IO control numbers
+
+// Linux kernel uses 0x54XX for special purposes.  Avoid such.
+// We'll pick large numbers.
+// We don't use the linux convention of dividing the IOC into a bunch
+// of bit fields.  We can always switch to this later, as the
+// IOC 0 returns the driver version (which IOC value will never change).
+
+#define GPIO_IOC_VERSION 0	// returns version
+#define GPIO_IOC_BASE 0xaa3a0000	// Intended for use on ARCangel 3!
+
+// Switch base address of parallel port.  0x3f8 is assumed.
+// WARNING!  You can write on any port whatsoever with this driver.
+// BE CAREFUL!
+#define GPIO_IOC_SET_PORT_BASE 	(GPIO_IOC_BASE+1) // cmd, arg=port base
+
+// General input/output ioctl.  See GPIO_ioctl struct.
+#define GPIO_IOC_DO_IO  	(GPIO_IOC_BASE+2) // cmd, arg=GPIO_ioctl *
+
+// For emergency purposes in case the driver is goofed up.
+#define GPIO_IOC_HARDRESET 	(GPIO_IOC_BASE+3) // cmd, no arg
+
+// Do you have an antiquated parallel port?  You might need to ask
+// the driver to use outb_p and inb_p (_p = pause).  Default is not to.
+#define GPIO_IOC_SET_PAUSE 	(GPIO_IOC_BASE+4) // arg = 1 => use pause; o/wise not.
diff --git a/gdb/regformats/reg-arc.dat b/gdb/regformats/reg-arc.dat
new file mode 100644
index 0000000..74f3b06
--- /dev/null
+++ b/gdb/regformats/reg-arc.dat
@@ -0,0 +1,41 @@
+name:arc
+expedite:fp,sp,ret
+32:r0
+32:r1
+32:r2
+32:r3
+32:r4
+32:r5
+32:r6
+32:r7
+32:r8
+32:r9
+32:r10
+32:r11
+32:r12
+32:r13
+32:r14
+32:r15
+32:r16
+32:r17
+32:r18
+32:r19
+32:r20
+32:r21
+32:r22
+32:r23
+32:r24
+32:r25
+32:r26
+32:bta
+32:lp_start
+32:lp_end
+32:lp_count
+32:status32
+32:blink
+32:fp
+32:sp
+32:efa
+32:ret
+32:orig_r8
+32:stop_pc
diff --git a/gdb/testsuite/ChangeLog.codito b/gdb/testsuite/ChangeLog.codito
new file mode 100644
index 0000000..87e1277
--- /dev/null
+++ b/gdb/testsuite/ChangeLog.codito
@@ -0,0 +1,151 @@
+2005-11-08  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* arcgdbserverusinggdbserver.exp: Is a duplicate of
+	lib/arc-gdbserver.exp. Remove it.
+	* lib/arc-jtag.exp: Remove hardcoded compiler, assembler, etc. Use
+	environment variables instead.
+	* lib/arc-gdbserver.exp: Ditto. Disallow fileio tests. Use default
+	timeout. 
+	* config/remote-gdbserver.exp (rsh_gdbserver_spawn): Expect output
+	from the spawned rsh program. Check for errors. Return -1 on
+	error.
+	(gdbserver_spawn): Return spawn_id.
+	(gdb_load): Check the returned spawn_id from gdbserver_spawn and
+	return -1 on error. Remove sleep and expect output from the
+	spawned process instead. Do a wait on the spawned process after it
+	finishes.
+	* lib/mi-support.exp (gdb_load): Ditto.
+
+2005-10-31  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* gdb.asm/asm-source.exp: Add linker flag -marclinux for target arc.
+
+2005-10-24  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* gdb.asm/asm-source.exp: Set debug-flags to -gdwarf-2 for target arc.
+
+2005-10-21  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* gdb.asm/arc.inc: Define macro's declare and end.
+
+2005-10-18  Kunal Parmar  <kunal.parmar@codito.com>
+
+	Bug #1183
+	* lib/mi-support.exp (mi_gdb_load): Add support for target
+	remote. Fix for Bug #1183 (Testsuite does not complete for
+	gdb.mi).
+
+2005-10-14  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* config/remote-gdbserver.exp (gdb_load): Check the return value
+	from gdb_target_cmd. Retry on failure.
+
+2005-09-28  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* lib/arc-jtag.exp: Skip the huge.exp test.
+
+2005-09-28  Kunal Parmar  <kunal.parmar@codito.com>
+
+	Bug #1183
+	* lib/mi-support.exp (mi_gdb_load): Add support for target
+	arcjtag. Fix for Bug #1183 (Testsuite does not complete for
+	gdb.mi).
+
+2005-09-23  Kunal Parmar  <kunal.parmar@codito.com>
+
+	* config/arc-jtag.exp: Take care about timeouts. Kill previous
+	program being debugged after doing arc-reset-board.
+	* lib/arc-jtag.exp: Add board_info to disallow unsupported tests.
+	Add board_info for arcjtag as gdb_protocol.
+
+2005-05-20  Soam Vasani  <soam.vasani@codito.com>
+
+	* gdb.arch/arc-step-jtag.s: Define "main" label.
+	* gdb.arch/arc-step.s: Ditto.
+
+2005-05-15  Soam Vasani  <soam.vasani@codito.com>
+
+	* gdb.arch/arc-step-jtag.exp: Check gdb_load's return value.
+
+2005-05-15  Soam Vasani  <soam.vasani@codito.com>
+
+	* config/arc-jtag.exp (gdb_target_arcjtag): Increase timeout.
+	Kill previous program being debugged.  Return zero on success,
+	non-zero otherwise.
+	(gdb_load): Check return value of gdb_target_arcjtag.  Return zero
+	on success, non-zero otherwise.
+
+2005-05-14  Soam Vasani  <soam.vasani@codito.com>
+
+	* gdb.arch/arc-step-jtag.exp: Oops.  Use arc-step-jtag.s, not
+	arc-step.s.
+
+2005-05-14  Soam Vasani  <soam.vasani@codito.com>
+
+	* gdb.arch/arc-step-jtag.exp: New file for the JTAG target.
+	* arc-step-jtag.s: New file, derived from arc-step.s: added labels
+	in delay slots and ended using "flag 1"
+	(JTAG uses hardware single step which can step thru delay slots,
+	unlike software single step.)
+	* gdb.arch/arc-step.exp: Quit if not on linux.
+
+2005-05-14  Soam Vasani  <soam.vasani@codito.com>
+
+	* config/arc-jtag.exp (gdb_target_arcjtag): If target arcjtag
+	fails, once do arc-reset-board and try again.
+
+2005-05-12  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* lib/gdbserver.exp: Use a special tests dir for specifying
+	the tests directory where the tests have been downloaded. 
+	* arcgdbserverusinggdbserver.exp: Use this to run the testsuite. 
+
+2005-05-04  Soam Vasani  <soam.vasani@codito.com>
+
+	* config/arc-jtag.exp: Target-specific file for the arcjtag target.
+	* lib/arc-jtag.exp: Baseboard file for arcjtag target.  (No real
+	reason to put it in this directory, but...)
+
+2005-04-13  Soam Vasani  <soam.vasani@codito.com>
+
+	* gdb.arch/arc-step.exp: Tests for software single step across
+	32 bit / 16bit instructions, branches with/without delay slots,
+	and zero-overhead-loops.
+	* gdb.arch/arc-step.s: Ditto.
+
+2005-04-11  Soam Vasani  <soam.vasani@codito.com>
+
+	* gdb.threads/thread_check.exp: Applied
+	  http://sources.redhat.com/ml/gdb-patches/2004-11/msg00458.html,
+	  which corrects the filename and the regexp.
+
+2005-04-08  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* gdb.base/float.exp: Add support for the ARC platform. 
+
+2005-03-30  Soam Vasani  <soam.vasani@codito.com>
+
+	* config/remote-gdbserver.exp (rsh_gdbserver_spawn): Find RSH.
+	* lib/arc-gdbserver.exp: Use rsh instead of telnet.
+
+2005-03-21  Soam Vasani  <soam.vasani@codito.com>
+
+	* config/remote-gdbserver.exp (mynewtelnet_open_and_exec): Assume
+	that telnet-exec.exp is in the path; do not hardcode the path.
+	* lib/arc-gdbserver.exp: Remove hardcoded paths, port numbers,
+	etc.  Use environment variables instead.
+
+2005-03-15  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* config/remote-gdbserver.exp: New file for nfs copying
+	* gdb.asm/arc.inc: New file for assembly language testing
+	* gdb.asm/asm-source.exp: Handle the arc architecture. 
+	* lib/telnet-exec.exp: A replacement for rsh using telnet to allow
+	  executing commands on the arc board. Used while testing
+	  gdbserver on ARC700. 
+	* lib/arc-gdbserver.exp: A setup for running the testsuite
+	  using arc-gdbserver. Should be a part of the dejagnu
+	  distribution but is kept here for convinience. Tailor this 
+	  for use. (Store usually in /usr/share/dejagnu/baseboards directory)
+	
+
diff --git a/gdb/testsuite/config/arc-jtag.exp b/gdb/testsuite/config/arc-jtag.exp
new file mode 100644
index 0000000..1689111
--- /dev/null
+++ b/gdb/testsuite/config/arc-jtag.exp
@@ -0,0 +1,112 @@
+# Test Framework Driver for GDB using the arcjtag target.
+
+#   Copyright 2005 Free Software Foundation, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+
+load_lib gdb.exp
+
+#
+# gdb_target_arcjtag
+# Set gdb to target arcjtag.
+#
+proc gdb_target_arcjtag { } {
+    global gdb_prompt
+    global exit_status
+
+    # our arcjtag target doesn't take any options (yet)
+    #set target_arcjtag_options "[board_info target gdb,target_sim_options]";
+
+    send_gdb "target arcjtag\n"
+
+    gdb_expect 60 {
+        -re "A program is being debugged already.*Kill it.*y or n. $" {
+            send_gdb "y\n"
+	    verbose "\t\tKilling previous program being debugged"
+            exp_continue
+        }
+	-re "Connected to the arcjtag target.*$gdb_prompt $"	{
+	    verbose "Set target to arcjtag"
+	}
+	-re "$gdb_prompt $" {
+	    verbose "Retrying target arcjtag..."
+	    send_gdb "arc-reset-board\n"
+	    send_gdb "target arcjtag\n"
+
+	    gdb_expect 60 {
+		-re "A program is being debugged already.*Kill it.*y or n. $" {
+		    send_gdb "y\n"
+		    verbose "\t\tKilling previous program being debugged"
+		    exp_continue
+		}
+		-re "Connected to the arcjtag target.*$gdb_prompt $"	{
+		    verbose "Set target to arcjtag"
+		}
+		timeout { 
+		    perror "Couldn't set target to arcjtag (timeout)."
+		    return 1
+		}
+	    }
+	}
+	timeout { 
+	    perror "Couldn't set target to arcjtag (timeout)."
+	    return 1
+	}
+    }
+
+    return 0
+}
+
+#
+# gdb_load -- load a file into the debugger.
+#             return a -1 if anything goes wrong.
+#
+proc gdb_load { arg } {
+    global verbose
+    global loadpath
+    global loadfile
+    global GDB
+    global gdb_prompt
+
+    if { $arg != "" } {
+	if [gdb_file_cmd $arg] then { return -1 }
+    }
+    
+    if { [gdb_target_arcjtag] != 0 } {
+	return -1
+    }
+
+    # gotta do something about the timeout....
+    send_gdb "load\n"
+
+    gdb_expect 180 {
+	-re ".*$gdb_prompt $" {
+	    if $verbose>1 then {
+		send_user "Loaded $arg into $GDB\n"
+	    }
+	    return 0
+	}
+	-re "$gdb_prompt $" {
+	    if $verbose>1 then {
+		perror "GDB couldn't load."
+	    }
+	}
+	timeout {
+	    perror "Timed out trying to load $arg."
+	}
+    }
+
+    return 1
+}
diff --git a/gdb/testsuite/config/remote-gdbserver.exp b/gdb/testsuite/config/remote-gdbserver.exp
new file mode 100644
index 0000000..60d106d
--- /dev/null
+++ b/gdb/testsuite/config/remote-gdbserver.exp
@@ -0,0 +1,570 @@
+# Test framework for GDB (remote protocol) using a "gdbserver",
+# ie. a debug agent running as a native process on the same or
+# a different host.
+
+# Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# bug-gdb@prep.ai.mit.edu
+
+# This file was written by Michael Snyder. (msnyder@redhat.com)
+
+#
+# This module to be used for testing gdb with a "gdbserver" 
+# built either from libremote or from gdb/gdbserver.
+#
+
+# Load the basic testing library, and the remote stuff.
+load_lib ../config/monitor.exp
+load_lib telnet.exp
+#
+# To be addressed or set in your baseboard config file:
+#
+#   set_board_info gdb_protocol "remote"
+#	Unles you have a gdbserver that uses a different protocol...
+#
+#   set_board_info use_gdb_stub 1
+#	This tells the rest of the test suite not to do things
+#	like "run" which don't work well on remote targets.
+#
+#   set_board_info gdb,do_reload_on_run 1
+#	Unles you have a gdbserver that can handle multiple sessions.
+#
+#   set_board_info noargs 1
+#	At present there is no provision in the remote protocol
+#	for passing arguments.  This test framework does not
+#	address the issue, so it's best to set this variable
+#	in your baseboard configuration file.  
+#	FIXME: there's no reason why the test harness couldn't
+#	pass commandline args when it spawns gdbserver.
+#
+#   set_board_info gdb,noinferiorio 1
+#	Neither the traditional gdbserver nor the one in libremote
+#	can presently capture stdout and relay it to GDB via the
+#	'O' packet.  This means that tests involving printf will
+#	fail unles you set this varibale in your baseboard
+#	configuration file.
+#   
+#   set_board_info gdb,no_hardware_watchpoints 1
+#	Unles you have a gdbserver that supports hardware watchpoints.
+#	FIXME: gdb should detect if the target doesn't support them,
+#	and fall back to using software watchpoints.
+#
+#   set_board_info gdb_server_prog
+#	This will be the path to the gdbserver program you want to test.
+#	Defaults to "gdbserver".
+#
+#   set_board_info sockethost
+#	The name of the host computer whose socket is being used.
+#	Defaults to "localhost".  Note: old gdbserver requires 
+#	that you define this, but libremote/gdbserver does not.
+#
+#   set_board_info socketport
+#	Port id to use for socket connection.  If not set explicitly,
+#	it will start at "2345" and increment for each use.
+#
+#   set_board_info rsh_prog
+#	The program to use to spawn executables on the remote board.
+#	Default: "rsh"
+#
+#   set_board_info rcp_prog
+#	The program to use to copy test executables to the remote board.
+#	Default: "rcp"
+#
+#   set_board_info nfsdir
+#	If rcp_prog is set to "cp", specify the local directory name that
+#	is NFS mounted by the board.
+
+#
+# gdb_load -- load a file into the debugger.
+#             return a -1 if anything goes wrong.
+#
+
+global server_exec;
+global portnum;
+set portnum "2000";
+
+proc gdb_load { args } {
+    global server_exec;
+    global portnum;
+    global verbose;
+    global gdb_prompt;
+
+    # Port id -- either specified in baseboard file, or managed here.
+    if [target_info exists gdb,socketport] {
+	set portnum [target_info gdb,socketport];
+    } else {
+	# Bump the port number to avoid conflicts with hung ports.
+	incr portnum;
+    }
+
+    # Extract the local and remote host ids from the target board struct.
+
+    if [target_info exists sockethost] {
+	set debughost  [target_info sockethost];
+    } else {
+	set debughost "localhost:";
+    }
+    # Extract the protocol
+    if [target_info exists gdb_protocol] {
+	set protocol [target_info gdb_protocol];
+    } else {
+	set protocol "remote";
+    }
+
+    # Extract the name of the gdbserver, if known (default 'gdbserver').
+    if [target_info exists gdb_server_prog] {
+	set gdbserver [target_info gdb_server_prog];
+    } else {
+	set gdbserver "gdbserver";
+    }
+    # Extract the socket hostname
+    if [target_info exists sockethost] {
+	set sockethost [target_info sockethost];
+    } else {
+	set sockethost ""
+    }
+
+    # Get target name
+    if [target_info exists hostname] {
+	set target_address [target_info hostname];
+    } else {
+	set target_address "localhost"
+    }
+
+    # Get the username on the target
+    if [target_info exists "username"] {
+	set username [target_info username];
+    } else {
+	set username "";
+    }
+
+    # Get download dir
+    if [target_info exists download_dir] {
+	set download_dir [target_info download_dir];
+    } else {
+	set download_dir "/tmp"
+    }
+
+    # Get tests dir
+    if [target_info exists tests_dir] {
+	set tests_dir [target_info tests_dir];
+    } else {
+	set tests_dir $download_dir
+    }
+
+    # Export the host:port pair.
+    set gdbport $debughost$portnum;
+
+    if { $args == "" || $args == "{}" } {
+	if [info exists server_exec] {
+	    set args $server_exec;
+	} else {
+	    send_gdb "info files\n";
+	    gdb_expect 30 {
+		-re "Symbols from \"(\[^\"\]+)\"" {
+		    set args $expect_out(1,string);
+		    exp_continue;
+		}
+		-re "Local exec file:\[\r\n\]+\[ \t\]*`(\[^'\]+)'," {
+		    set args $expect_out(1,string);
+		    exp_continue;
+		}
+		-re "$gdb_prompt $" { }
+	    }
+	}
+    }
+
+    # remember new exec file 
+    set server_exec $args;
+
+    # Download the test files into the test_board
+    gdbserver_download $target_address $username $server_exec \
+	$download_dir/a-$portnum.out
+
+    # tell gdb what file we are debugging
+    if [gdb_file_cmd $args] {
+	return -1;
+    }
+
+    if [target_info exists solib_path] {
+	send_gdb "set solib-absolute-prefix [target_info solib_path]\n"
+	gdb_expect 30 {
+	    -re "$gdb_prompt $" {
+		if $verbose>1 then {
+		    send_user "set library path\n"
+		}
+	    }
+	    default { 
+		perror "Couldn't set library path\n"
+		return -1
+	    }
+	}
+    }
+
+    for {set i 1} {$i <= 3} {incr i} {
+	# Fire off the debug agent
+	set server_spawn_id [gdbserver_spawn $target_address $username \
+				 "$gdbserver $target_address:$portnum $tests_dir/a-$portnum.out 2>&1"]
+	
+	if { $server_spawn_id <= 0 } { return -1 }
+
+	# Wait for the server to produce at least one line and an additional
+	# character of output.  This will wait until any TCP socket has been
+	# created, so that GDB can connect.
+	expect {
+	    # expect output from $server_spawn_id
+	    -i $server_spawn_id
+	    -re ".*\n." { }
+	}
+    
+	# We can't just call close, because if gdbserver is local then that means
+	# that it will get a SIGHUP.  Doing it this way could also allow us to
+	# get at the inferior's input or output if necessary, and means that we
+	# don't need to redirect output.
+	expect_background {
+	   -i $server_spawn_id
+	   -re "." { }
+	   eof {
+	       # The spawn ID is already closed now (but not yet waited for).
+	       wait -nowait -i $expect_out(spawn_id)
+	   }
+	}
+	
+	# attach to the "serial port"
+	if {[gdb_target_cmd $protocol $gdbport] == 0 } {
+	    break
+	}
+	verbose -log "Unable to connect to target. Re-trying.."
+    }	
+
+    # do the real load if needed
+    if [target_info exists gdb_server_do_load] {
+        send_gdb "load\n"
+        set timeout 2400
+        verbose "Timeout is now $timeout seconds" 2
+        gdb_expect {
+            -re ".*$gdb_prompt $" {
+                if $verbose>1 then {
+                    send_user "Loaded $arg into $GDB\n"
+                }
+                set timeout 30
+                verbose "Timeout is now $timeout seconds" 2
+                return 1
+            }
+            -re "$gdb_prompt $"     {
+                if $verbose>1 then {
+                    perror "GDB couldn't load."
+                }
+            }
+            timeout {
+                if $verbose>1 then {
+                    perror "Timed out trying to load $arg."
+                }
+            }
+        }
+    }
+
+    return 0;
+}
+
+
+# Use RSH or telnet depending on the program chosen
+# by the board file. 
+# Return spawn_id
+proc gdbserver_spawn { dest username commandline } {
+    global board_info 
+    if ![target_info exists rsh_prog] {
+        if { [which remsh] != 0 } {
+            set RSH remsh
+        } else {
+            set RSH rsh
+        }
+    } else {
+        set RSH [target_info rsh_prog];
+    }
+
+    if { $RSH == "rsh" } {
+	return [rsh_gdbserver_spawn $dest $username $commandline]
+    } else {
+
+	if { $RSH == "telnet" } {
+	    # Spawn the shell
+	    return [telnet_gdbserver_spawn $dest $username $commandline]
+	    
+	    # expect the shell prompt obtained from 
+	    # the board description.
+	    # Now spawn gdbserver with its parameters
+	    # and dont expect any output from the gdbserver
+	    # other than the shell prompt
+	    # FIXME ?? Where do I close the telnet
+	    # session ( could use gdb_finish for closing the telnet session)
+
+	    
+
+	} else {
+	    verbose "Unknown rsh program "
+	    return -1
+	}
+    }
+}
+
+proc mynewtelnet_open_and_exec {  dest port shell_prompt commandline } {
+    global board_info
+    
+    spawn "telnet-exec.exp" $dest $commandline
+    set board_info($dest,fileid) $spawn_id;
+    return $spawn_id;
+}
+
+
+proc mytelnet_open_and_exec {  dest port shell_prompt commandline } {
+    set tries 0
+    set result -1
+    set need_respawn 1
+    
+    verbose "Starting a telnet connection to $dest:$port $shell_prompt " 2
+    while { $result < 0 && $tries <= 3 } {
+	if { $need_respawn } {
+	    set need_respawn 0
+	    spawn "telnet" $dest $port
+	}
+	expect {
+	    "Trying " {
+		exp_continue
+	    }
+	    -re "$shell_prompt.*$" {
+		verbose "Got prompt $shell_prompt\n"
+		set result 0
+		exp_send $commandline
+	   
+	    }
+	    -re "nt Name:|ogin:" {
+		if [board_info $connhost exists telnet_username] {
+		    exp_send "[board_info $connhost telnet_username]\n"
+		    exp_continue
+		}
+		if [board_info $connhost exists username] {
+		    exp_send "[board_info $connhost username]\n"
+		    exp_continue
+		}
+		perror "telnet: need to login"
+		break
+	    }
+	    "assword:" {
+		if [board_info $connhost exists telnet_password] {
+		    exp_send "[board_info $connhost telnet_password]\n"
+		    exp_continue
+		}
+		if [board_info $connhost exists password] {
+		    exp_send "[board_info $connhost password]\n"
+		    exp_continue
+		}
+		perror "telnet: need a password"
+		break
+	    }
+	    -re "advance.*y/n.*\\?" {
+		exp_send "n\n"
+		exp_continue
+	    }
+	    -re {([Aa]dvanced|[Ss]imple) or ([Ss]imple|[Aa]dvanced)} {
+		exp_send "simple\n"
+		exp_continue
+	    }
+	    "Connected to" {
+		exp_continue
+	    }
+	    "unknown host" {
+		exp_send "\003"
+		perror "telnet: unknown host"
+		break
+	    }
+	    "VxWorks Boot" {
+		exp_send "@\n"
+		sleep 20
+		exp_continue
+	    }
+	    -re "Escape character is.*\\.\[\r\n\]" {
+		    exp_continue
+	    }
+	    "has logged on from" {
+		exp_continue
+	    }
+	    "You have no Kerberos tickets" {
+		warning "telnet: no kerberos Tickets, please kinit"
+		break
+	    }
+	    -re "Connection refused.*$" {
+		catch "exp_send \"\003\"" foo
+		sleep 5
+		warning "telnet: connection refused."
+	    }
+	    -re "Sorry, this system is engaged.*" {
+		exp_send "\003"
+		warning "telnet: already connected."
+	    }
+	    "Connection closed by foreign host.*$" {
+		warning "telnet: connection closed by foreign host."
+		break
+	    }
+	    -re "\[\r\n\]+" {
+		exp_continue
+	    }
+	    timeout {
+		exp_send "\n"
+	    }
+	    eof {
+		warning "telnet: got unexpected EOF from telnet."
+		catch close
+		catch wait
+		set need_respawn 1
+		sleep 5
+	    }
+	}
+	incr tries
+    }
+
+    
+    verbose "spawn id is $spawn_id"
+    set board_info($dest,fileid) $spawn_id;
+    return $spawn_id
+}
+
+# Use telnet to spawn a session 
+proc telnet_gdbserver_spawn { dest username commandline } {
+    global board_info
+    set remote $dest
+    set telnet_prog "telnet"
+    set prompt [target_info shell_prompt]
+    set mport 23 
+    verbose "commandline is $commandline"
+    return [mynewtelnet_open_and_exec $remote $mport $prompt $commandline]
+}
+
+
+#
+# Use $RSH to spawn $commandline on remote machine $dest as user $username.
+# (Note $username on $dest will have to have appropriate .rhost entries.)
+#
+proc rsh_gdbserver_spawn { dest username commandline } {
+    global board_info
+
+    if [target_info exists rsh_prog] {
+	set RSH [target_info rsh_prog];
+    } else {
+        set RSH rsh
+    }
+
+    if [board_info $dest exists hostname] {
+	set remote [board_info $dest hostname];
+    } else {
+	set remote $dest;
+    }
+
+    if { $username == "" } {
+	set rsh_useropts ""
+    } else {
+	set rsh_useropts "-l"
+    }
+
+    verbose "spawn $RSH $rsh_useropts $username $remote $commandline";
+    spawn $RSH $rsh_useropts $username $remote $commandline;
+    set board_info($dest,fileid) $spawn_id;
+
+    set timeout 60
+    expect {
+	# expect output from $spawn_id
+	-i $spawn_id
+	-re "(.*No route to host)|(poll: protocol failure in circuit setup)|(.*Unknown host)|(.*Connection refused)|(Login incorrect)|(Permission denied)" {
+	    verbose -log "$RSH to $remote failed, output \"$expect_out(buffer)\""
+	    return -1
+	}
+	-re ".*\r" { }
+	timeout {
+	    verbose -log "$RSH to $remote timedout (timeout=$timeout)"
+	    return -1
+	}
+	eof {
+	    verbose -log "$RSH to $remote failed"	    
+	    return -1
+	}
+    }
+
+    return $spawn_id;
+}
+
+#
+# Download $srcfile to $destfile on $desthost as user $username using rcp.
+#
+
+proc gdbserver_download {desthost username srcfile destfile} {
+    if [target_info exists rsh_prog] {
+	set RSH [target_info rsh_prog];
+    } else {
+        set RSH rsh
+    }
+
+    if ![target_info exists rcp_prog] {
+        set RCP rcp
+    } else {
+	set RCP [target_info rcp_prog];
+    }
+
+    if [board_info $desthost exists name] {
+	set desthost [board_info $desthost name];
+    }
+
+    if [board_info $desthost exists hostname] {
+	set desthost [board_info $desthost hostname];
+    }
+
+    if { $username == "" } {
+	set rsh_useropts ""
+	set rcp_dest $desthost
+    } else {
+	set rsh_useropts "-l $username"
+	set rcp_dest "$username@$desthost"
+    }
+
+    # Delete the output file
+    # set status [catch "exec $RSH $rsh_useropts $desthost rm -f $destfile |& cat" output] 
+
+    if { $RCP != "cp" } {
+	set status [catch "exec $RCP $srcfile $rcp_dest:$destfile |& cat" output]
+    } else {
+	if [target_info exists nfsdir] {
+	    set nfsdir [target_info nfsdir];
+	    verbose -log "nfsdir is  $nfsdir"
+	    set status [catch "exec cp $srcfile $nfsdir/$destfile |& cat" output]
+	} else {
+	    verbose "\nnfsdir not set\n"
+	    set status 1
+	}
+    }
+    if { $status == 0 } {
+	if [target_info exists nfsdir] {
+	    verbose "Copied $srcfile to $nfsdir/$destfile" 2
+	    return $destfile;
+	} else {
+	    verbose "Copied $srcfile to $desthost:$destfile" 2
+	    return $destfile;
+	}
+    } else {
+	verbose "Download to $desthost failed, $output."
+	return ""
+    }
+}
diff --git a/gdb/testsuite/gdb.arch/arc-step-jtag.exp b/gdb/testsuite/gdb.arch/arc-step-jtag.exp
new file mode 100644
index 0000000..a51f00e
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/arc-step-jtag.exp
@@ -0,0 +1,88 @@
+if $tracelevel {
+    strace $tracelevel
+}
+
+# Test single-stepping zero-overhead-loops and delay slots
+
+if ![istarget "arc-*-*"] then {
+    verbose "Skipping ARC single-step tests."
+    return
+}
+
+if ![istarget "*elf32*"] then {
+    verbose "Skipping ARC JTAG single-step tests."
+    return
+}
+
+set testfile "arc-step-jtag"
+set srcfile ${testfile}.s
+set binfile ${objdir}/${subdir}/${testfile}
+if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable ""] != "" } {
+    gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail."
+}
+
+gdb_exit
+gdb_start
+gdb_reinitialize_dir $srcdir/$subdir
+
+if { [ gdb_load ${binfile} ] != 0 } {
+    gdb_suppress_entire_file "Load failed, so all tests in this file will automatically fail."
+}
+
+#
+# Run to `main' where we begin our tests.
+#
+
+gdb_test "adv _main" 	".* in _main .*"  "advance to _main"
+
+gdb_test "stepi"     	".* Lmov .*"      "step mov instruction"
+gdb_test "p \$r0"    	".*= 1"           "r0 value after mov instruction"
+
+gdb_test "stepi"     	".* Lmov_s .*"    "step mov_s instruction"
+gdb_test "p \$r0"    	".*= 2"           "r0 value after mov_s instruction"
+
+gdb_test "stepi"     	".* Lb .*"        "step b instruction"
+
+gdb_test "stepi"     	".* Lb_s .*"      "step b_s instruction"
+
+gdb_test "stepi"     	".* Lbdotd_dslot .*"    "step b.d branch"
+gdb_test "stepi"     	".* Lbdotd .*"          "step b.d delay slot"
+gdb_test "p \$r0"    	".*= 5"                 "r0 value after b.d delay slot"
+
+gdb_test "stepi"     	".* Lbl .*"       "step bl instruction"
+
+gdb_test "stepi"     	".* Lj_sdotd_dslot .*"  "step j_s.d \[blink\] branch"
+gdb_test "stepi"     	".* Lj_sdotd .*"        "step j_s.d \[blink\] delay slot"
+gdb_test "p \$r0"    	".*= 6"                 "r0 value after j_s.d \[blink\] delay slot"
+
+gdb_test "stepi"     	".* Lj .*"        "step j instruction"
+
+gdb_test "stepi"     	".*"              "step mov instruction"
+gdb_test "stepi"     	".* ZOLstart .*"  "step lp instruction"
+
+gdb_test "p \$lp_count" ".*= 3"           "lp_count value"
+gdb_test "p \$lp_end - \$lp_start" \
+                        ".* = 8"          "lp_end - lp_start == 8"
+
+gdb_test "p \$r0"       ".* = 6"          "r0 value before loop"
+
+# step thru the loop, checking the value of r0
+
+# first iteration
+gdb_test "stepi"        ".* ZOLmiddle .*" "step add instruction (inside ZOL)"
+gdb_test "p \$r0"       ".* = 7"          "r0 value after 1 iteration"
+gdb_test "stepi"        ".* ZOLstart .*"  "step across end of ZOL"
+
+# second iteration
+gdb_test "stepi"        ".* ZOLmiddle .*" "step add instruction (inside ZOL)"
+gdb_test "p \$r0"       ".* = 8"          "r0 value after 2 iterations"
+gdb_test "stepi"        ".* ZOLstart .*"  "step across end of ZOL"
+
+# last iteration
+gdb_test "stepi"        ".* ZOLmiddle .*" "step add instruction (inside ZOL)"
+gdb_test "p \$r0"       ".* = 9"          "r0 value after 3 iterations"
+gdb_test "stepi"        ".* ZOLend .*"    "step out of end of ZOL"
+
+# exit(r0)
+gdb_test "continue"     ".*Program exited.*011.*" \
+                                          "value of r0 on exit"
diff --git a/gdb/testsuite/gdb.arch/arc-step-jtag.s b/gdb/testsuite/gdb.arch/arc-step-jtag.s
new file mode 100644
index 0000000..7ad8e1f
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/arc-step-jtag.s
@@ -0,0 +1,46 @@
+_main:
+	.global _main
+main:	
+	.global main
+
+	mov   r0,1		; 32 bit instruction
+Lmov:	
+	mov_s r0,2		; 16 bit instruction
+Lmov_s:	
+	b Lb			; 32 bit, no delay slot
+	mov r0,3
+	nop
+Lb:	
+	b_s Lb_s		; 16 bit, no delay slot
+	mov r0,4
+	nop
+Lb_s:	
+	b.d Lbdotd		; 32 bit, delay slot
+Lbdotd_dslot:
+	mov r0,5
+	nop
+Lbdotd:
+
+	bl Lbl
+Lj_sdotd:
+	j Lj
+Lbl:	
+	j_s.d [blink]		; 16 bit, delay slot
+Lj_sdotd_dslot:
+	mov r0,6
+Lj:	
+	mov lp_count,3		; zero-overhead loop
+	lp ZOLend
+ZOLstart:
+	add r0,r0,1
+ZOLmiddle:
+	nop
+ZOLend:	
+	;; r0 should be 9
+	
+	
+	;; exit(r0)
+	flag 1
+	nop
+	nop
+	nop
diff --git a/gdb/testsuite/gdb.arch/arc-step.exp b/gdb/testsuite/gdb.arch/arc-step.exp
new file mode 100644
index 0000000..e958b5f
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/arc-step.exp
@@ -0,0 +1,83 @@
+if $tracelevel {
+    strace $tracelevel
+}
+
+# Test single-stepping zero-overhead-loops and delay slots
+
+if ![istarget "arc-*-*"] then {
+    verbose "Skipping ARC single-step tests."
+    return
+}
+
+if ![istarget "*linux*"] then {
+    verbose "Skipping ARC linux single-step tests."
+    return
+}
+
+set testfile "arc-step"
+set srcfile ${testfile}.s
+set binfile ${objdir}/${subdir}/${testfile}
+if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable ""] != "" } {
+    gdb_suppress_entire_file "Testcase compile failed, so all tests in this file will automatically fail."
+}
+
+gdb_exit
+gdb_start
+gdb_reinitialize_dir $srcdir/$subdir
+gdb_load ${binfile}
+
+#
+# Run to `main' where we begin our tests.
+#
+
+gdb_test "adv _main" 	".* in _main .*"  "advance to _main"
+
+gdb_test "stepi"     	".* Lmov .*"      "step mov instruction"
+gdb_test "p \$r0"    	".*= 1"           "r0 value after mov instruction"
+
+gdb_test "stepi"     	".* Lmov_s .*"    "step mov_s instruction"
+gdb_test "p \$r0"    	".*= 2"           "r0 value after mov_s instruction"
+
+gdb_test "stepi"     	".* Lb .*"        "step b instruction"
+
+gdb_test "stepi"     	".* Lb_s .*"      "step b_s instruction"
+
+gdb_test "stepi"     	".* Lbdotd .*"    "step b.d instruction"
+gdb_test "p \$r0"    	".*= 5"           "r0 value after b.d instruction"
+
+gdb_test "stepi"     	".* Lbl .*"       "step bl instruction"
+
+gdb_test "stepi"     	".* Lj_sdotd .*"  "step j_s.d \[blink\] instruction"
+gdb_test "p \$r0"    	".*= 6"           "r0 value after j_s.d \[blink\] instruction"
+
+gdb_test "stepi"     	".* Lj .*"        "step j instruction"
+
+gdb_test "stepi"     	".*"              "step mov instruction"
+gdb_test "stepi"     	".* ZOLstart .*"  "step lp instruction"
+
+gdb_test "p \$lp_count" ".*= 3"           "lp_count value"
+gdb_test "p \$lp_end - \$lp_start" \
+                        ".* = 8"          "lp_end - lp_start == 8"
+
+gdb_test "p \$r0"       ".* = 6"          "r0 value before loop"
+
+# step thru the loop, checking the value of r0
+
+# first iteration
+gdb_test "stepi"        ".* ZOLmiddle .*" "step add instruction (inside ZOL)"
+gdb_test "p \$r0"       ".* = 7"          "r0 value after 1 iteration"
+gdb_test "stepi"        ".* ZOLstart .*"  "step across end of ZOL"
+
+# second iteration
+gdb_test "stepi"        ".* ZOLmiddle .*" "step add instruction (inside ZOL)"
+gdb_test "p \$r0"       ".* = 8"          "r0 value after 1 iteration"
+gdb_test "stepi"        ".* ZOLstart .*"  "step across end of ZOL"
+
+# last iteration
+gdb_test "stepi"        ".* ZOLmiddle .*" "step add instruction (inside ZOL)"
+gdb_test "p \$r0"       ".* = 9"          "r0 value after 1 iteration"
+gdb_test "stepi"        ".* ZOLend .*"    "step out of end of ZOL"
+
+# exit(r0)
+gdb_test "continue"     ".*Program exited.*011.*" \
+                                          "value of r0 on exit"
diff --git a/gdb/testsuite/gdb.arch/arc-step.s b/gdb/testsuite/gdb.arch/arc-step.s
new file mode 100644
index 0000000..8dce39a
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/arc-step.s
@@ -0,0 +1,43 @@
+_main:
+	.global _main
+main:	
+	.global main
+
+	mov   r0,1		; 32 bit instruction
+Lmov:	
+	mov_s r0,2		; 16 bit instruction
+Lmov_s:	
+	b Lb			; 32 bit, no delay slot
+	mov r0,3
+	nop
+Lb:	
+	b_s Lb_s		; 16 bit, no delay slot
+	mov r0,4
+	nop
+Lb_s:	
+	b.d Lbdotd		; 32 bit, delay slot
+	mov r0,5
+	nop
+Lbdotd:
+
+	bl Lbl
+Lj_sdotd:
+	j Lj
+Lbl:	
+	j_s.d [blink]		; 16 bit, delay slot
+	mov r0,6
+Lj:	
+	mov lp_count,3		; zero-overhead loop
+	lp ZOLend
+ZOLstart:
+	add r0,r0,1
+ZOLmiddle:
+	nop
+ZOLend:	
+	;; r0 should be 9
+	
+	
+	;; exit(r0)
+	;; mov r0,0
+	mov r8,1
+	trap_s 0
diff --git a/gdb/testsuite/gdb.asm/arc.inc b/gdb/testsuite/gdb.asm/arc.inc
new file mode 100644
index 0000000..e22c35c
--- /dev/null
+++ b/gdb/testsuite/gdb.asm/arc.inc
@@ -0,0 +1,55 @@
+
+	comment "subroutine prologue"
+	.macro gdbasm_enter
+	st.a    blink,[sp,-4]
+	st.a	fp, [sp,-4]
+	mov	fp,sp
+	.endm
+
+	comment "subroutine epilogue"
+	.macro gdbasm_leave
+	ld.ab  fp, [sp,4]
+	ld     blink,[sp,0]
+	j.d    [blink]
+	add    sp,sp,4
+	.endm
+
+	.macro gdbasm_call subr
+	bl	\subr
+	.endm
+
+	.macro gdbasm_several_nops
+	nop
+	nop
+	nop
+	nop
+	.endm
+
+	comment "exit (0)"
+	.macro gdbasm_exit0
+	mov_s    r0,0
+	trap_s	 0
+	.endm
+
+	comment "crt0 startup"
+	.macro gdbasm_startup
+	mov    fp, 0
+	.endm
+
+	comment "Declare a data variable"
+	.macro gdbasm_datavar name value
+	.data
+\name:
+	.long	\value
+	.endm
+
+	comment "Declare the start of a subroutine"
+	.macro gdbasm_declare name
+	.type	\name, @function
+\name:
+	.endm
+
+	comment "End a subroutine"
+	.macro gdbasm_end name
+	.size	\name, .-name
+	.endm
diff --git a/gdb/testsuite/lib/arc-gdbserver.exp b/gdb/testsuite/lib/arc-gdbserver.exp
new file mode 100644
index 0000000..6674e92
--- /dev/null
+++ b/gdb/testsuite/lib/arc-gdbserver.exp
@@ -0,0 +1,98 @@
+# Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software
+# Foundation, Inc.
+#
+# This file is part of DejaGnu.
+#
+# DejaGnu is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# DejaGnu is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with DejaGnu; if not, write to the Free Software Foundation,
+# Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# gdbserver running cross
+
+#load the config file
+load_generic_config "remote-gdbserver"
+
+
+process_multilib_options ""
+
+# The default compiler for this target.
+set_board_info compiler  "$env(GDBTEST_CC)"
+set_board_info cflags    "$env(GDBTEST_CFLAGS)"
+set_board_info assembler "$env(GDBTEST_AS) $env(GDBTEST_ASFLAGS)"
+set_board_info linker    "$env(GDBTEST_LD)" 
+set_board_info ldflags   "$env(GDBTEST_LDFLAGS)"
+
+# We will be using the standard GDB remote protocol
+set_board_info gdb_protocol "remote"
+
+set_board_info netport "$env(GDBTEST_GDBSERVER_HOST):$env(GDBTEST_GDBSERVER_PORT)"
+
+# Path to the gdbserver executable, if required.
+set_board_info gdb_server_prog $env(GDBTEST_GDBSERVER_PATH)
+#    "../gdbserver/gdbserver"
+
+# Name of the computer whose socket will be used, if required.
+set_board_info sockethost "$env(GDBTEST_GDBSERVER_HOST):"
+
+# Port ID to use for socket connection
+set_board_info gdb,socketport $env(GDBTEST_GDBSERVER_PORT)
+
+# Use techniques appropriate to a stub
+set_board_info use_gdb_stub 1
+
+# This gdbserver can only run a process once per session.
+set_board_info gdb,do_reload_on_run 1
+
+# There's no support for argument-passing (yet).
+set_board_info noargs 1
+
+# Can't do FILE IO in current gdbserver
+set_board_info gdb,nofileio 1
+
+# Can't do input (or output) in the current gdbserver.
+set_board_info gdb,noinferiorio 1
+
+# Can't do hardware watchpoints, in general
+set_board_info gdb,no_hardware_watchpoints 1
+
+# Copy the testcases using cp 
+set_board_info rcp_prog "cp"
+
+
+# Set nfs directory 
+# On my machine this is how it is mounted. - ramana
+# kanika:/home/opt/share on /mnt/nfsmounts type nfs (rw,addr=192.168.100.68)
+set_board_info nfsdir $env(GDBTEST_NFSDIR)
+
+# Set the test directory on the board. Where is this mounted 
+# on the board. 
+set_board_info tests_dir $env(GDBTEST_TESTS_DIR)
+
+# run on target using rsh
+set_board_info rsh_prog "rsh"
+
+# Download directory
+set_board_info download_dir $env(GDBTEST_DOWNLOAD_DIR)
+
+# Hostname 
+set_board_info hostname $env(GDBTEST_GDBSERVER_HOST)
+set_board_info username "root"
+set_board_info sockethost "$env(GDBTEST_GDBSERVER_HOST):"
+
+#Shell prompt
+set_board_info shell_prompt "\[arcLinux\]$"
+
+#set_board_info board,connect "telnet"
+
+# timeout
+#set_board_info gdb,timeout 300
diff --git a/gdb/testsuite/lib/arc-jtag.exp b/gdb/testsuite/lib/arc-jtag.exp
new file mode 100644
index 0000000..c613f30
--- /dev/null
+++ b/gdb/testsuite/lib/arc-jtag.exp
@@ -0,0 +1,32 @@
+#
+# The baseboard file for the arcjtag target
+#
+
+load_generic_config "arc-jtag"
+
+set_board_info compiler  "$env(GDBTEST_CC)"
+set_board_info cflags    "$env(GDBTEST_CFLAGS)"
+set_board_info assembler "$env(GDBTEST_AS) $env(GDBTEST_ASFLAGS)"
+set_board_info linker    "$env(GDBTEST_LD)"
+set_board_info ldflags   "$env(GDBTEST_LDFLAGS)"
+
+#Reload the file before running
+set_board_info gdb,do_reload_on_run 1
+
+#Arguments cannot be passed
+set_board_info noargs               1
+
+#File IO not supported
+set_board_info gdb,nofileio         1
+
+#Inferior is unable to do I/O
+set_board_info gdb,noinferiorio     1
+
+#Signals not supported
+set_board_info gdb,nosignals        1
+
+#Skip the huge.exp test
+set_board_info gdb,skip_huge_test   1
+
+#We use "target arcjtag" to talk to JTAG
+set_board_info gdb_protocol         "arcjtag"
diff --git a/gdb/testsuite/lib/telnet-exec.exp b/gdb/testsuite/lib/telnet-exec.exp
new file mode 100644
index 0000000..8bbaa8d
--- /dev/null
+++ b/gdb/testsuite/lib/telnet-exec.exp
@@ -0,0 +1,29 @@
+#!/usr/bin/expect -f 
+
+#
+#
+#
+
+
+set host "192.168.100.222"
+set debuggee [lindex $argv 0]
+
+set timeout 360
+set env(TERM) vt100;			# actual value doesn't matter, just has to be set
+
+spawn telnet $host
+sleep 1;				# wait for telnet to happen
+send "PS1=\\# \r"
+expect "\# "
+#expect "\[arcLinux\]\$"
+#send_user "one\n"
+
+
+send "cd /nfs/gdbserver-tests/ \r"
+expect "\# "
+#expect "\[arcLinux\]\$"
+send_user "starting gdbserver...\n"
+send "./gdbserver host:4004 /nfs/gdbserver-tests/ramana-tests/a-4004.out \r"
+
+expect "xxx"
+send "exit"
\ No newline at end of file
diff --git a/include/elf/ChangeLog.codito b/include/elf/ChangeLog.codito
new file mode 100644
index 0000000..d30c7c4
--- /dev/null
+++ b/include/elf/ChangeLog.codito
@@ -0,0 +1,8 @@
+2005-05-15  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* arc.h: Merge new ELF relocs.
+
+2005-05-12  Ramana Radhakrishnan  <ramana@codito.com>
+
+	* dwarf2.h: Add Metaware specific CFA info. 
+
diff --git a/opcodes/ChangeLog.codito b/opcodes/ChangeLog.codito
new file mode 100644
index 0000000..253e0df
--- /dev/null
+++ b/opcodes/ChangeLog.codito
@@ -0,0 +1,16 @@
+2006-03-03  Ashwin Pathmudi  <ashwin.pathmudi@codito.com>
+
+	* arc-dis.c (a4AnalyzeInstr): New. Disassembler function
+	called by gdb for the a4 core.  
+
+2005-03-30  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arcompact-dis.c(dsmOneArcInst): Update ARC register information
+	for the debugger.
+	* include/opcode/arc.h: Update struct arcDisState to contain
+	information about the targets of operands.
+
+2005-03-07  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* arcompact-dis.c(dsmOneArcInst):Update address
+	writeback for the debugger. 
diff --git a/opcodes/arc-asm.c b/opcodes/arc-asm.c
new file mode 100644
index 0000000..498a7fd
--- /dev/null
+++ b/opcodes/arc-asm.c
@@ -0,0 +1,898 @@
+/* Assembler interface for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
+
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2007
+   Free Software Foundation, Inc.
+
+   This file is part of libopcodes.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "arc-desc.h"
+#include "arc-opc.h"
+#include "opintl.h"
+#include "xregex.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+
+#undef  min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef  max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
+
+/* -- assembler routines inserted here.  */
+
+/* -- asm.c */
+#if 0
+static const char * MISSING_CLOSING_PARENTHESIS = N_("missing `)'");
+
+/* Handle '#' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    const char **strp,
+	    int opindex ATTRIBUTE_UNUSED,
+	    long *valuep ATTRIBUTE_UNUSED)
+{
+  if (**strp == '#')
+    ++*strp;
+  return NULL;
+}
+
+/* Handle shigh(), high().  */
+
+static const char *
+parse_hi16 (CGEN_CPU_DESC cd,
+	    const char **strp,
+	    int opindex,
+	    unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  if (**strp == '#')
+    ++*strp;
+
+  if (strncasecmp (*strp, "high(", 5) == 0)
+    {
+      *strp += 5;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_ULO,
+				   & result_type, & value);
+      if (**strp != ')')
+	return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+  	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	{
+	  value >>= 16;
+	  value &= 0xffff;
+	}
+      *valuep = value;
+      return errmsg;
+    }
+  else if (strncasecmp (*strp, "shigh(", 6) == 0)
+    {
+      *strp += 6;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_HI16_SLO,
+ 				   & result_type, & value);
+      if (**strp != ')')
+	return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+        {
+          value += 0x8000;
+          value >>= 16;
+	  value &= 0xffff;
+        }
+      *valuep = value;
+      return errmsg;
+    }
+
+  return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+
+/* Handle low() in a signed context.  Also handle sda().
+   The signedness of the value doesn't matter to low(), but this also
+   handles the case where low() isn't present.  */
+
+static const char *
+parse_slo16 (CGEN_CPU_DESC cd,
+	     const char ** strp,
+	     int opindex,
+	     long * valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  if (**strp == '#')
+    ++*strp;
+
+  if (strncasecmp (*strp, "low(", 4) == 0)
+    {
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
+				   & result_type, & value);
+      if (**strp != ')')
+	return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	value = ((value & 0xffff) ^ 0x8000) - 0x8000;
+      *valuep = value;
+      return errmsg;
+    }
+
+  if (strncasecmp (*strp, "sda(", 4) == 0)
+    {
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_SDA16,
+				   NULL, & value);
+      if (**strp != ')')
+	return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return cgen_parse_signed_integer (cd, strp, opindex, valuep);
+}
+
+/* Handle low() in an unsigned context.
+   The signedness of the value doesn't matter to low(), but this also
+   handles the case where low() isn't present.  */
+
+static const char *
+parse_ulo16 (CGEN_CPU_DESC cd,
+	     const char **strp,
+	     int opindex,
+	     unsigned long *valuep)
+{
+  const char *errmsg;
+  enum cgen_parse_operand_result result_type;
+  bfd_vma value;
+
+  if (**strp == '#')
+    ++*strp;
+
+  if (strncasecmp (*strp, "low(", 4) == 0)
+    {
+      *strp += 4;
+      errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_M32R_LO16,
+				   & result_type, & value);
+      if (**strp != ')')
+	return MISSING_CLOSING_PARENTHESIS;
+      ++*strp;
+      if (errmsg == NULL
+	  && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER)
+	value &= 0xffff;
+      *valuep = value;
+      return errmsg;
+    }
+
+  return cgen_parse_unsigned_integer (cd, strp, opindex, valuep);
+}
+#endif
+
+/* -- */
+
+const char * arc_cgen_parse_operand
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
+
+/* Main entry point for operand parsing.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  */
+
+const char *
+arc_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
+{
+  const char * errmsg = NULL;
+  /* Used by scalar operands that still need to be parsed.  */
+  long junk ATTRIBUTE_UNUSED;
+
+  switch (opindex)
+    {
+    case ARC_OPERAND_EXDI :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Di, & fields->f_F);
+      break;
+    case ARC_OPERAND_F :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_uflags, & fields->f_F);
+      break;
+    case ARC_OPERAND_F0 :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_nil, & fields->f_F);
+      break;
+    case ARC_OPERAND_F1 :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_auflags, & fields->f_F);
+      break;
+    case ARC_OPERAND_F1F :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_aufflags, & fields->f_F);
+      break;
+    case ARC_OPERAND_GP :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_gp, & junk);
+      break;
+    case ARC_OPERAND_LDODI :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Di, & fields->f_LDODi);
+      break;
+    case ARC_OPERAND_LDRDI :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Di, & fields->f_LDRDi);
+      break;
+    case ARC_OPERAND_NE :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_ne, & junk);
+      break;
+    case ARC_OPERAND_PCL :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_pcl, & junk);
+      break;
+    case ARC_OPERAND_QCONDB :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Qcondb, & fields->f_cond_Q);
+      break;
+    case ARC_OPERAND_QCONDI :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Qcondi, & fields->f_cond_Q);
+      break;
+    case ARC_OPERAND_QCONDJ :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Qcondj, & fields->f_cond_Q);
+      break;
+    case ARC_OPERAND_R0 :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_r0, & junk);
+      break;
+    case ARC_OPERAND_R31 :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_r31, & junk);
+      break;
+    case ARC_OPERAND_RA :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_cr_names, & fields->f_op_A);
+      break;
+    case ARC_OPERAND_RA_0 :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_nil, & fields->f_op_A);
+      break;
+    case ARC_OPERAND_RB :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_cr_names, & fields->f_op_B);
+      break;
+    case ARC_OPERAND_RB_0 :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_nil, & fields->f_op_B);
+      break;
+    case ARC_OPERAND_RC :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_cr_names, & fields->f_op_C);
+      break;
+    case ARC_OPERAND_RC_ILINK :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_ilinkx, & fields->f_op_Cj);
+      break;
+    case ARC_OPERAND_RC_NOILINK :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_noilink, & fields->f_op_Cj);
+      break;
+    case ARC_OPERAND_R_A :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_cr16, & fields->f_op__a);
+      break;
+    case ARC_OPERAND_R_B :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_cr16, & fields->f_op__b);
+      break;
+    case ARC_OPERAND_R_C :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_cr16, & fields->f_op__c);
+      break;
+    case ARC_OPERAND_RCC :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Rcc, & fields->f_brcond);
+      break;
+    case ARC_OPERAND_RCCS :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_RccS, & fields->f_brscond);
+      break;
+    case ARC_OPERAND_RH :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_cr_names, & fields->f_op_h);
+      break;
+    case ARC_OPERAND_SP :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_sp, & junk);
+      break;
+    case ARC_OPERAND_STODI :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_Di, & fields->f_STODi);
+      break;
+    case ARC_OPERAND_U6 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U6, (unsigned long *) (& fields->f_u6));
+      break;
+    case ARC_OPERAND_U6X2 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U6X2, (unsigned long *) (& fields->f_u6x2));
+      break;
+    case ARC_OPERAND__AW :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h__aw, & junk);
+      break;
+    case ARC_OPERAND__L :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_insn32, & junk);
+      break;
+    case ARC_OPERAND__S :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_insn16, & junk);
+      break;
+    case ARC_OPERAND_CBIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_CBIT, (unsigned long *) (& junk));
+      break;
+    case ARC_OPERAND_DELAY_N :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_delay, & fields->f_delay_N);
+      break;
+    case ARC_OPERAND_DUMMY_OP :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_DUMMY_OP, (unsigned long *) (& fields->f_dummy));
+      break;
+    case ARC_OPERAND_I2COND :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_i2cond, & fields->f_cond_i2);
+      break;
+    case ARC_OPERAND_I3COND :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_i3cond, & fields->f_cond_i3);
+      break;
+    case ARC_OPERAND_LABEL10 :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL10, 0, NULL,  & value);
+        fields->f_rel10 = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL13A :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL13A, 0, NULL,  & value);
+        fields->f_rel13bl = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL21 :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL21, 0, NULL,  & value);
+        fields->f_rel21 = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL21A :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL21A, 0, NULL,  & value);
+        fields->f_rel21bl = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL25 :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL25, 0, NULL,  & value);
+        fields->f_rel25 = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL25A :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL25A, 0, NULL,  & value);
+        fields->f_rel25bl = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL7 :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL7, 0, NULL,  & value);
+        fields->f_rel7 = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL8 :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL8, 0, NULL,  & value);
+        fields->f_rel8 = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL9 :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, ARC_OPERAND_LABEL9, 0, NULL,  & value);
+        fields->f_rel9 = value;
+      }
+      break;
+    case ARC_OPERAND_LBIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_LBIT, (unsigned long *) (& junk));
+      break;
+    case ARC_OPERAND_NBIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_NBIT, (unsigned long *) (& junk));
+      break;
+    case ARC_OPERAND_S12 :
+      errmsg = cgen_parse_signed_integer (cd, strp, ARC_OPERAND_S12, (long *) (& fields->f_s12));
+      break;
+    case ARC_OPERAND_S12X2 :
+      errmsg = cgen_parse_signed_integer (cd, strp, ARC_OPERAND_S12X2, (long *) (& fields->f_s12x2));
+      break;
+    case ARC_OPERAND_S1BIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_S1BIT, (unsigned long *) (& junk));
+      break;
+    case ARC_OPERAND_S2BIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_S2BIT, (unsigned long *) (& junk));
+      break;
+    case ARC_OPERAND_S9 :
+      errmsg = cgen_parse_signed_integer (cd, strp, ARC_OPERAND_S9, (long *) (& fields->f_s9));
+      break;
+    case ARC_OPERAND_S9X4 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_S9X4, (unsigned long *) (& fields->f_s9x4));
+      break;
+    case ARC_OPERAND_SC_S9_ :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_S9_, (unsigned long *) (& fields->f_s9x4));
+      break;
+    case ARC_OPERAND_SC_S9B :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_S9B, (unsigned long *) (& fields->f_s9x1));
+      break;
+    case ARC_OPERAND_SC_S9W :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_S9W, (unsigned long *) (& fields->f_s9x2));
+      break;
+    case ARC_OPERAND_SC_U5_ :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_U5_, (unsigned long *) (& fields->f_u5x4));
+      break;
+    case ARC_OPERAND_SC_U5B :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_U5B, (unsigned long *) (& fields->f_u5));
+      break;
+    case ARC_OPERAND_SC_U5W :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_SC_U5W, (unsigned long *) (& fields->f_u5x2));
+      break;
+    case ARC_OPERAND_TRAPNUM :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_TRAPNUM, (unsigned long *) (& fields->f_trapnum));
+      break;
+    case ARC_OPERAND_U3 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U3, (unsigned long *) (& fields->f_u3));
+      break;
+    case ARC_OPERAND_U5 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U5, (unsigned long *) (& fields->f_u5));
+      break;
+    case ARC_OPERAND_U5X4 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U5X4, (unsigned long *) (& fields->f_u5x4));
+      break;
+    case ARC_OPERAND_U7 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U7, (unsigned long *) (& fields->f_u7));
+      break;
+    case ARC_OPERAND_U8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U8, (unsigned long *) (& fields->f_u8));
+      break;
+    case ARC_OPERAND_U8X4 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_U8X4, (unsigned long *) (& fields->f_u8x4));
+      break;
+    case ARC_OPERAND_UNCONDB :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_uncondb, & junk);
+      break;
+    case ARC_OPERAND_UNCONDI :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_uncondi, & junk);
+      break;
+    case ARC_OPERAND_UNCONDJ :
+      errmsg = cgen_parse_keyword (cd, strp, & arc_cgen_opval_h_uncondj, & junk);
+      break;
+    case ARC_OPERAND_VBIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_VBIT, (unsigned long *) (& junk));
+      break;
+    case ARC_OPERAND_ZBIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, ARC_OPERAND_ZBIT, (unsigned long *) (& junk));
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+cgen_parse_fn * const arc_cgen_parse_handlers[] = 
+{
+  parse_insn_normal,
+};
+
+void
+arc_cgen_init_asm (CGEN_CPU_DESC cd)
+{
+  arc_cgen_init_opcode_table (cd);
+  arc_cgen_init_ibld_table (cd);
+  cd->parse_handlers = & arc_cgen_parse_handlers[0];
+  cd->parse_operand = arc_cgen_parse_operand;
+#ifdef CGEN_ASM_INIT_HOOK
+CGEN_ASM_INIT_HOOK
+#endif
+}
+
+
+
+/* Regex construction routine.
+
+   This translates an opcode syntax string into a regex string,
+   by replacing any non-character syntax element (such as an
+   opcode) with the pattern '.*'
+
+   It then compiles the regex and stores it in the opcode, for
+   later use by arc_cgen_assemble_insn
+
+   Returns NULL for success, an error message for failure.  */
+
+char * 
+arc_cgen_build_insn_regex (CGEN_INSN *insn)
+{  
+  CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+  const char *mnem = CGEN_INSN_MNEMONIC (insn);
+  char rxbuf[CGEN_MAX_RX_ELEMENTS];
+  char *rx = rxbuf;
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+  int reg_err;
+
+  syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
+
+  /* Mnemonics come first in the syntax string.  */
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+    return _("missing mnemonic in syntax string");
+  ++syn;
+
+  /* Generate a case sensitive regular expression that emulates case
+     insensitive matching in the "C" locale.  We cannot generate a case
+     insensitive regular expression because in Turkish locales, 'i' and 'I'
+     are not equal modulo case conversion.  */
+
+  /* Copy the literal mnemonic out of the insn.  */
+  for (; *mnem; mnem++)
+    {
+      char c = *mnem;
+
+      if (ISALPHA (c))
+	{
+	  *rx++ = '[';
+	  *rx++ = TOLOWER (c);
+	  *rx++ = TOUPPER (c);
+	  *rx++ = ']';
+	}
+      else
+	*rx++ = c;
+    }
+
+  /* Copy any remaining literals from the syntax string into the rx.  */
+  for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+    {
+      if (CGEN_SYNTAX_CHAR_P (* syn)) 
+	{
+	  char c = CGEN_SYNTAX_CHAR (* syn);
+
+	  switch (c) 
+	    {
+	      /* Escape any regex metacharacters in the syntax.  */
+	    case '.': case '[': case '\\': 
+	    case '*': case '^': case '$': 
+
+#ifdef CGEN_ESCAPE_EXTENDED_REGEX
+	    case '?': case '{': case '}': 
+	    case '(': case ')': case '*':
+	    case '|': case '+': case ']':
+#endif
+	      *rx++ = '\\';
+	      *rx++ = c;
+	      break;
+
+	    default:
+	      if (ISALPHA (c))
+		{
+		  *rx++ = '[';
+		  *rx++ = TOLOWER (c);
+		  *rx++ = TOUPPER (c);
+		  *rx++ = ']';
+		}
+	      else
+		*rx++ = c;
+	      break;
+	    }
+	}
+      else
+	{
+	  /* Replace non-syntax fields with globs.  */
+	  *rx++ = '.';
+	  *rx++ = '*';
+	}
+    }
+
+  /* Trailing whitespace ok.  */
+  * rx++ = '['; 
+  * rx++ = ' '; 
+  * rx++ = '\t'; 
+  * rx++ = ']'; 
+  * rx++ = '*'; 
+
+  /* But anchor it after that.  */
+  * rx++ = '$'; 
+  * rx = '\0';
+
+  CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+  reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+  if (reg_err == 0) 
+    return NULL;
+  else
+    {
+      static char msg[80];
+
+      regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
+      regfree ((regex_t *) CGEN_INSN_RX (insn));
+      free (CGEN_INSN_RX (insn));
+      (CGEN_INSN_RX (insn)) = NULL;
+      return msg;
+    }
+}
+
+
+/* Default insn parser.
+
+   The syntax string is scanned and operands are parsed and stored in FIELDS.
+   Relocs are queued as we go via other callbacks.
+
+   ??? Note that this is currently an all-or-nothing parser.  If we fail to
+   parse the instruction, we return 0 and the caller will start over from
+   the beginning.  Backtracking will be necessary in parsing subexpressions,
+   but that can be handled there.  Not handling backtracking here may get
+   expensive in the case of the m68k.  Deal with later.
+
+   Returns NULL for success, an error message for failure.  */
+
+static const char *
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
+{
+  /* ??? Runtime added insns not handled yet.  */
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const char *str = *strp;
+  const char *errmsg;
+  const char *p;
+  const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+  /* FIXME: wip */
+  int past_opcode_p;
+#endif
+
+  /* For now we assume the mnemonic is first (there are no leading operands).
+     We can parse it without needing to set up operand parsing.
+     GAS's input scrubber will ensure mnemonics are lowercase, but we may
+     not be called from GAS.  */
+  p = CGEN_INSN_MNEMONIC (insn);
+  while (*p && TOLOWER (*p) == TOLOWER (*str))
+    ++p, ++str;
+
+  if (* p)
+    return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+  if (* str && ! ISSPACE (* str))
+    return _("unrecognized instruction");
+#endif
+
+  CGEN_INIT_PARSE (cd);
+  cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+  past_opcode_p = 0;
+#endif
+
+  /* We don't check for (*str != '\0') here because we want to parse
+     any trailing fake arguments in the syntax string.  */
+  syn = CGEN_SYNTAX_STRING (syntax);
+
+  /* Mnemonics come first for now, ensure valid string.  */
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+    abort ();
+
+  ++syn;
+
+  while (* syn != 0)
+    {
+      /* Non operand chars must match exactly.  */
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+	{
+	  /* FIXME: While we allow for non-GAS callers above, we assume the
+	     first char after the mnemonic part is a space.  */
+	  /* FIXME: We also take inappropriate advantage of the fact that
+	     GAS's input scrubber will remove extraneous blanks.  */
+	  if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+	    {
+#ifdef CGEN_MNEMONIC_OPERANDS
+	      if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+		past_opcode_p = 1;
+#endif
+	      ++ syn;
+	      ++ str;
+	    }
+	  else if (*str)
+	    {
+	      /* Syntax char didn't match.  Can't be this insn.  */
+	      static char msg [80];
+
+	      /* xgettext:c-format */
+	      sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+		       CGEN_SYNTAX_CHAR(*syn), *str);
+	      return msg;
+	    }
+	  else
+	    {
+	      /* Ran out of input.  */
+	      static char msg [80];
+
+	      /* xgettext:c-format */
+	      sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+		       CGEN_SYNTAX_CHAR(*syn));
+	      return msg;
+	    }
+	  continue;
+	}
+
+      /* We have an operand of some sort.  */
+      errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+					  &str, fields);
+      if (errmsg)
+	return errmsg;
+
+      /* Done with this operand, continue with next one.  */
+      ++ syn;
+    }
+
+  /* If we're at the end of the syntax string, we're done.  */
+  if (* syn == 0)
+    {
+      /* FIXME: For the moment we assume a valid `str' can only contain
+	 blanks now.  IE: We needn't try again with a longer version of
+	 the insn and it is assumed that longer versions of insns appear
+	 before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
+      while (ISSPACE (* str))
+	++ str;
+
+      if (* str != '\0')
+	return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+      return NULL;
+    }
+
+  /* We couldn't parse it.  */
+  return _("unrecognized instruction");
+}
+
+/* Main entry point.
+   This routine is called for each instruction to be assembled.
+   STR points to the insn to be assembled.
+   We assume all necessary tables have been initialized.
+   The assembled instruction, less any fixups, is stored in BUF.
+   Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+   still needs to be converted to target byte order, otherwise BUF is an array
+   of bytes in target byte order.
+   The result is a pointer to the insn's entry in the opcode table,
+   or NULL if an error occured (an error message will have already been
+   printed).
+
+   Note that when processing (non-alias) macro-insns,
+   this function recurses.
+
+   ??? It's possible to make this cpu-independent.
+   One would have to deal with a few minor things.
+   At this point in time doing so would be more of a curiosity than useful
+   [for example this file isn't _that_ big], but keeping the possibility in
+   mind helps keep the design clean.  */
+
+const CGEN_INSN *
+arc_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
+{
+  const char *start;
+  CGEN_INSN_LIST *ilist;
+  const char *parse_errmsg = NULL;
+  const char *insert_errmsg = NULL;
+  int recognized_mnemonic = 0;
+
+  /* Skip leading white space.  */
+  while (ISSPACE (* str))
+    ++ str;
+
+  /* The instructions are stored in hashed lists.
+     Get the first in the list.  */
+  ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+  /* Keep looking until we find a match.  */
+  start = str;
+  for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+    {
+      const CGEN_INSN *insn = ilist->insn;
+      recognized_mnemonic = 1;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
+      /* Not usually needed as unsupported opcodes
+	 shouldn't be in the hash lists.  */
+      /* Is this insn supported by the selected cpu?  */
+      if (! arc_cgen_insn_supported (cd, insn))
+	continue;
+#endif
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
+	 chosen immediately.  Instead, it is used during assembler/linker
+	 relaxation if possible.  */
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
+	continue;
+
+      str = start;
+
+      /* Skip this insn if str doesn't look right lexically.  */
+      if (CGEN_INSN_RX (insn) != NULL &&
+	  regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+	continue;
+
+      /* Allow parse/insert handlers to obtain length of insn.  */
+      CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+      parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+      if (parse_errmsg != NULL)
+	continue;
+
+      /* ??? 0 is passed for `pc'.  */
+      insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+						 (bfd_vma) 0);
+      if (insert_errmsg != NULL)
+        continue;
+
+      /* It is up to the caller to actually output the insn and any
+         queued relocs.  */
+      return insn;
+    }
+
+  {
+    static char errbuf[150];
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+    const char *tmp_errmsg;
+
+    /* If requesting verbose error messages, use insert_errmsg.
+       Failing that, use parse_errmsg.  */
+    tmp_errmsg = (insert_errmsg ? insert_errmsg :
+		  parse_errmsg ? parse_errmsg :
+		  recognized_mnemonic ?
+		  _("unrecognized form of instruction") :
+		  _("unrecognized instruction"));
+
+    if (strlen (start) > 50)
+      /* xgettext:c-format */
+      sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+    else 
+      /* xgettext:c-format */
+      sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+#else
+    if (strlen (start) > 50)
+      /* xgettext:c-format */
+      sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+    else 
+      /* xgettext:c-format */
+      sprintf (errbuf, _("bad instruction `%.50s'"), start);
+#endif
+      
+    *errmsg = errbuf;
+    return NULL;
+  }
+}
diff --git a/opcodes/arc-desc.c b/opcodes/arc-desc.c
new file mode 100644
index 0000000..006b6eb
--- /dev/null
+++ b/opcodes/arc-desc.c
@@ -0,0 +1,4057 @@
+/* CPU data for arc.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "arc-desc.h"
+#include "arc-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+#include "xregex.h"
+
+/* Attributes.  */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+  { "#f", 0 },
+  { "#t", 1 },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
+{
+  { "base", MACH_BASE },
+  { "a5", MACH_A5 },
+  { "arc600", MACH_ARC600 },
+  { "arc700", MACH_ARC700 },
+  { "max", MACH_MAX },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
+{
+  { "ARCompact", ISA_ARCOMPACT },
+  { "max", ISA_MAX },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY LIMM_attr[] ATTRIBUTE_UNUSED =
+{
+  { "none", LIMM_NONE },
+  { "h", LIMM_H },
+  { "B", LIMM_B },
+  { "BC", LIMM_BC },
+  { "C", LIMM_C },
+  { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE arc_cgen_ifield_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "RESERVED", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { "SIGNED", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE arc_cgen_hardware_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "PC", &bool_attr[0], &bool_attr[0] },
+  { "PROFILE", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE arc_cgen_operand_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { "SIGNED", &bool_attr[0], &bool_attr[0] },
+  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE arc_cgen_insn_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "LIMM", & LIMM_attr[0], & LIMM_attr[0] },
+  { "ALIAS", &bool_attr[0], &bool_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
+  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+  { "PBB", &bool_attr[0], &bool_attr[0] },
+  { "SHORT_P", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+/* Instruction set variants.  */
+
+static const CGEN_ISA arc_cgen_isa_table[] = {
+  { "ARCompact", 32, 32, 32, 32 },
+  { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants.  */
+
+static const CGEN_MACH arc_cgen_mach_table[] = {
+  { "a5", "A5", MACH_A5, 16 },
+  { "arc600", "ARC600", MACH_ARC600, 16 },
+  { "arc700", "ARC700", MACH_ARC700, 16 },
+  { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_cr_names_entries[] =
+{
+  { "gp", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "fp", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "blink", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "mlo", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "mmid", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "mhi", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "lp_count", 60, {0, {{{0, 0}}}}, 0, 0 },
+  { "pcl", 63, {0, {{{0, 0}}}}, 0, 0 },
+  { "ilink1", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "ilink2", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "r32", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "r33", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "r34", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "r35", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "r36", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "r37", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "r38", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "r39", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "r40", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "r41", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "r42", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "r43", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "r44", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "r45", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "r46", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "r47", 47, {0, {{{0, 0}}}}, 0, 0 },
+  { "r48", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "r49", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "r50", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "r51", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "r52", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "r53", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "r54", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "r55", 55, {0, {{{0, 0}}}}, 0, 0 },
+  { "r56", 56, {0, {{{0, 0}}}}, 0, 0 },
+  { "r57", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "r58", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "r59", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "r60", 60, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_cr_names =
+{
+  & arc_cgen_opval_cr_names_entries[0],
+  72,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Qcondb_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "ra", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "al", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "eq", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "z", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "ne", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "nz", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "pl", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "p", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "mi", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "n", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "cs", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "c", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "lo", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "nc", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "hs", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "vs", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "v", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "vc", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "nv", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "gt", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "lt", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "le", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "hi", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "ls", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "pnz", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_Qcondb =
+{
+  & arc_cgen_opval_h_Qcondb_entries[0],
+  28,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Qcondj_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "al", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "eq", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "z", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "ne", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "nz", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "pl", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "p", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "mi", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "n", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "cs", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "c", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "lo", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "nc", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "hs", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "vs", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "v", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "vc", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "nv", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "gt", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "ge", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "lt", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "le", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "hi", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "ls", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "pnz", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_Qcondj =
+{
+  & arc_cgen_opval_h_Qcondj_entries[0],
+  27,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Qcondi_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { ".al", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { ".eq", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { ".z", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { ".ne", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { ".nz", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { ".pl", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { ".p", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { ".mi", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { ".n", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { ".cs", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { ".c", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { ".lo", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { ".cc", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { ".nc", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { ".hs", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { ".vs", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { ".v", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { ".vc", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { ".nv", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { ".gt", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { ".ge", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { ".lt", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { ".le", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { ".hi", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { ".ls", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { ".pnz", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_Qcondi =
+{
+  & arc_cgen_opval_h_Qcondi_entries[0],
+  27,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_uncondb_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "al", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "ra", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_uncondb =
+{
+  & arc_cgen_opval_h_uncondb_entries[0],
+  3,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_uncondj_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "al", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_uncondj =
+{
+  & arc_cgen_opval_h_uncondj_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_uncondi_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { ".al", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_uncondi =
+{
+  & arc_cgen_opval_h_uncondi_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_i2cond_entries[] =
+{
+  { "COND2_", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND2_al", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND2_ra", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND2_eq", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND2_z", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND2_ne", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND2_nz", 2, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_i2cond =
+{
+  & arc_cgen_opval_h_i2cond_entries[0],
+  7,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_i3cond_entries[] =
+{
+  { "COND3_gt", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_ge", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_lt", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_le", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_hi", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_cc", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_nc", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_hs", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_cs", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_c", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_lo", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "COND3_ls", 7, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_i3cond =
+{
+  & arc_cgen_opval_h_i3cond_entries[0],
+  12,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_delay_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { ".d", 1, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_delay =
+{
+  & arc_cgen_opval_h_delay_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_uflags_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { ".f", 1, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_uflags =
+{
+  & arc_cgen_opval_h_uflags_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_nil_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_nil =
+{
+  & arc_cgen_opval_h_nil_entries[0],
+  1,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_auflags_entries[] =
+{
+  { "", 1, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_auflags =
+{
+  & arc_cgen_opval_h_auflags_entries[0],
+  1,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_aufflags_entries[] =
+{
+  { ".f", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "", 1, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_aufflags =
+{
+  & arc_cgen_opval_h_aufflags_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Di_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { ".di", 1, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_Di =
+{
+  & arc_cgen_opval_h_Di_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_insn16_entries[] =
+{
+  { "_s", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_insn16 =
+{
+  & arc_cgen_opval_h_insn16_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_insn32_entries[] =
+{
+  { "", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "_l", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_insn32 =
+{
+  & arc_cgen_opval_h_insn32_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h__aw_entries[] =
+{
+  { ".a", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { ".aw", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h__aw =
+{
+  & arc_cgen_opval_h__aw_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_cr16_entries[] =
+{
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 7, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_cr16 =
+{
+  & arc_cgen_opval_h_cr16_entries[0],
+  8,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_r0_entries[] =
+{
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_r0 =
+{
+  & arc_cgen_opval_h_r0_entries[0],
+  1,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_gp_entries[] =
+{
+  { "r26", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "gp", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_gp =
+{
+  & arc_cgen_opval_h_gp_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_sp_entries[] =
+{
+  { "sp", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r28", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_sp =
+{
+  & arc_cgen_opval_h_sp_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_pcl_entries[] =
+{
+  { "pcl", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r63", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_pcl =
+{
+  & arc_cgen_opval_h_pcl_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_noilink_entries[] =
+{
+  { "gp", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "fp", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "blink", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "mlo", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "mmid", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "mhi", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "lp_count", 60, {0, {{{0, 0}}}}, 0, 0 },
+  { "pcl", 63, {0, {{{0, 0}}}}, 0, 0 },
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
+  { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
+  { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
+  { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
+  { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "r32", 32, {0, {{{0, 0}}}}, 0, 0 },
+  { "r33", 33, {0, {{{0, 0}}}}, 0, 0 },
+  { "r34", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "r35", 35, {0, {{{0, 0}}}}, 0, 0 },
+  { "r36", 36, {0, {{{0, 0}}}}, 0, 0 },
+  { "r37", 37, {0, {{{0, 0}}}}, 0, 0 },
+  { "r38", 38, {0, {{{0, 0}}}}, 0, 0 },
+  { "r39", 39, {0, {{{0, 0}}}}, 0, 0 },
+  { "r40", 40, {0, {{{0, 0}}}}, 0, 0 },
+  { "r41", 41, {0, {{{0, 0}}}}, 0, 0 },
+  { "r42", 42, {0, {{{0, 0}}}}, 0, 0 },
+  { "r43", 43, {0, {{{0, 0}}}}, 0, 0 },
+  { "r44", 44, {0, {{{0, 0}}}}, 0, 0 },
+  { "r45", 45, {0, {{{0, 0}}}}, 0, 0 },
+  { "r46", 46, {0, {{{0, 0}}}}, 0, 0 },
+  { "r47", 47, {0, {{{0, 0}}}}, 0, 0 },
+  { "r48", 48, {0, {{{0, 0}}}}, 0, 0 },
+  { "r49", 49, {0, {{{0, 0}}}}, 0, 0 },
+  { "r50", 50, {0, {{{0, 0}}}}, 0, 0 },
+  { "r51", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "r52", 52, {0, {{{0, 0}}}}, 0, 0 },
+  { "r53", 53, {0, {{{0, 0}}}}, 0, 0 },
+  { "r54", 54, {0, {{{0, 0}}}}, 0, 0 },
+  { "r55", 55, {0, {{{0, 0}}}}, 0, 0 },
+  { "r56", 56, {0, {{{0, 0}}}}, 0, 0 },
+  { "r57", 57, {0, {{{0, 0}}}}, 0, 0 },
+  { "r58", 58, {0, {{{0, 0}}}}, 0, 0 },
+  { "r59", 59, {0, {{{0, 0}}}}, 0, 0 },
+  { "r60", 60, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_noilink =
+{
+  & arc_cgen_opval_h_noilink_entries[0],
+  68,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_ilinkx_entries[] =
+{
+  { "ilink1", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "ilink2", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_ilinkx =
+{
+  & arc_cgen_opval_h_ilinkx_entries[0],
+  4,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_r31_entries[] =
+{
+  { "blink", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r31", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_r31 =
+{
+  & arc_cgen_opval_h_r31_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_status32_entries[] =
+{
+  { "status32", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_status32 =
+{
+  & arc_cgen_opval_h_status32_entries[0],
+  1,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_ne_entries[] =
+{
+  { "ne", 0, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_ne =
+{
+  & arc_cgen_opval_h_ne_entries[0],
+  1,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_RccS_entries[] =
+{
+  { "eq", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "ne", 1, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_RccS =
+{
+  & arc_cgen_opval_h_RccS_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY arc_cgen_opval_h_Rcc_entries[] =
+{
+  { "req", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "rne", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "rlt", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "rge", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "rlo", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "rhs", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "bit0", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "bit1", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD arc_cgen_opval_h_Rcc =
+{
+  & arc_cgen_opval_h_Rcc_entries[0],
+  8,
+  0, 0, 0, 0, ""
+};
+
+
+/* The hardware table.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_HW_##a)
+#else
+#define A(a) (1 << CGEN_HW_/**/a)
+#endif
+
+const CGEN_HW_ENTRY arc_cgen_hw_table[] =
+{
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-lbit", HW_H_LBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-e1", HW_H_E1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-e2", HW_H_E2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-s1bit", HW_H_S1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-s2bit", HW_H_S2BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-Qcondb", HW_H_QCONDB, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Qcondb, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-Qcondj", HW_H_QCONDJ, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Qcondj, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-Qcondi", HW_H_QCONDI, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Qcondi, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uncondb", HW_H_UNCONDB, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_uncondb, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uncondj", HW_H_UNCONDJ, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_uncondj, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uncondi", HW_H_UNCONDI, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_uncondi, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-i2cond", HW_H_I2COND, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_i2cond, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-i3cond", HW_H_I3COND, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_i3cond, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-delay", HW_H_DELAY, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_delay, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uflags", HW_H_UFLAGS, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_uflags, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-nil", HW_H_NIL, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_nil, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-auflags", HW_H_AUFLAGS, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_auflags, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-aufflags", HW_H_AUFFLAGS, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_aufflags, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-Di", HW_H_DI, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Di, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-insn16", HW_H_INSN16, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_insn16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-insn32", HW_H_INSN32, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_insn32, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-_aw", HW_H__AW, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h__aw, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cr16", HW_H_CR16, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_cr16, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_r0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gp", HW_H_GP, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_gp, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sp", HW_H_SP, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_sp, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pcl", HW_H_PCL, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_pcl, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-noilink", HW_H_NOILINK, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_noilink, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ilinkx", HW_H_ILINKX, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_ilinkx, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-r31", HW_H_R31, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_r31, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-auxr", HW_H_AUXR, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-status32", HW_H_STATUS32, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_status32, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-timer-expire", HW_H_TIMER_EXPIRE, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-prof-offset", HW_H_PROF_OFFSET, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ne", HW_H_NE, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_ne, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-RccS", HW_H_RCCS, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_RccS, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-Rcc", HW_H_RCC, CGEN_ASM_KEYWORD, (PTR) & arc_cgen_opval_h_Rcc, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+/* The instruction field table.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_IFLD_##a)
+#else
+#define A(a) (1 << CGEN_IFLD_/**/a)
+#endif
+
+const CGEN_IFLD arc_cgen_ifld_table[] =
+{
+  { ARC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_COND_Q, "f-cond-Q", 0, 32, 27, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_COND_I2, "f-cond-i2", 0, 32, 5, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_COND_I3, "f-cond-i3", 0, 32, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_BRCOND, "f-brcond", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_OP__A, "f-op--a", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_OP__B, "f-op--b", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_OP__C, "f-op--c", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_B_5_3, "f-B-5-3", 0, 32, 17, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_OP_B, "f-op-B", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_OP_C, "f-op-C", 0, 32, 20, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_OP_CJ, "f-op-Cj", 0, 32, 20, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_H_2_0, "f-h-2-0", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_H_5_3, "f-h-5-3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_OP_H, "f-op-h", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_U6, "f-u6", 0, 32, 20, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_U6X2, "f-u6x2", 0, 32, 20, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_DELAY_N, "f-delay-N", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_RES27, "f-res27", 0, 32, 27, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_F, "f-F", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_CBRANCH_IMM, "f-cbranch-imm", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_OP_A, "f-op-A", 0, 32, 26, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_S12H, "f-s12h", 0, 32, 26, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_S12, "f-s12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_S12X2, "f-s12x2", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_REL10, "f-rel10", 0, 32, 7, 9, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_REL7, "f-rel7", 0, 32, 10, 6, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_REL8, "f-rel8", 0, 32, 9, 7, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_REL13BL, "f-rel13bl", 0, 32, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_D21L, "f-d21l", 0, 32, 5, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_D21BL, "f-d21bl", 0, 32, 5, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_D21H, "f-d21h", 0, 32, 16, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_D25M, "f-d25m", 0, 32, 16, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_D25H, "f-d25h", 0, 32, 28, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_REL21, "f-rel21", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_REL21BL, "f-rel21bl", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_REL25, "f-rel25", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_REL25BL, "f-rel25bl", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_D9L, "f-d9l", 0, 32, 8, 7, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_D9H, "f-d9h", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_REL9, "f-rel9", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_U3, "f-u3", 0, 32, 13, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_U5, "f-u5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_U7, "f-u7", 0, 32, 9, 7, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_U8, "f-u8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_S9, "f-s9", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_U5X2, "f-u5x2", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_U5X4, "f-u5x4", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_U8X4, "f-u8x4", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_S9X1, "f-s9x1", 0, 32, 7, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_S9X2, "f-s9x2", 0, 32, 7, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_S9X4, "f-s9x4", 0, 32, 7, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_DUMMY, "f-dummy", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_OPM, "f-opm", 0, 32, 0, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_GO_TYPE, "f-go-type", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_GO_CC_TYPE, "f-go-cc-type", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_GO_OP, "f-go-op", 0, 32, 10, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_I16_43, "f-i16-43", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_I16_GO, "f-i16-go", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_I16_GP_TYPE, "f-i16-gp-type", 0, 32, 5, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_I16ADDCMPU7_TYPE, "f-i16addcmpu7-type", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_BUF, "f-buf", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_BR, "f-br", 0, 32, 27, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_BLUF, "f-bluf", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_BRSCOND, "f-brscond", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_LDOZZX, "f-ldozzx", 0, 32, 23, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_LDR6ZZX, "f-ldr6zzx", 0, 32, 10, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_STOZZR, "f-stozzr", 0, 32, 29, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_LDOAA, "f-ldoaa", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_LDRAA, "f-ldraa", 0, 32, 8, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_STOAA, "f-stoaa", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_LDODI, "f-LDODi", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_LDRDI, "f-LDRDi", 0, 32, 16, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_STODI, "f-STODi", 0, 32, 26, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { ARC_F_TRAPNUM, "f-trapnum", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD ARC_F_OP_B_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD ARC_F_OP_H_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD ARC_F_S12_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD ARC_F_S12X2_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL21_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL21BL_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL25_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL25BL_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL9_MULTI_IFIELD [];
+const CGEN_MAYBE_MULTI_IFLD ARC_F_S9_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD ARC_F_OP_B_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP__B] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_B_5_3] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD ARC_F_OP_H_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_H_2_0] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_H_5_3] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD ARC_F_S12_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U6] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S12H] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD ARC_F_S12X2_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U6] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S12H] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL21_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21L] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21H] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL21BL_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21BL] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21H] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL25_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21L] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D25M] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D25H] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL25BL_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D21BL] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D25M] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D25H] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD ARC_F_REL9_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D9L] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D9H] } },
+    { 0, { (const PTR) 0 } }
+};
+const CGEN_MAYBE_MULTI_IFLD ARC_F_S9_MULTI_IFIELD [] =
+{
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U8] } },
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_D9H] } },
+    { 0, { (const PTR) 0 } }
+};
+
+/* The operand table.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_OPERAND_##a)
+#else
+#define A(a) (1 << CGEN_OPERAND_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) ARC_OPERAND_##op
+#else
+#define OPERAND(op) ARC_OPERAND_/**/op
+#endif
+
+const CGEN_OPERAND arc_cgen_operand_table[] =
+{
+/* pc: program counter */
+  { "pc", ARC_OPERAND_PC, HW_H_PC, 0, 0,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_NIL] } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* lbit: loop inhibit bit */
+  { "lbit", ARC_OPERAND_LBIT, HW_H_LBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* zbit: zero bit */
+  { "zbit", ARC_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* nbit: negative bit */
+  { "nbit", ARC_OPERAND_NBIT, HW_H_NBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* cbit: carry bit */
+  { "cbit", ARC_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* vbit: overflow bit */
+  { "vbit", ARC_OPERAND_VBIT, HW_H_VBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* s1bit: channel 1 saturate */
+  { "s1bit", ARC_OPERAND_S1BIT, HW_H_S1BIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* s2bit: channel 2 saturate */
+  { "s2bit", ARC_OPERAND_S2BIT, HW_H_S2BIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* Qcondb: Condition */
+  { "Qcondb", ARC_OPERAND_QCONDB, HW_H_QCONDB, 27, 5,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_Q] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* Qcondj: Condition */
+  { "Qcondj", ARC_OPERAND_QCONDJ, HW_H_QCONDJ, 27, 5,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_Q] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* Qcondi: Condition */
+  { "Qcondi", ARC_OPERAND_QCONDI, HW_H_QCONDI, 27, 5,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_Q] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* uncondb: unconditional branch */
+  { "uncondb", ARC_OPERAND_UNCONDB, HW_H_UNCONDB, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* uncondj: unconditional jump */
+  { "uncondj", ARC_OPERAND_UNCONDJ, HW_H_UNCONDJ, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* uncondi: unconditional insn */
+  { "uncondi", ARC_OPERAND_UNCONDI, HW_H_UNCONDI, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* i2cond: Condition */
+  { "i2cond", ARC_OPERAND_I2COND, HW_H_I2COND, 5, 2,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_I2] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* i3cond: Condition */
+  { "i3cond", ARC_OPERAND_I3COND, HW_H_I3COND, 7, 3,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_COND_I3] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* delay_N: Delay slot exposed */
+  { "delay_N", ARC_OPERAND_DELAY_N, HW_H_DELAY, 26, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_DELAY_N] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* _S: 16 bit opcode */
+  { "_S", ARC_OPERAND__S, HW_H_INSN16, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* _L: 32 bit opcode */
+  { "_L", ARC_OPERAND__L, HW_H_INSN32, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* F: update flags */
+  { "F", ARC_OPERAND_F, HW_H_UFLAGS, 16, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* F1: always update flags */
+  { "F1", ARC_OPERAND_F1, HW_H_AUFLAGS, 16, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* F1F: always update flags; .F allowed */
+  { "F1F", ARC_OPERAND_F1F, HW_H_AUFFLAGS, 16, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* F0: never update flags */
+  { "F0", ARC_OPERAND_F0, HW_H_NIL, 16, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* R_a: Core Register a */
+  { "R_a", ARC_OPERAND_R_A, HW_H_CR16, 13, 3,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP__A] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* RA: Core Register A */
+  { "RA", ARC_OPERAND_RA, HW_H_CR, 26, 6,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_A] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* R_b: Core Register b */
+  { "R_b", ARC_OPERAND_R_B, HW_H_CR16, 5, 3,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP__B] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* RB: Core Register B */
+  { "RB", ARC_OPERAND_RB, HW_H_CR, 5, 6,
+    { 2, { (const PTR) &ARC_F_OP_B_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* R_c: Core Register b */
+  { "R_c", ARC_OPERAND_R_C, HW_H_CR16, 8, 3,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP__C] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* RC: Core Register C */
+  { "RC", ARC_OPERAND_RC, HW_H_CR, 20, 6,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_C] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* Rh: Core register h */
+  { "Rh", ARC_OPERAND_RH, HW_H_CR, 8, 6,
+    { 2, { (const PTR) &ARC_F_OP_H_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* R0: Core Register 0 */
+  { "R0", ARC_OPERAND_R0, HW_H_R0, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* R31: Core Register 31 */
+  { "R31", ARC_OPERAND_R31, HW_H_R31, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* GP: Global Pointer */
+  { "GP", ARC_OPERAND_GP, HW_H_GP, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* SP: Stack Pointer */
+  { "SP", ARC_OPERAND_SP, HW_H_SP, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* PCL: read PC - aligned */
+  { "PCL", ARC_OPERAND_PCL, HW_H_PCL, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* RA_0: encode A as 0 */
+  { "RA_0", ARC_OPERAND_RA_0, HW_H_NIL, 26, 6,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_A] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* RB_0: encode B as 0 */
+  { "RB_0", ARC_OPERAND_RB_0, HW_H_NIL, 5, 6,
+    { 2, { (const PTR) &ARC_F_OP_B_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* RC_ilink: inlink[01] as op C */
+  { "RC_ilink", ARC_OPERAND_RC_ILINK, HW_H_ILINKX, 20, 6,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_CJ] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* RC_noilink: Core reg C, not ilink */
+  { "RC_noilink", ARC_OPERAND_RC_NOILINK, HW_H_NOILINK, 20, 6,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_OP_CJ] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* NE: NE condition  */
+  { "NE", ARC_OPERAND_NE, HW_H_NE, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* U6: 6 bit unsigned immediate */
+  { "U6", ARC_OPERAND_U6, HW_H_UINT, 20, 6,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U6] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* U6x2: 6 bit unsigned immediate */
+  { "U6x2", ARC_OPERAND_U6X2, HW_H_UINT, 20, 6,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U6X2] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* u3: 3 bit unsigned immediate */
+  { "u3", ARC_OPERAND_U3, HW_H_UINT, 13, 3,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U3] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* u5: 5 bit unsigned immediate */
+  { "u5", ARC_OPERAND_U5, HW_H_UINT, 11, 5,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* u7: 7 bit unsigned immediate */
+  { "u7", ARC_OPERAND_U7, HW_H_UINT, 9, 7,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U7] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* u8: 8 bit unsigned immediate */
+  { "u8", ARC_OPERAND_U8, HW_H_UINT, 8, 8,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* s9: 8 bit signed immediate */
+  { "s9", ARC_OPERAND_S9, HW_H_SINT, 8, 9,
+    { 2, { (const PTR) &ARC_F_S9_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* s12: 12 bit signed immediate */
+  { "s12", ARC_OPERAND_S12, HW_H_SINT, 20, 12,
+    { 2, { (const PTR) &ARC_F_S12_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* s12x2: 12 bit signed immediate */
+  { "s12x2", ARC_OPERAND_S12X2, HW_H_SINT, 20, 12,
+    { 2, { (const PTR) &ARC_F_S12X2_MULTI_IFIELD[0] } }, 
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* u5x4: 5 bit uns imm times 4 */
+  { "u5x4", ARC_OPERAND_U5X4, HW_H_UINT, 11, 5,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5X4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sc_u5_: 5 bit uns imm times 4 */
+  { "sc_u5_", ARC_OPERAND_SC_U5_, HW_H_UINT, 11, 5,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5X4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sc_u5w: 5 bit uns imm times 2 */
+  { "sc_u5w", ARC_OPERAND_SC_U5W, HW_H_UINT, 11, 5,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5X2] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sc_u5b: 5 bit uns imm times 1 */
+  { "sc_u5b", ARC_OPERAND_SC_U5B, HW_H_UINT, 11, 5,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U5] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* u8x4: 8 bit uns imm times 4 */
+  { "u8x4", ARC_OPERAND_U8X4, HW_H_UINT, 8, 8,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_U8X4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* s9x4: 9 bit sgn imm times 4 */
+  { "s9x4", ARC_OPERAND_S9X4, HW_H_UINT, 7, 9,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S9X4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sc_s9_: 8 bit uns imm times 4 */
+  { "sc_s9_", ARC_OPERAND_SC_S9_, HW_H_UINT, 7, 9,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S9X4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sc_s9w: 8 bit uns imm times 2 */
+  { "sc_s9w", ARC_OPERAND_SC_S9W, HW_H_UINT, 7, 9,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S9X2] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sc_s9b: 8 bit uns imm times 1 */
+  { "sc_s9b", ARC_OPERAND_SC_S9B, HW_H_UINT, 7, 9,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_S9X1] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* label7: 7 bit pc relative address */
+  { "label7", ARC_OPERAND_LABEL7, HW_H_IADDR, 10, 6,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_REL7] } }, 
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* label8: 8 bit pc relative address */
+  { "label8", ARC_OPERAND_LABEL8, HW_H_IADDR, 9, 7,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_REL8] } }, 
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* label9: 9 bit pc relative address */
+  { "label9", ARC_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
+    { 2, { (const PTR) &ARC_F_REL9_MULTI_IFIELD[0] } }, 
+    { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* label10: 10 bit pc relative address */
+  { "label10", ARC_OPERAND_LABEL10, HW_H_IADDR, 7, 9,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_REL10] } }, 
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* label13a: 13 bit bl pc rel address */
+  { "label13a", ARC_OPERAND_LABEL13A, HW_H_IADDR, 5, 11,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_REL13BL] } }, 
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* label21: 21 bit pc relative address */
+  { "label21", ARC_OPERAND_LABEL21, HW_H_IADDR, 5, 20,
+    { 2, { (const PTR) &ARC_F_REL21_MULTI_IFIELD[0] } }, 
+    { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* label21a: 21 bit bl pc rel address */
+  { "label21a", ARC_OPERAND_LABEL21A, HW_H_IADDR, 5, 19,
+    { 2, { (const PTR) &ARC_F_REL21BL_MULTI_IFIELD[0] } }, 
+    { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* label25: 25 bit pc relative address */
+  { "label25", ARC_OPERAND_LABEL25, HW_H_IADDR, 5, 24,
+    { 3, { (const PTR) &ARC_F_REL25_MULTI_IFIELD[0] } }, 
+    { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* label25a: 25 bit bl pc rel address */
+  { "label25a", ARC_OPERAND_LABEL25A, HW_H_IADDR, 5, 23,
+    { 3, { (const PTR) &ARC_F_REL25BL_MULTI_IFIELD[0] } }, 
+    { 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
+/* dummy-op: (first 16 bit of) next insn */
+  { "dummy-op", ARC_OPERAND_DUMMY_OP, HW_H_UINT, 16, 16,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_DUMMY] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* RccS: BRcc_s */
+  { "RccS", ARC_OPERAND_RCCS, HW_H_RCCS, 8, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_BRSCOND] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* Rcc: BRcc / BBIT Condition */
+  { "Rcc", ARC_OPERAND_RCC, HW_H_RCC, 28, 4,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_BRCOND] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* LDODi: ld /w offs Direct mem access */
+  { "LDODi", ARC_OPERAND_LDODI, HW_H_DI, 20, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_LDODI] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* LDRDi: ld reg-reg Direct mem access */
+  { "LDRDi", ARC_OPERAND_LDRDI, HW_H_DI, 16, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_LDRDI] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* STODi: ld w/ offs Direct mem access */
+  { "STODi", ARC_OPERAND_STODI, HW_H_DI, 26, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_STODI] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* EXDi: ex Direct memory access */
+  { "EXDi", ARC_OPERAND_EXDI, HW_H_DI, 16, 1,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_F] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* _AW: .AW suffix */
+  { "_AW", ARC_OPERAND__AW, HW_H__AW, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* trapnum: 6 bit trap number */
+  { "trapnum", ARC_OPERAND_TRAPNUM, HW_H_UINT, 5, 6,
+    { 0, { (const PTR) &arc_cgen_ifld_table[ARC_F_TRAPNUM] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sentinel */
+  { 0, 0, 0, 0, 0,
+    { 0, { (const PTR) 0 } },
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+/* The instruction table.  */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+
+static const CGEN_IBASE arc_cgen_insn_table[MAX_INSNS] =
+{
+  /* Special null first entry.
+     A `num' value of zero is thus invalid.
+     Also, the special `invalid' insn resides here.  */
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } } },
+/* b$i2cond $label10 */
+  {
+    ARC_INSN_B_S, "b_s", "b", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* b$i3cond$_S $label7 */
+  {
+    ARC_INSN_BCC_S, "bcc_s", "b", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* br$RccS$_S $R_b,0,$label8 */
+  {
+    ARC_INSN_BRCC_S, "brcc_s", "br", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* b$Qcondb$_L $label21 */
+  {
+    ARC_INSN_BCC_L, "bcc_l", "b", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* b$Qcondb$_L.d $label21 */
+  {
+    ARC_INSN_BCC_L_D, "bcc_l.d", "b", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* b$uncondb$_L $label25 */
+  {
+    ARC_INSN_B_L, "b_l", "b", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* b$uncondb$_L.d $label25 */
+  {
+    ARC_INSN_B_L_D, "b_l.d", "b", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* b$Rcc $RB,$RC,$label9 */
+  {
+    ARC_INSN_BRCC_RC, "brcc_RC", "b", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* b$Rcc.d $RB,$RC,$label9 */
+  {
+    ARC_INSN_BRCC_RC_D, "brcc_RC.d", "b", 32,
+    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* b$Rcc $RB,$U6,$label9 */
+  {
+    ARC_INSN_BRCC_U6, "brcc_U6", "b", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* b$Rcc.d $RB,$U6,$label9 */
+  {
+    ARC_INSN_BRCC_U6_D, "brcc_U6.d", "b", 32,
+    { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* bl$uncondj$_S $label13a */
+  {
+    ARC_INSN_BL_S, "bl_s", "bl", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* bl$Qcondj$_L $label21 */
+  {
+    ARC_INSN_BLCC, "blcc", "bl", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* bl$Qcondj$_L.d $label21 */
+  {
+    ARC_INSN_BLCC_D, "blcc.d", "bl", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* bl$uncondj$_L $label25a */
+  {
+    ARC_INSN_BL, "bl", "bl", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* bl$uncondj$_L.d $label25a */
+  {
+    ARC_INSN_BL_D, "bl.d", "bl", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ld$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LD_ABS, "ld_abs", "ld", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ld$_AW$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LD__AW_ABS, "ld$_AW_abs", "ld", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ld.ab$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LD_AB_ABS, "ld.ab_abs", "ld.ab", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ld.as$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LD_AS_ABS, "ld.as_abs", "ld.as", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ld$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LD_ABC, "ld_abc", "ld", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ld$_AW$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LD__AW_ABC, "ld$_AW_abc", "ld", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ld.ab$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LD_AB_ABC, "ld.ab_abc", "ld.ab", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ld.as$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LD_AS_ABC, "ld.as_abc", "ld.as", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ld$_S $R_a,[$R_b,$R_c] */
+  {
+    ARC_INSN_LD_S_ABC, "ld_s_abc", "ld", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ld$_S $R_c,[$R_b,$sc_u5_] */
+  {
+    ARC_INSN_LD_S_ABU, "ld_s_abu", "ld", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ld$_S $R_b,[$SP,$u5x4] */
+  {
+    ARC_INSN_LD_S_ABSP, "ld_s_absp", "ld", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ld$_S $R_b,[$GP,$sc_s9_] */
+  {
+    ARC_INSN_LD_S_GPREL, "ld_s_gprel", "ld", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ld$_S $R_b,[$PCL,$u8x4] */
+  {
+    ARC_INSN_LD_S_PCREL, "ld_s_pcrel", "ld", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ldb$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDB_ABS, "ldb_abs", "ldb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldb$_AW$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDB__AW_ABS, "ldb$_AW_abs", "ldb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldb.ab$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDB_AB_ABS, "ldb.ab_abs", "ldb.ab", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldb.as$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDB_AS_ABS, "ldb.as_abs", "ldb.as", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldb$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDB_ABC, "ldb_abc", "ldb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldb$_AW$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDB__AW_ABC, "ldb$_AW_abc", "ldb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldb.ab$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDB_AB_ABC, "ldb.ab_abc", "ldb.ab", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldb.as$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDB_AS_ABC, "ldb.as_abc", "ldb.as", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldb$_S $R_a,[$R_b,$R_c] */
+  {
+    ARC_INSN_LDB_S_ABC, "ldb_s_abc", "ldb", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ldb$_S $R_c,[$R_b,$sc_u5b] */
+  {
+    ARC_INSN_LDB_S_ABU, "ldb_s_abu", "ldb", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ldb$_S $R_b,[$SP,$u5x4] */
+  {
+    ARC_INSN_LDB_S_ABSP, "ldb_s_absp", "ldb", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ldb$_S $R_b,[$GP,$sc_s9b] */
+  {
+    ARC_INSN_LDB_S_GPREL, "ldb_s_gprel", "ldb", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ldb.x$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDB_X_ABS, "ldb.x_abs", "ldb.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldb$_AW.x$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDB__AW_X_ABS, "ldb$_AW.x_abs", "ldb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldb.ab.x$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDB_AB_X_ABS, "ldb.ab.x_abs", "ldb.ab.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldb.as.x$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDB_AS_X_ABS, "ldb.as.x_abs", "ldb.as.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldb.x$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDB_X_ABC, "ldb.x_abc", "ldb.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldb$_AW.x$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDB__AW_X_ABC, "ldb$_AW.x_abc", "ldb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldb.ab.x$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDB_AB_X_ABC, "ldb.ab.x_abc", "ldb.ab.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldb.as.x$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDB_AS_X_ABC, "ldb.as.x_abc", "ldb.as.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldw$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDW_ABS, "ldw_abs", "ldw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldw$_AW$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDW__AW_ABS, "ldw$_AW_abs", "ldw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldw.ab$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDW_AB_ABS, "ldw.ab_abs", "ldw.ab", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldw.as$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDW_AS_ABS, "ldw.as_abs", "ldw.as", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldw$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDW_ABC, "ldw_abc", "ldw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldw$_AW$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDW__AW_ABC, "ldw$_AW_abc", "ldw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldw.ab$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDW_AB_ABC, "ldw.ab_abc", "ldw.ab", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldw.as$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDW_AS_ABC, "ldw.as_abc", "ldw.as", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldw$_S $R_a,[$R_b,$R_c] */
+  {
+    ARC_INSN_LDW_S_ABC, "ldw_s_abc", "ldw", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ldw$_S $R_c,[$R_b,$sc_u5w] */
+  {
+    ARC_INSN_LDW_S_ABU, "ldw_s_abu", "ldw", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ldw$_S $R_b,[$GP,$sc_s9w] */
+  {
+    ARC_INSN_LDW_S_GPREL, "ldw_s_gprel", "ldw", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ldw.x$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDW_X_ABS, "ldw.x_abs", "ldw.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldw$_AW.x$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDW__AW_X_ABS, "ldw$_AW.x_abs", "ldw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldw.ab.x$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDW_AB_X_ABS, "ldw.ab.x_abs", "ldw.ab.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldw.as.x$LDODi $RA,[$RB,$s9] */
+  {
+    ARC_INSN_LDW_AS_X_ABS, "ldw.as.x_abs", "ldw.as.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ldw.x$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDW_X_ABC, "ldw.x_abc", "ldw.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldw$_AW.x$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDW__AW_X_ABC, "ldw$_AW.x_abc", "ldw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldw.ab.x$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDW_AB_X_ABC, "ldw.ab.x_abc", "ldw.ab.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldw.as.x$LDRDi $RA,[$RB,$RC] */
+  {
+    ARC_INSN_LDW_AS_X_ABC, "ldw.as.x_abc", "ldw.as.x", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ldw$_S.x $R_c,[$R_b,$sc_u5w] */
+  {
+    ARC_INSN_LDW_S_X_ABU, "ldw_s.x_abu", "ldw", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* st$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_ST_ABS, "st_abs", "st", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* st$_AW$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_ST__AW_ABS, "st$_AW_abs", "st", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* st.ab$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_ST_AB_ABS, "st.ab_abs", "st.ab", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* st.as$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_ST_AS_ABS, "st.as_abs", "st.as", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* st$_S $R_c,[$R_b,$sc_u5_] */
+  {
+    ARC_INSN_ST_S_ABU, "st_s_abu", "st", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* st$_S $R_b,[$SP,$u5x4] */
+  {
+    ARC_INSN_ST_S_ABSP, "st_s_absp", "st", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* stb$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_STB_ABS, "stb_abs", "stb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* stb$_AW$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_STB__AW_ABS, "stb$_AW_abs", "stb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* stb.ab$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_STB_AB_ABS, "stb.ab_abs", "stb.ab", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* stb.as$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_STB_AS_ABS, "stb.as_abs", "stb.as", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* stb$_S $R_c,[$R_b,$sc_u5b] */
+  {
+    ARC_INSN_STB_S_ABU, "stb_s_abu", "stb", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* stb$_S $R_b,[$SP,$u5x4] */
+  {
+    ARC_INSN_STB_S_ABSP, "stb_s_absp", "stb", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* stw$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_STW_ABS, "stw_abs", "stw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* stw$_AW$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_STW__AW_ABS, "stw$_AW_abs", "stw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* stw.ab$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_STW_AB_ABS, "stw.ab_abs", "stw.ab", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* stw.as$STODi $RC,[$RB,$s9] */
+  {
+    ARC_INSN_STW_AS_ABS, "stw.as_abs", "stw.as", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* stw$_S $R_c,[$R_b,$sc_u5w] */
+  {
+    ARC_INSN_STW_S_ABU, "stw_s_abu", "stw", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* add$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ADD_L_S12__RA_, "add_L_s12 $RA,", "add", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ADD_CCU6__RA_, "add_ccu6 $RA,", "add", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ADD_L_U6__RA_, "add_L_u6 $RA,", "add", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ADD_L_R_R__RA__RC, "add_L_r_r $RA,$RC", "add", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* add$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ADD_CC__RA__RC, "add_cc $RA,$RC", "add", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* add$_S $R_a,$R_b,$R_c */
+  {
+    ARC_INSN_ADD_S_ABC, "add_s_abc", "add", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* add$_S $R_c,$R_b,$u3 */
+  {
+    ARC_INSN_ADD_S_CBU3, "add_s_cbu3", "add", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* add$_S $R_b,$R_b,$Rh */
+  {
+    ARC_INSN_ADD_S_MCAH, "add_s_mcah", "add", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_H, 0 } } } }
+  },
+/* add$_S $R_b,$SP,$u5x4 */
+  {
+    ARC_INSN_ADD_S_ABSP, "add_s_absp", "add", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* add$_S $SP,$SP,$u5x4 */
+  {
+    ARC_INSN_ADD_S_ASSPSP, "add_s_asspsp", "add", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* add$_S $R0,$GP,$s9x4 */
+  {
+    ARC_INSN_ADD_S_GP, "add_s_gp", "add", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* add$_S $R_b,$R_b,$u7 */
+  {
+    ARC_INSN_ADD_S_R_U7, "add_s_r_u7", "add", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* adc$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ADC_L_S12__RA_, "adc_L_s12 $RA,", "adc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* adc$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ADC_CCU6__RA_, "adc_ccu6 $RA,", "adc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* adc$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ADC_L_U6__RA_, "adc_L_u6 $RA,", "adc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* adc$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ADC_L_R_R__RA__RC, "adc_L_r_r $RA,$RC", "adc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* adc$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ADC_CC__RA__RC, "adc_cc $RA,$RC", "adc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sub$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_SUB_L_S12__RA_, "sub_L_s12 $RA,", "sub", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_SUB_CCU6__RA_, "sub_ccu6 $RA,", "sub", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_SUB_L_U6__RA_, "sub_L_u6 $RA,", "sub", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_SUB_L_R_R__RA__RC, "sub_L_r_r $RA,$RC", "sub", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sub$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_SUB_CC__RA__RC, "sub_cc $RA,$RC", "sub", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sub$_S $R_c,$R_b,$u3 */
+  {
+    ARC_INSN_SUB_S_CBU3, "sub_s_cbu3", "sub", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* sub$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_SUB_S_GO, "I16_GO_SUB_s_go", "sub", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* sub$_S $NE$R_b,$R_b,$R_b */
+  {
+    ARC_INSN_SUB_S_GO_SUB_NE, "sub_s_go_sub_ne", "sub", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* sub$_S $R_b,$R_b,$u5 */
+  {
+    ARC_INSN_SUB_S_SSB, "sub_s_ssb", "sub", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* sub$_S $SP,$SP,$u5x4 */
+  {
+    ARC_INSN_SUB_S_ASSPSP, "sub_s_asspsp", "sub", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* sbc$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_SBC_L_S12__RA_, "sbc_L_s12 $RA,", "sbc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sbc$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_SBC_CCU6__RA_, "sbc_ccu6 $RA,", "sbc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sbc$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_SBC_L_U6__RA_, "sbc_L_u6 $RA,", "sbc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sbc$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_SBC_L_R_R__RA__RC, "sbc_L_r_r $RA,$RC", "sbc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sbc$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_SBC_CC__RA__RC, "sbc_cc $RA,$RC", "sbc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* and$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_AND_L_S12__RA_, "and_L_s12 $RA,", "and", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* and$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_AND_CCU6__RA_, "and_ccu6 $RA,", "and", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* and$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_AND_L_U6__RA_, "and_L_u6 $RA,", "and", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* and$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_AND_L_R_R__RA__RC, "and_L_r_r $RA,$RC", "and", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* and$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_AND_CC__RA__RC, "and_cc $RA,$RC", "and", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* and$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_AND_S_GO, "I16_GO_AND_s_go", "and", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* or$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_OR_L_S12__RA_, "or_L_s12 $RA,", "or", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* or$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_OR_CCU6__RA_, "or_ccu6 $RA,", "or", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* or$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_OR_L_U6__RA_, "or_L_u6 $RA,", "or", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* or$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_OR_L_R_R__RA__RC, "or_L_r_r $RA,$RC", "or", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* or$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_OR_CC__RA__RC, "or_cc $RA,$RC", "or", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* or$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_OR_S_GO, "I16_GO_OR_s_go", "or", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* bic$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_BIC_L_S12__RA_, "bic_L_s12 $RA,", "bic", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bic$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_BIC_CCU6__RA_, "bic_ccu6 $RA,", "bic", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bic$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_BIC_L_U6__RA_, "bic_L_u6 $RA,", "bic", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bic$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_BIC_L_R_R__RA__RC, "bic_L_r_r $RA,$RC", "bic", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bic$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_BIC_CC__RA__RC, "bic_cc $RA,$RC", "bic", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bic$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_BIC_S_GO, "I16_GO_BIC_s_go", "bic", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* xor$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_XOR_L_S12__RA_, "xor_L_s12 $RA,", "xor", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* xor$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_XOR_CCU6__RA_, "xor_ccu6 $RA,", "xor", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* xor$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_XOR_L_U6__RA_, "xor_L_u6 $RA,", "xor", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* xor$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_XOR_L_R_R__RA__RC, "xor_L_r_r $RA,$RC", "xor", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* xor$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_XOR_CC__RA__RC, "xor_cc $RA,$RC", "xor", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* xor$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_XOR_S_GO, "I16_GO_XOR_s_go", "xor", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* max$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MAX_L_S12__RA_, "max_L_s12 $RA,", "max", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* max$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MAX_CCU6__RA_, "max_ccu6 $RA,", "max", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* max$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MAX_L_U6__RA_, "max_L_u6 $RA,", "max", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* max$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MAX_L_R_R__RA__RC, "max_L_r_r $RA,$RC", "max", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* max$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MAX_CC__RA__RC, "max_cc $RA,$RC", "max", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* min$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MIN_L_S12__RA_, "min_L_s12 $RA,", "min", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* min$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MIN_CCU6__RA_, "min_ccu6 $RA,", "min", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* min$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MIN_L_U6__RA_, "min_L_u6 $RA,", "min", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* min$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MIN_L_R_R__RA__RC, "min_L_r_r $RA,$RC", "min", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* min$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MIN_CC__RA__RC, "min_cc $RA,$RC", "min", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mov$_L$F $RB,$s12 */
+  {
+    ARC_INSN_MOV_L_S12_, "mov_L_s12 ", "mov", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* mov$Qcondi$F $RB,$U6 */
+  {
+    ARC_INSN_MOV_CCU6_, "mov_ccu6 ", "mov", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* mov$_L$F $RB,$U6 */
+  {
+    ARC_INSN_MOV_L_U6_, "mov_L_u6 ", "mov", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* mov$_L$F $RB,$RC */
+  {
+    ARC_INSN_MOV_L_R_R__RC, "mov_L_r_r $RC", "mov", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* mov$Qcondi$F $RB,$RC */
+  {
+    ARC_INSN_MOV_CC__RC, "mov_cc $RC", "mov", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* mov$_S $R_b,$Rh */
+  {
+    ARC_INSN_MOV_S_MCAH, "mov_s_mcah", "mov", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_H, 0 } } } }
+  },
+/* mov$_S $Rh,$R_b */
+  {
+    ARC_INSN_MOV_S_MCAHB, "mov_s_mcahb", "mov", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* mov$_S $R_b,$u7 */
+  {
+    ARC_INSN_MOV_S_R_U7, "mov_s_r_u7", "mov", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* tst$_L$F1 $RB,$s12 */
+  {
+    ARC_INSN_TST_L_S12_, "tst_L_s12 ", "tst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* tst$Qcondi$F1 $RB,$U6 */
+  {
+    ARC_INSN_TST_CCU6_, "tst_ccu6 ", "tst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* tst$_L$F1 $RB,$U6 */
+  {
+    ARC_INSN_TST_L_U6_, "tst_L_u6 ", "tst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* tst$_L$F1 $RB,$RC */
+  {
+    ARC_INSN_TST_L_R_R__RC, "tst_L_r_r $RC", "tst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* tst$Qcondi$F1 $RB,$RC */
+  {
+    ARC_INSN_TST_CC__RC, "tst_cc $RC", "tst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* tst$_S $R_b,$R_c */
+  {
+    ARC_INSN_TST_S_GO, "tst_s_go", "tst", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* cmp$_L$F1 $RB,$s12 */
+  {
+    ARC_INSN_CMP_L_S12_, "cmp_L_s12 ", "cmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* cmp$Qcondi$F1 $RB,$U6 */
+  {
+    ARC_INSN_CMP_CCU6_, "cmp_ccu6 ", "cmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* cmp$_L$F1 $RB,$U6 */
+  {
+    ARC_INSN_CMP_L_U6_, "cmp_L_u6 ", "cmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* cmp$_L$F1 $RB,$RC */
+  {
+    ARC_INSN_CMP_L_R_R__RC, "cmp_L_r_r $RC", "cmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* cmp$Qcondi$F1 $RB,$RC */
+  {
+    ARC_INSN_CMP_CC__RC, "cmp_cc $RC", "cmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* cmp$_S $R_b,$Rh */
+  {
+    ARC_INSN_CMP_S_MCAH, "cmp_s_mcah", "cmp", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_H, 0 } } } }
+  },
+/* cmp$_S $R_b,$u7 */
+  {
+    ARC_INSN_CMP_S_R_U7, "cmp_s_r_u7", "cmp", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* rcmp$_L$F1 $RB,$s12 */
+  {
+    ARC_INSN_RCMP_L_S12_, "rcmp_L_s12 ", "rcmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* rcmp$Qcondi$F1 $RB,$U6 */
+  {
+    ARC_INSN_RCMP_CCU6_, "rcmp_ccu6 ", "rcmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* rcmp$_L$F1 $RB,$U6 */
+  {
+    ARC_INSN_RCMP_L_U6_, "rcmp_L_u6 ", "rcmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* rcmp$_L$F1 $RB,$RC */
+  {
+    ARC_INSN_RCMP_L_R_R__RC, "rcmp_L_r_r $RC", "rcmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* rcmp$Qcondi$F1 $RB,$RC */
+  {
+    ARC_INSN_RCMP_CC__RC, "rcmp_cc $RC", "rcmp", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* rsub$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_RSUB_L_S12__RA_, "rsub_L_s12 $RA,", "rsub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* rsub$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_RSUB_CCU6__RA_, "rsub_ccu6 $RA,", "rsub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* rsub$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_RSUB_L_U6__RA_, "rsub_L_u6 $RA,", "rsub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* rsub$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_RSUB_L_R_R__RA__RC, "rsub_L_r_r $RA,$RC", "rsub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* rsub$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_RSUB_CC__RA__RC, "rsub_cc $RA,$RC", "rsub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bset$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_BSET_L_S12__RA_, "bset_L_s12 $RA,", "bset", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bset$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_BSET_CCU6__RA_, "bset_ccu6 $RA,", "bset", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bset$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_BSET_L_U6__RA_, "bset_L_u6 $RA,", "bset", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bset$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_BSET_L_R_R__RA__RC, "bset_L_r_r $RA,$RC", "bset", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bset$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_BSET_CC__RA__RC, "bset_cc $RA,$RC", "bset", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bset$_S $R_b,$R_b,$u5 */
+  {
+    ARC_INSN_BSET_S_SSB, "bset_s_ssb", "bset", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* bclr$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_BCLR_L_S12__RA_, "bclr_L_s12 $RA,", "bclr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bclr$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_BCLR_CCU6__RA_, "bclr_ccu6 $RA,", "bclr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bclr$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_BCLR_L_U6__RA_, "bclr_L_u6 $RA,", "bclr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bclr$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_BCLR_L_R_R__RA__RC, "bclr_L_r_r $RA,$RC", "bclr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bclr$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_BCLR_CC__RA__RC, "bclr_cc $RA,$RC", "bclr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bclr$_S $R_b,$R_b,$u5 */
+  {
+    ARC_INSN_BCLR_S_SSB, "bclr_s_ssb", "bclr", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* btst$_L$F1 $RB,$s12 */
+  {
+    ARC_INSN_BTST_L_S12_, "btst_L_s12 ", "btst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* btst$Qcondi$F1 $RB,$U6 */
+  {
+    ARC_INSN_BTST_CCU6_, "btst_ccu6 ", "btst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* btst$_L$F1 $RB,$U6 */
+  {
+    ARC_INSN_BTST_L_U6_, "btst_L_u6 ", "btst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* btst$_L$F1 $RB,$RC */
+  {
+    ARC_INSN_BTST_L_R_R__RC, "btst_L_r_r $RC", "btst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* btst$Qcondi$F1 $RB,$RC */
+  {
+    ARC_INSN_BTST_CC__RC, "btst_cc $RC", "btst", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* btst$_S $R_b,$u5 */
+  {
+    ARC_INSN_BTST_S_SSB, "btst_s_ssb", "btst", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* bxor$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_BXOR_L_S12__RA_, "bxor_L_s12 $RA,", "bxor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bxor$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_BXOR_CCU6__RA_, "bxor_ccu6 $RA,", "bxor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bxor$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_BXOR_L_U6__RA_, "bxor_L_u6 $RA,", "bxor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bxor$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_BXOR_L_R_R__RA__RC, "bxor_L_r_r $RA,$RC", "bxor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bxor$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_BXOR_CC__RA__RC, "bxor_cc $RA,$RC", "bxor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bmsk$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_BMSK_L_S12__RA_, "bmsk_L_s12 $RA,", "bmsk", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bmsk$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_BMSK_CCU6__RA_, "bmsk_ccu6 $RA,", "bmsk", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bmsk$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_BMSK_L_U6__RA_, "bmsk_L_u6 $RA,", "bmsk", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* bmsk$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_BMSK_L_R_R__RA__RC, "bmsk_L_r_r $RA,$RC", "bmsk", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bmsk$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_BMSK_CC__RA__RC, "bmsk_cc $RA,$RC", "bmsk", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* bmsk$_S $R_b,$R_b,$u5 */
+  {
+    ARC_INSN_BMSK_S_SSB, "bmsk_s_ssb", "bmsk", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* add1$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ADD1_L_S12__RA_, "add1_L_s12 $RA,", "add1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add1$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ADD1_CCU6__RA_, "add1_ccu6 $RA,", "add1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add1$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ADD1_L_U6__RA_, "add1_L_u6 $RA,", "add1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add1$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ADD1_L_R_R__RA__RC, "add1_L_r_r $RA,$RC", "add1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* add1$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ADD1_CC__RA__RC, "add1_cc $RA,$RC", "add1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* add1$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_ADD1_S_GO, "I16_GO_ADD1_s_go", "add1", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* add2$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ADD2_L_S12__RA_, "add2_L_s12 $RA,", "add2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add2$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ADD2_CCU6__RA_, "add2_ccu6 $RA,", "add2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add2$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ADD2_L_U6__RA_, "add2_L_u6 $RA,", "add2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add2$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ADD2_L_R_R__RA__RC, "add2_L_r_r $RA,$RC", "add2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* add2$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ADD2_CC__RA__RC, "add2_cc $RA,$RC", "add2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* add2$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_ADD2_S_GO, "I16_GO_ADD2_s_go", "add2", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* add3$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ADD3_L_S12__RA_, "add3_L_s12 $RA,", "add3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add3$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ADD3_CCU6__RA_, "add3_ccu6 $RA,", "add3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add3$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ADD3_L_U6__RA_, "add3_L_u6 $RA,", "add3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* add3$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ADD3_L_R_R__RA__RC, "add3_L_r_r $RA,$RC", "add3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* add3$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ADD3_CC__RA__RC, "add3_cc $RA,$RC", "add3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* add3$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_ADD3_S_GO, "I16_GO_ADD3_s_go", "add3", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* sub1$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_SUB1_L_S12__RA_, "sub1_L_s12 $RA,", "sub1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub1$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_SUB1_CCU6__RA_, "sub1_ccu6 $RA,", "sub1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub1$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_SUB1_L_U6__RA_, "sub1_L_u6 $RA,", "sub1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub1$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_SUB1_L_R_R__RA__RC, "sub1_L_r_r $RA,$RC", "sub1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sub1$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_SUB1_CC__RA__RC, "sub1_cc $RA,$RC", "sub1", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sub2$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_SUB2_L_S12__RA_, "sub2_L_s12 $RA,", "sub2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub2$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_SUB2_CCU6__RA_, "sub2_ccu6 $RA,", "sub2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub2$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_SUB2_L_U6__RA_, "sub2_L_u6 $RA,", "sub2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub2$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_SUB2_L_R_R__RA__RC, "sub2_L_r_r $RA,$RC", "sub2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sub2$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_SUB2_CC__RA__RC, "sub2_cc $RA,$RC", "sub2", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sub3$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_SUB3_L_S12__RA_, "sub3_L_s12 $RA,", "sub3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub3$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_SUB3_CCU6__RA_, "sub3_ccu6 $RA,", "sub3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub3$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_SUB3_L_U6__RA_, "sub3_L_u6 $RA,", "sub3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sub3$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_SUB3_L_R_R__RA__RC, "sub3_L_r_r $RA,$RC", "sub3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sub3$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_SUB3_CC__RA__RC, "sub3_cc $RA,$RC", "sub3", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mpy$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MPY_L_S12__RA_, "mpy_L_s12 $RA,", "mpy", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpy$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MPY_CCU6__RA_, "mpy_ccu6 $RA,", "mpy", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpy$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MPY_L_U6__RA_, "mpy_L_u6 $RA,", "mpy", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpy$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MPY_L_R_R__RA__RC, "mpy_L_r_r $RA,$RC", "mpy", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mpy$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MPY_CC__RA__RC, "mpy_cc $RA,$RC", "mpy", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mpyh$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MPYH_L_S12__RA_, "mpyh_L_s12 $RA,", "mpyh", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpyh$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MPYH_CCU6__RA_, "mpyh_ccu6 $RA,", "mpyh", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpyh$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MPYH_L_U6__RA_, "mpyh_L_u6 $RA,", "mpyh", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpyh$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MPYH_L_R_R__RA__RC, "mpyh_L_r_r $RA,$RC", "mpyh", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mpyh$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MPYH_CC__RA__RC, "mpyh_cc $RA,$RC", "mpyh", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mpyhu$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MPYHU_L_S12__RA_, "mpyhu_L_s12 $RA,", "mpyhu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpyhu$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MPYHU_CCU6__RA_, "mpyhu_ccu6 $RA,", "mpyhu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpyhu$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MPYHU_L_U6__RA_, "mpyhu_L_u6 $RA,", "mpyhu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpyhu$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MPYHU_L_R_R__RA__RC, "mpyhu_L_r_r $RA,$RC", "mpyhu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mpyhu$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MPYHU_CC__RA__RC, "mpyhu_cc $RA,$RC", "mpyhu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mpyu$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MPYU_L_S12__RA_, "mpyu_L_s12 $RA,", "mpyu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpyu$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MPYU_CCU6__RA_, "mpyu_ccu6 $RA,", "mpyu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpyu$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MPYU_L_U6__RA_, "mpyu_L_u6 $RA,", "mpyu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mpyu$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MPYU_L_R_R__RA__RC, "mpyu_L_r_r $RA,$RC", "mpyu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mpyu$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MPYU_CC__RA__RC, "mpyu_cc $RA,$RC", "mpyu", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* j$_L$F0 [$RC_noilink] */
+  {
+    ARC_INSN_J_L_R_R___RC_NOILINK_, "j_L_r_r [$RC_noilink]", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* j$Qcondi$F0 [$RC_noilink] */
+  {
+    ARC_INSN_J_CC___RC_NOILINK_, "j_cc [$RC_noilink]", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* j$_L$F1F [$RC_ilink] */
+  {
+    ARC_INSN_J_L_R_R___RC_ILINK_, "j_L_r_r [$RC_ilink]", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* j$Qcondi$F1F [$RC_ilink] */
+  {
+    ARC_INSN_J_CC___RC_ILINK_, "j_cc [$RC_ilink]", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* j$_L$F0 $s12 */
+  {
+    ARC_INSN_J_L_S12_, "j_L_s12 ", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* j$Qcondi$F0 $U6 */
+  {
+    ARC_INSN_J_CCU6_, "j_ccu6 ", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* j$_L$F0 $U6 */
+  {
+    ARC_INSN_J_L_U6_, "j_L_u6 ", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* j$_S [$R_b] */
+  {
+    ARC_INSN_J_S, "j_s", "j", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* j$_S [$R31] */
+  {
+    ARC_INSN_J_S__S, "j_s$_S", "j", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* jeq$_S [$R31] */
+  {
+    ARC_INSN_J_SEQ__S, "j_seq$_S", "jeq", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* jne$_S [$R31] */
+  {
+    ARC_INSN_J_SNE__S, "j_sne$_S", "jne", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* j$_L$F0.d $s12 */
+  {
+    ARC_INSN_J_L_S12_D_, "j_L_s12.d ", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* j$Qcondi$F0.d $U6 */
+  {
+    ARC_INSN_J_CCU6_D_, "j_ccu6.d ", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* j$_L$F0.d $U6 */
+  {
+    ARC_INSN_J_L_U6_D_, "j_L_u6.d ", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* j$_L$F0.d [$RC] */
+  {
+    ARC_INSN_J_L_R_R_D___RC_, "j_L_r_r.d [$RC]", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* j$Qcondi$F0.d [$RC] */
+  {
+    ARC_INSN_J_CC_D___RC_, "j_cc.d [$RC]", "j", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* j$_S.d [$R_b] */
+  {
+    ARC_INSN_J_S_D, "j_s.d", "j", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* j$_S.d [$R31] */
+  {
+    ARC_INSN_J_S__S_D, "j_s$_S.d", "j", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* jl$_L$F0 $s12 */
+  {
+    ARC_INSN_JL_L_S12_, "jl_L_s12 ", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* jl$Qcondi$F0 $U6 */
+  {
+    ARC_INSN_JL_CCU6_, "jl_ccu6 ", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* jl$_L$F0 $U6 */
+  {
+    ARC_INSN_JL_L_U6_, "jl_L_u6 ", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* jl$_S [$R_b] */
+  {
+    ARC_INSN_JL_S, "jl_s", "jl", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* jl$_L$F0 [$RC_noilink] */
+  {
+    ARC_INSN_JL_L_R_R___RC_NOILINK_, "jl_L_r_r [$RC_noilink]", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* jl$Qcondi$F0 [$RC_noilink] */
+  {
+    ARC_INSN_JL_CC___RC_NOILINK_, "jl_cc [$RC_noilink]", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* jl$_L$F0.d $s12 */
+  {
+    ARC_INSN_JL_L_S12_D_, "jl_L_s12.d ", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* jl$Qcondi$F0.d $U6 */
+  {
+    ARC_INSN_JL_CCU6_D_, "jl_ccu6.d ", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* jl$_L$F0.d $U6 */
+  {
+    ARC_INSN_JL_L_U6_D_, "jl_L_u6.d ", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* jl$_L$F0.d [$RC] */
+  {
+    ARC_INSN_JL_L_R_R_D___RC_, "jl_L_r_r.d [$RC]", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* jl$Qcondi$F0.d [$RC] */
+  {
+    ARC_INSN_JL_CC_D___RC_, "jl_cc.d [$RC]", "jl", 32,
+    { 0|A(RELAXED)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* jl$_S.d [$R_b] */
+  {
+    ARC_INSN_JL_S_D, "jl_s.d", "jl", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* lp$_L$F0 $s12x2 */
+  {
+    ARC_INSN_LP_L_S12_, "lp_L_s12 ", "lp", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* lp$Qcondi$F0 $U6x2 */
+  {
+    ARC_INSN_LPCC_CCU6, "lpcc_ccu6", "lp", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* flag$_L$F0 $s12 */
+  {
+    ARC_INSN_FLAG_L_S12_, "flag_L_s12 ", "flag", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* flag$Qcondi$F0 $U6 */
+  {
+    ARC_INSN_FLAG_CCU6_, "flag_ccu6 ", "flag", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* flag$_L$F0 $U6 */
+  {
+    ARC_INSN_FLAG_L_U6_, "flag_L_u6 ", "flag", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* flag$_L$F0 $RC */
+  {
+    ARC_INSN_FLAG_L_R_R__RC, "flag_L_r_r $RC", "flag", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* flag$Qcondi$F0 $RC */
+  {
+    ARC_INSN_FLAG_CC__RC, "flag_cc $RC", "flag", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* lr$_L$F0 $RB,[$RC] */
+  {
+    ARC_INSN_LR_L_R_R___RC_, "lr_L_r_r [$RC]", "lr", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* lr$_L$F0 $RB,[$s12] */
+  {
+    ARC_INSN_LR_L_S12_, "lr_L_s12 ", "lr", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* lr$_L$F0 $RB,[$U6] */
+  {
+    ARC_INSN_LR_L_U6_, "lr_L_u6 ", "lr", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sr$_L$F0 $RB,[$RC] */
+  {
+    ARC_INSN_SR_L_R_R___RC_, "sr_L_r_r [$RC]", "sr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* sr$_L$F0 $RB,[$s12] */
+  {
+    ARC_INSN_SR_L_S12_, "sr_L_s12 ", "sr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sr$_L$F0 $RB,[$U6] */
+  {
+    ARC_INSN_SR_L_U6_, "sr_L_u6 ", "sr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asl$_L$F $RB,$RC */
+  {
+    ARC_INSN_ASL_L_R_R__RC, "asl_L_r_r $RC", "asl", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* asl$_L$F $RB,$U6 */
+  {
+    ARC_INSN_ASL_L_U6_, "asl_L_u6 ", "asl", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asl$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_ASL_S_GO, "I16_GO_ASL_s_go", "asl", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* asr$_L$F $RB,$RC */
+  {
+    ARC_INSN_ASR_L_R_R__RC, "asr_L_r_r $RC", "asr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* asr$_L$F $RB,$U6 */
+  {
+    ARC_INSN_ASR_L_U6_, "asr_L_u6 ", "asr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asr$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_ASR_S_GO, "I16_GO_ASR_s_go", "asr", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* lsr$_L$F $RB,$RC */
+  {
+    ARC_INSN_LSR_L_R_R__RC, "lsr_L_r_r $RC", "lsr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* lsr$_L$F $RB,$U6 */
+  {
+    ARC_INSN_LSR_L_U6_, "lsr_L_u6 ", "lsr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* lsr$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_LSR_S_GO, "I16_GO_LSR_s_go", "lsr", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ror$_L$F $RB,$RC */
+  {
+    ARC_INSN_ROR_L_R_R__RC, "ror_L_r_r $RC", "ror", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* ror$_L$F $RB,$U6 */
+  {
+    ARC_INSN_ROR_L_U6_, "ror_L_u6 ", "ror", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* rrc$_L$F $RB,$RC */
+  {
+    ARC_INSN_RRC_L_R_R__RC, "rrc_L_r_r $RC", "rrc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* rrc$_L$F $RB,$U6 */
+  {
+    ARC_INSN_RRC_L_U6_, "rrc_L_u6 ", "rrc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sexb$_L$F $RB,$RC */
+  {
+    ARC_INSN_SEXB_L_R_R__RC, "sexb_L_r_r $RC", "sexb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* sexb$_L$F $RB,$U6 */
+  {
+    ARC_INSN_SEXB_L_U6_, "sexb_L_u6 ", "sexb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sexb$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_SEXB_S_GO, "I16_GO_SEXB_s_go", "sexb", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* sexw$_L$F $RB,$RC */
+  {
+    ARC_INSN_SEXW_L_R_R__RC, "sexw_L_r_r $RC", "sexw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* sexw$_L$F $RB,$U6 */
+  {
+    ARC_INSN_SEXW_L_U6_, "sexw_L_u6 ", "sexw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* sexw$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_SEXW_S_GO, "I16_GO_SEXW_s_go", "sexw", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* extb$_L$F $RB,$RC */
+  {
+    ARC_INSN_EXTB_L_R_R__RC, "extb_L_r_r $RC", "extb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* extb$_L$F $RB,$U6 */
+  {
+    ARC_INSN_EXTB_L_U6_, "extb_L_u6 ", "extb", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* extb$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_EXTB_S_GO, "I16_GO_EXTB_s_go", "extb", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* extw$_L$F $RB,$RC */
+  {
+    ARC_INSN_EXTW_L_R_R__RC, "extw_L_r_r $RC", "extw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* extw$_L$F $RB,$U6 */
+  {
+    ARC_INSN_EXTW_L_U6_, "extw_L_u6 ", "extw", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* extw$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_EXTW_S_GO, "I16_GO_EXTW_s_go", "extw", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* abs$_L$F $RB,$RC */
+  {
+    ARC_INSN_ABS_L_R_R__RC, "abs_L_r_r $RC", "abs", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* abs$_L$F $RB,$U6 */
+  {
+    ARC_INSN_ABS_L_U6_, "abs_L_u6 ", "abs", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* abs$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_ABS_S_GO, "I16_GO_ABS_s_go", "abs", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* not$_L$F $RB,$RC */
+  {
+    ARC_INSN_NOT_L_R_R__RC, "not_L_r_r $RC", "not", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* not$_L$F $RB,$U6 */
+  {
+    ARC_INSN_NOT_L_U6_, "not_L_u6 ", "not", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* not$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_NOT_S_GO, "I16_GO_NOT_s_go", "not", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* rlc$_L$F $RB,$RC */
+  {
+    ARC_INSN_RLC_L_R_R__RC, "rlc_L_r_r $RC", "rlc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* rlc$_L$F $RB,$U6 */
+  {
+    ARC_INSN_RLC_L_U6_, "rlc_L_u6 ", "rlc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ex$_L$EXDi $RB,$RC */
+  {
+    ARC_INSN_EX_L_R_R__RC, "ex_L_r_r $RC", "ex", 32,
+    { 0, { { { (1<<MACH_ARC700), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ex$_L$EXDi $RB,$U6 */
+  {
+    ARC_INSN_EX_L_U6_, "ex_L_u6 ", "ex", 32,
+    { 0, { { { (1<<MACH_ARC700), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* neg$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_NEG_S_GO, "I16_GO_NEG_s_go", "neg", 32,
+    { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* swi */
+  {
+    ARC_INSN_SWI, "swi", "swi", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* trap$_S $trapnum */
+  {
+    ARC_INSN_TRAP_S, "trap_s", "trap", 32,
+    { 0|A(SHORT_P)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* brk */
+  {
+    ARC_INSN_BRK, "brk", "brk", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* brk_s */
+  {
+    ARC_INSN_BRK_S, "brk_s", "brk_s", 32,
+    { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* asl$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ASL_L_S12__RA_, "asl_L_s12 $RA,", "asl", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asl$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ASL_CCU6__RA_, "asl_ccu6 $RA,", "asl", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asl$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ASL_L_U6__RA_, "asl_L_u6 $RA,", "asl", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asl$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ASL_L_R_R__RA__RC, "asl_L_r_r $RA,$RC", "asl", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* asl$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ASL_CC__RA__RC, "asl_cc $RA,$RC", "asl", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* asl$_S $R_c,$R_b,$u3 */
+  {
+    ARC_INSN_ASL_S_CBU3, "asl_s_cbu3", "asl", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* asl$_S $R_b,$R_b,$u5 */
+  {
+    ARC_INSN_ASL_S_SSB, "asl_s_ssb", "asl", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* asl$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_ASLM_S_GO, "I16_GO_ASLM_s_go", "asl", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* lsr$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_LSR_L_S12__RA_, "lsr_L_s12 $RA,", "lsr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* lsr$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_LSR_CCU6__RA_, "lsr_ccu6 $RA,", "lsr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* lsr$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_LSR_L_U6__RA_, "lsr_L_u6 $RA,", "lsr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* lsr$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_LSR_L_R_R__RA__RC, "lsr_L_r_r $RA,$RC", "lsr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* lsr$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_LSR_CC__RA__RC, "lsr_cc $RA,$RC", "lsr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* lsr$_S $R_b,$R_b,$u5 */
+  {
+    ARC_INSN_LSR_S_SSB, "lsr_s_ssb", "lsr", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* lsr$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_LSRM_S_GO, "I16_GO_LSRM_s_go", "lsr", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* asr$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ASR_L_S12__RA_, "asr_L_s12 $RA,", "asr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asr$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ASR_CCU6__RA_, "asr_ccu6 $RA,", "asr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asr$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ASR_L_U6__RA_, "asr_L_u6 $RA,", "asr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asr$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ASR_L_R_R__RA__RC, "asr_L_r_r $RA,$RC", "asr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* asr$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ASR_CC__RA__RC, "asr_cc $RA,$RC", "asr", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* asr$_S $R_c,$R_b,$u3 */
+  {
+    ARC_INSN_ASR_S_CBU3, "asr_s_cbu3", "asr", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* asr$_S $R_b,$R_b,$u5 */
+  {
+    ARC_INSN_ASR_S_SSB, "asr_s_ssb", "asr", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* asr$_S $R_b,$R_b,$R_c */
+  {
+    ARC_INSN_I16_GO_ASRM_S_GO, "I16_GO_ASRM_s_go", "asr", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* ror$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ROR_L_S12__RA_, "ror_L_s12 $RA,", "ror", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ror$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ROR_CCU6__RA_, "ror_ccu6 $RA,", "ror", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ror$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ROR_L_U6__RA_, "ror_L_u6 $RA,", "ror", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* ror$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ROR_L_R_R__RA__RC, "ror_L_r_r $RA,$RC", "ror", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* ror$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ROR_CC__RA__RC, "ror_cc $RA,$RC", "ror", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mul64$_L$F1 $RB,$s12 */
+  {
+    ARC_INSN_MUL64_L_S12_, "mul64_L_s12 ", "mul64", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mul64$Qcondi$F1 $RB,$U6 */
+  {
+    ARC_INSN_MUL64_CCU6_, "mul64_ccu6 ", "mul64", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mul64$_L$F1 $RB,$U6 */
+  {
+    ARC_INSN_MUL64_L_U6_, "mul64_L_u6 ", "mul64", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mul64$_L$F1 $RB,$RC */
+  {
+    ARC_INSN_MUL64_L_R_R__RC, "mul64_L_r_r $RC", "mul64", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mul64$Qcondi$F1 $RB,$RC */
+  {
+    ARC_INSN_MUL64_CC__RC, "mul64_cc $RC", "mul64", 32,
+    { 0|A(RELAXED), { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mul64$_S $R_b,$R_c */
+  {
+    ARC_INSN_MUL64_S_GO, "mul64_s_go", "mul64", 32,
+    { 0|A(SHORT_P)|A(RELAXABLE), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* mulu64$_L$F1 $RB,$s12 */
+  {
+    ARC_INSN_MULU64_L_S12_, "mulu64_L_s12 ", "mulu64", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mulu64$Qcondi$F1 $RB,$U6 */
+  {
+    ARC_INSN_MULU64_CCU6_, "mulu64_ccu6 ", "mulu64", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mulu64$_L$F1 $RB,$U6 */
+  {
+    ARC_INSN_MULU64_L_U6_, "mulu64_L_u6 ", "mulu64", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mulu64$_L$F1 $RB,$RC */
+  {
+    ARC_INSN_MULU64_L_R_R__RC, "mulu64_L_r_r $RC", "mulu64", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mulu64$Qcondi$F1 $RB,$RC */
+  {
+    ARC_INSN_MULU64_CC__RC, "mulu64_cc $RC", "mulu64", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* adds$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ADDS_L_S12__RA_, "adds_L_s12 $RA,", "adds", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* adds$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ADDS_CCU6__RA_, "adds_ccu6 $RA,", "adds", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* adds$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ADDS_L_U6__RA_, "adds_L_u6 $RA,", "adds", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* adds$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ADDS_L_R_R__RA__RC, "adds_L_r_r $RA,$RC", "adds", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* adds$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ADDS_CC__RA__RC, "adds_cc $RA,$RC", "adds", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* subs$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_SUBS_L_S12__RA_, "subs_L_s12 $RA,", "subs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* subs$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_SUBS_CCU6__RA_, "subs_ccu6 $RA,", "subs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* subs$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_SUBS_L_U6__RA_, "subs_L_u6 $RA,", "subs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* subs$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_SUBS_L_R_R__RA__RC, "subs_L_r_r $RA,$RC", "subs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* subs$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_SUBS_CC__RA__RC, "subs_cc $RA,$RC", "subs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* divaw$_L$F0 $RB,$RB,$s12 */
+  {
+    ARC_INSN_DIVAW_L_S12__RA_, "divaw_L_s12 $RA,", "divaw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* divaw$Qcondi$F0 $RB,$RB,$U6 */
+  {
+    ARC_INSN_DIVAW_CCU6__RA_, "divaw_ccu6 $RA,", "divaw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* divaw$_L$F0 $RA,$RB,$U6 */
+  {
+    ARC_INSN_DIVAW_L_U6__RA_, "divaw_L_u6 $RA,", "divaw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* divaw$_L$F0 $RA,$RB,$RC */
+  {
+    ARC_INSN_DIVAW_L_R_R__RA__RC, "divaw_L_r_r $RA,$RC", "divaw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* divaw$Qcondi$F0 $RB,$RB,$RC */
+  {
+    ARC_INSN_DIVAW_CC__RA__RC, "divaw_cc $RA,$RC", "divaw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* asls$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ASLS_L_S12__RA_, "asls_L_s12 $RA,", "asls", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asls$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ASLS_CCU6__RA_, "asls_ccu6 $RA,", "asls", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asls$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ASLS_L_U6__RA_, "asls_L_u6 $RA,", "asls", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asls$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ASLS_L_R_R__RA__RC, "asls_L_r_r $RA,$RC", "asls", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* asls$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ASLS_CC__RA__RC, "asls_cc $RA,$RC", "asls", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* asrs$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ASRS_L_S12__RA_, "asrs_L_s12 $RA,", "asrs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asrs$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ASRS_CCU6__RA_, "asrs_ccu6 $RA,", "asrs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asrs$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ASRS_L_U6__RA_, "asrs_L_u6 $RA,", "asrs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* asrs$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ASRS_L_R_R__RA__RC, "asrs_L_r_r $RA,$RC", "asrs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* asrs$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ASRS_CC__RA__RC, "asrs_cc $RA,$RC", "asrs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* addsdw$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_ADDSDW_L_S12__RA_, "addsdw_L_s12 $RA,", "addsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* addsdw$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_ADDSDW_CCU6__RA_, "addsdw_ccu6 $RA,", "addsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* addsdw$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_ADDSDW_L_U6__RA_, "addsdw_L_u6 $RA,", "addsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* addsdw$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_ADDSDW_L_R_R__RA__RC, "addsdw_L_r_r $RA,$RC", "addsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* addsdw$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_ADDSDW_CC__RA__RC, "addsdw_cc $RA,$RC", "addsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* subsdw$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_SUBSDW_L_S12__RA_, "subsdw_L_s12 $RA,", "subsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* subsdw$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_SUBSDW_CCU6__RA_, "subsdw_ccu6 $RA,", "subsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* subsdw$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_SUBSDW_L_U6__RA_, "subsdw_L_u6 $RA,", "subsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* subsdw$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_SUBSDW_L_R_R__RA__RC, "subsdw_L_r_r $RA,$RC", "subsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* subsdw$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_SUBSDW_CC__RA__RC, "subsdw_cc $RA,$RC", "subsdw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* swap$_L$F $RB,$RC */
+  {
+    ARC_INSN_SWAP_L_R_R__RC, "swap_L_r_r $RC", "swap", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* swap$_L$F $RB,$U6 */
+  {
+    ARC_INSN_SWAP_L_U6_, "swap_L_u6 ", "swap", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* norm$_L$F $RB,$RC */
+  {
+    ARC_INSN_NORM_L_R_R__RC, "norm_L_r_r $RC", "norm", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* norm$_L$F $RB,$U6 */
+  {
+    ARC_INSN_NORM_L_U6_, "norm_L_u6 ", "norm", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* rnd16$_L$F $RB,$RC */
+  {
+    ARC_INSN_RND16_L_R_R__RC, "rnd16_L_r_r $RC", "rnd16", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* rnd16$_L$F $RB,$U6 */
+  {
+    ARC_INSN_RND16_L_U6_, "rnd16_L_u6 ", "rnd16", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* abssw$_L$F $RB,$RC */
+  {
+    ARC_INSN_ABSSW_L_R_R__RC, "abssw_L_r_r $RC", "abssw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* abssw$_L$F $RB,$U6 */
+  {
+    ARC_INSN_ABSSW_L_U6_, "abssw_L_u6 ", "abssw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* abss$_L$F $RB,$RC */
+  {
+    ARC_INSN_ABSS_L_R_R__RC, "abss_L_r_r $RC", "abss", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* abss$_L$F $RB,$U6 */
+  {
+    ARC_INSN_ABSS_L_U6_, "abss_L_u6 ", "abss", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* negsw$_L$F $RB,$RC */
+  {
+    ARC_INSN_NEGSW_L_R_R__RC, "negsw_L_r_r $RC", "negsw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* negsw$_L$F $RB,$U6 */
+  {
+    ARC_INSN_NEGSW_L_U6_, "negsw_L_u6 ", "negsw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* negs$_L$F $RB,$RC */
+  {
+    ARC_INSN_NEGS_L_R_R__RC, "negs_L_r_r $RC", "negs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* negs$_L$F $RB,$U6 */
+  {
+    ARC_INSN_NEGS_L_U6_, "negs_L_u6 ", "negs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* normw$_L$F $RB,$RC */
+  {
+    ARC_INSN_NORMW_L_R_R__RC, "normw_L_r_r $RC", "normw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_C, 0 } } } }
+  },
+/* normw$_L$F $RB,$U6 */
+  {
+    ARC_INSN_NORMW_L_U6_, "normw_L_u6 ", "normw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* nop_s */
+  {
+    ARC_INSN_NOP_S, "nop_s", "nop_s", 32,
+    { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* unimp_s */
+  {
+    ARC_INSN_UNIMP_S, "unimp_s", "unimp_s", 32,
+    { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* pop$_S $R_b */
+  {
+    ARC_INSN_POP_S_B, "pop_s_b", "pop", 32,
+    { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* pop$_S $R31 */
+  {
+    ARC_INSN_POP_S_BLINK, "pop_s_blink", "pop", 32,
+    { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* push$_S $R_b */
+  {
+    ARC_INSN_PUSH_S_B, "push_s_b", "push", 32,
+    { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* push$_S $R31 */
+  {
+    ARC_INSN_PUSH_S_BLINK, "push_s_blink", "push", 32,
+    { 0|A(SHORT_P), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/* mullw$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MULLW_L_S12__RA_, "mullw_L_s12 $RA,", "mullw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mullw$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MULLW_CCU6__RA_, "mullw_ccu6 $RA,", "mullw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mullw$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MULLW_L_U6__RA_, "mullw_L_u6 $RA,", "mullw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mullw$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MULLW_L_R_R__RA__RC, "mullw_L_r_r $RA,$RC", "mullw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mullw$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MULLW_CC__RA__RC, "mullw_cc $RA,$RC", "mullw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* maclw$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MACLW_L_S12__RA_, "maclw_L_s12 $RA,", "maclw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* maclw$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MACLW_CCU6__RA_, "maclw_ccu6 $RA,", "maclw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* maclw$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MACLW_L_U6__RA_, "maclw_L_u6 $RA,", "maclw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* maclw$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MACLW_L_R_R__RA__RC, "maclw_L_r_r $RA,$RC", "maclw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* maclw$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MACLW_CC__RA__RC, "maclw_cc $RA,$RC", "maclw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* machlw$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MACHLW_L_S12__RA_, "machlw_L_s12 $RA,", "machlw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* machlw$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MACHLW_CCU6__RA_, "machlw_ccu6 $RA,", "machlw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* machlw$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MACHLW_L_U6__RA_, "machlw_L_u6 $RA,", "machlw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* machlw$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MACHLW_L_R_R__RA__RC, "machlw_L_r_r $RA,$RC", "machlw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* machlw$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MACHLW_CC__RA__RC, "machlw_cc $RA,$RC", "machlw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mululw$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MULULW_L_S12__RA_, "mululw_L_s12 $RA,", "mululw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mululw$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MULULW_CCU6__RA_, "mululw_ccu6 $RA,", "mululw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mululw$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MULULW_L_U6__RA_, "mululw_L_u6 $RA,", "mululw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* mululw$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MULULW_L_R_R__RA__RC, "mululw_L_r_r $RA,$RC", "mululw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* mululw$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MULULW_CC__RA__RC, "mululw_cc $RA,$RC", "mululw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* machulw$_L$F $RB,$RB,$s12 */
+  {
+    ARC_INSN_MACHULW_L_S12__RA_, "machulw_L_s12 $RA,", "machulw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* machulw$Qcondi$F $RB,$RB,$U6 */
+  {
+    ARC_INSN_MACHULW_CCU6__RA_, "machulw_ccu6 $RA,", "machulw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* machulw$_L$F $RA,$RB,$U6 */
+  {
+    ARC_INSN_MACHULW_L_U6__RA_, "machulw_L_u6 $RA,", "machulw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_B, 0 } } } }
+  },
+/* machulw$_L$F $RA,$RB,$RC */
+  {
+    ARC_INSN_MACHULW_L_R_R__RA__RC, "machulw_L_r_r $RA,$RC", "machulw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/* machulw$Qcondi$F $RB,$RB,$RC */
+  {
+    ARC_INSN_MACHULW_CC__RA__RC, "machulw_cc $RA,$RC", "machulw", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { LIMM_BC, 0 } } } }
+  },
+/*  */
+  {
+    ARC_INSN_CURRENT_LOOP_END, "current_loop_end", "", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/*  */
+  {
+    ARC_INSN_CURRENT_LOOP_END_AFTER_BRANCH, "current_loop_end_after_branch", "", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+/*  */
+  {
+    ARC_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH, "arc600_current_loop_end_after_branch", "", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { LIMM_NONE, 0 } } } }
+  },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call.  */
+
+static void
+init_tables (void)
+{
+}
+
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void arc_cgen_rebuild_tables (CGEN_CPU_TABLE *);
+
+/* Subroutine of arc_cgen_cpu_open to look up a mach via its bfd name.  */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
+{
+  while (table->name)
+    {
+      if (strcmp (name, table->bfd_name) == 0)
+	return table;
+      ++table;
+    }
+  abort ();
+}
+
+/* Subroutine of arc_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_hw_table (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  int machs = cd->machs;
+  const CGEN_HW_ENTRY *init = & arc_cgen_hw_table[0];
+  /* MAX_HW is only an upper bound on the number of selected entries.
+     However each entry is indexed by it's enum so there can be holes in
+     the table.  */
+  const CGEN_HW_ENTRY **selected =
+    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+  cd->hw_table.init_entries = init;
+  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+  /* ??? For now we just use machs to determine which ones we want.  */
+  for (i = 0; init[i].name != NULL; ++i)
+    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+	& machs)
+      selected[init[i].type] = &init[i];
+  cd->hw_table.entries = selected;
+  cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of arc_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_ifield_table (CGEN_CPU_TABLE *cd)
+{
+  cd->ifld_table = & arc_cgen_ifld_table[0];
+}
+
+/* Subroutine of arc_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_operand_table (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  int machs = cd->machs;
+  const CGEN_OPERAND *init = & arc_cgen_operand_table[0];
+  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+     However each entry is indexed by it's enum so there can be holes in
+     the table.  */
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
+
+  cd->operand_table.init_entries = init;
+  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  /* ??? For now we just use mach to determine which ones we want.  */
+  for (i = 0; init[i].name != NULL; ++i)
+    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+	& machs)
+      selected[init[i].type] = &init[i];
+  cd->operand_table.entries = selected;
+  cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of arc_cgen_cpu_open to build the hardware table.
+   ??? This could leave out insns not supported by the specified mach/isa,
+   but that would cause errors like "foo only supported by bar" to become
+   "unknown insn", so for now we include all insns and require the app to
+   do the checking later.
+   ??? On the other hand, parsing of such insns may require their hardware or
+   operand elements to be in the table [which they mightn't be].  */
+
+static void
+build_insn_table (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  const CGEN_IBASE *ib = & arc_cgen_insn_table[0];
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+  for (i = 0; i < MAX_INSNS; ++i)
+    insns[i].base = &ib[i];
+  cd->insn_table.init_entries = insns;
+  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+  cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of arc_cgen_cpu_open to rebuild the tables.  */
+
+static void
+arc_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  CGEN_BITSET *isas = cd->isas;
+  unsigned int machs = cd->machs;
+
+  cd->int_insn_p = CGEN_INT_INSN_P;
+
+  /* Data derived from the isa spec.  */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+  cd->default_insn_bitsize = UNSET;
+  cd->base_insn_bitsize = UNSET;
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
+  cd->max_insn_bitsize = 0;
+  for (i = 0; i < MAX_ISAS; ++i)
+    if (cgen_bitset_contains (isas, i))
+      {
+	const CGEN_ISA *isa = & arc_cgen_isa_table[i];
+
+	/* Default insn sizes of all selected isas must be
+	   equal or we set the result to 0, meaning "unknown".  */
+	if (cd->default_insn_bitsize == UNSET)
+	  cd->default_insn_bitsize = isa->default_insn_bitsize;
+	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+	  ; /* This is ok.  */
+	else
+	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+	/* Base insn sizes of all selected isas must be equal
+	   or we set the result to 0, meaning "unknown".  */
+	if (cd->base_insn_bitsize == UNSET)
+	  cd->base_insn_bitsize = isa->base_insn_bitsize;
+	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+	  ; /* This is ok.  */
+	else
+	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+	/* Set min,max insn sizes.  */
+	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+	  cd->min_insn_bitsize = isa->min_insn_bitsize;
+	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+	  cd->max_insn_bitsize = isa->max_insn_bitsize;
+      }
+
+  /* Data derived from the mach spec.  */
+  for (i = 0; i < MAX_MACHS; ++i)
+    if (((1 << i) & machs) != 0)
+      {
+	const CGEN_MACH *mach = & arc_cgen_mach_table[i];
+
+	if (mach->insn_chunk_bitsize != 0)
+	{
+	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+	    {
+	      fprintf (stderr, "arc_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+	      abort ();
+	    }
+
+ 	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+	}
+      }
+
+  /* Determine which hw elements are used by MACH.  */
+  build_hw_table (cd);
+
+  /* Build the ifield table.  */
+  build_ifield_table (cd);
+
+  /* Determine which operands are used by MACH/ISA.  */
+  build_operand_table (cd);
+
+  /* Build the instruction table.  */
+  build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+   It's much like opening a file, and must be the first function called.
+   The arguments are a set of (type/value) pairs, terminated with
+   CGEN_CPU_OPEN_END.
+
+   Currently supported values:
+   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
+   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
+   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
+   CGEN_CPU_OPEN_END:     terminates arguments
+
+   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+   precluded.
+
+   ??? We only support ISO C stdargs here, not K&R.
+   Laziness, plus experiment to see if anything requires K&R - eventually
+   K&R will no longer be supported - e.g. GDB is currently trying this.  */
+
+CGEN_CPU_DESC
+arc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+  static int init_p;
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
+  unsigned int machs = 0; /* 0 = "unspecified" */
+  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+  va_list ap;
+
+  if (! init_p)
+    {
+      init_tables ();
+      init_p = 1;
+    }
+
+  memset (cd, 0, sizeof (*cd));
+
+  va_start (ap, arg_type);
+  while (arg_type != CGEN_CPU_OPEN_END)
+    {
+      switch (arg_type)
+	{
+	case CGEN_CPU_OPEN_ISAS :
+	  isas = va_arg (ap, CGEN_BITSET *);
+	  break;
+	case CGEN_CPU_OPEN_MACHS :
+	  machs = va_arg (ap, unsigned int);
+	  break;
+	case CGEN_CPU_OPEN_BFDMACH :
+	  {
+	    const char *name = va_arg (ap, const char *);
+	    const CGEN_MACH *mach =
+	      lookup_mach_via_bfd_name (arc_cgen_mach_table, name);
+
+	    machs |= 1 << mach->num;
+	    break;
+	  }
+	case CGEN_CPU_OPEN_ENDIAN :
+	  endian = va_arg (ap, enum cgen_endian);
+	  break;
+	default :
+	  fprintf (stderr, "arc_cgen_cpu_open: unsupported argument `%d'\n",
+		   arg_type);
+	  abort (); /* ??? return NULL? */
+	}
+      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+    }
+  va_end (ap);
+
+  /* Mach unspecified means "all".  */
+  if (machs == 0)
+    machs = (1 << MAX_MACHS) - 1;
+  /* Base mach is always selected.  */
+  machs |= 1;
+  if (endian == CGEN_ENDIAN_UNKNOWN)
+    {
+      /* ??? If target has only one, could have a default.  */
+      fprintf (stderr, "arc_cgen_cpu_open: no endianness specified\n");
+      abort ();
+    }
+
+  cd->isas = cgen_bitset_copy (isas);
+  cd->machs = machs;
+  cd->endian = endian;
+  /* FIXME: for the sparc case we can determine insn-endianness statically.
+     The worry here is where both data and insn endian can be independently
+     chosen, in which case this function will need another argument.
+     Actually, will want to allow for more arguments in the future anyway.  */
+  cd->insn_endian = endian;
+
+  /* Table (re)builder.  */
+  cd->rebuild_tables = arc_cgen_rebuild_tables;
+  arc_cgen_rebuild_tables (cd);
+
+  /* Default to not allowing signed overflow.  */
+  cd->signed_overflow_ok_p = 0;
+  
+  return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to arc_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+   MACH_NAME is the bfd name of the mach.  */
+
+CGEN_CPU_DESC
+arc_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
+{
+  return arc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+			       CGEN_CPU_OPEN_ENDIAN, endian,
+			       CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+   ??? This can live in a machine independent file, but there's currently
+   no place to put this file (there's no libcgen).  libopcodes is the wrong
+   place as some simulator ports use this but they don't use libopcodes.  */
+
+void
+arc_cgen_cpu_close (CGEN_CPU_DESC cd)
+{
+  unsigned int i;
+  const CGEN_INSN *insns;
+
+  if (cd->macro_insn_table.init_entries)
+    {
+      insns = cd->macro_insn_table.init_entries;
+      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
+    }
+
+  if (cd->insn_table.init_entries)
+    {
+      insns = cd->insn_table.init_entries;
+      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
+
+  if (cd->macro_insn_table.init_entries)
+    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+  if (cd->insn_table.init_entries)
+    free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+  if (cd->hw_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+  if (cd->operand_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
+  free (cd);
+}
+
diff --git a/opcodes/arc-desc.h b/opcodes/arc-desc.h
new file mode 100644
index 0000000..85d8564
--- /dev/null
+++ b/opcodes/arc-desc.h
@@ -0,0 +1,575 @@
+/* CPU data header for arc.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef ARC_CPU_H
+#define ARC_CPU_H
+
+#include "opcode/cgen-bitset.h"
+
+#define CGEN_ARCH arc
+
+/* Given symbol S, return arc_cgen_<S>.  */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define CGEN_SYM(s) arc##_cgen_##s
+#else
+#define CGEN_SYM(s) arc/**/_cgen_/**/s
+#endif
+
+
+/* Selected cpu families.  */
+#define HAVE_CPU_A5F
+#define HAVE_CPU_ARC600F
+#define HAVE_CPU_ARC700F
+
+#define CGEN_INSN_LSB0_P 0
+
+/* Minimum size of any insn (in bytes).  */
+#define CGEN_MIN_INSN_SIZE 4
+
+/* Maximum size of any insn (in bytes).  */
+#define CGEN_MAX_INSN_SIZE 4
+
+#define CGEN_INT_INSN_P 1
+
+/* Maximum number of syntax elements in an instruction.  */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
+   we can't hash on everything up to the space.  */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction.  */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
+
+/* Enums.  */
+
+/* Enum declaration for enum values for Qcond to be used in case form.  */
+typedef enum e_qvalues {
+  COND_AL = 0, COND_EQ = 1, COND_Z = 1, COND_NE = 2
+ , COND_NZ = 2, COND_PL = 3, COND_P = 3, COND_MI = 4
+ , COND_N = 4, COND_CS = 5, COND_C = 5, COND_LO = 5
+ , COND_CC = 6, COND_NC = 6, COND_HS = 6, COND_VS = 7
+ , COND_V = 7, COND_VC = 8, COND_NV = 8, COND_GT = 9
+ , COND_GE = 10, COND_LT = 11, COND_LE = 12, COND_HI = 13
+ , COND_LS = 14, COND_PNZ = 15
+} E_QVALUES;
+
+/* Enum declaration for enum values for i3cond to be used in case form.  */
+typedef enum e_i3cond {
+  COND3_GT = 0, COND3_GE = 1, COND3_LT = 2, COND3_LE = 3
+ , COND3_HI = 4, COND3_CC = 5, COND3_NC = 5, COND3_HS = 5
+ , COND3_CS = 6, COND3_C = 6, COND3_LO = 6, COND3_LS = 7
+} E_I3COND;
+
+/* Enum declaration for enum values for brcond to be used in case form.  */
+typedef enum e_brcond {
+  CONDBR_REQ = 0, CONDBR_RNE = 1, CONDBR_RLT = 2, CONDBR_RGE = 3
+ , CONDBR_RLO = 4, CONDBR_RHS = 5, CONDBR_BIT0 = 14, CONDBR_BIT1 = 15
+} E_BRCOND;
+
+/* Enum declaration for .  */
+typedef enum cr_names {
+  H_CR_GP = 26, H_CR_FP = 27, H_CR_SP = 28, H_CR_BLINK = 31
+ , H_CR_MLO = 57, H_CR_MMID = 58, H_CR_MHI = 59, H_CR_LP_COUNT = 60
+ , H_CR_PCL = 63, H_CR_ILINK1 = 29, H_CR_ILINK2 = 30, H_CR_R29 = 29
+ , H_CR_R30 = 30, H_CR_R0 = 0, H_CR_R1 = 1, H_CR_R2 = 2
+ , H_CR_R3 = 3, H_CR_R4 = 4, H_CR_R5 = 5, H_CR_R6 = 6
+ , H_CR_R7 = 7, H_CR_R8 = 8, H_CR_R9 = 9, H_CR_R10 = 10
+ , H_CR_R11 = 11, H_CR_R12 = 12, H_CR_R13 = 13, H_CR_R14 = 14
+ , H_CR_R15 = 15, H_CR_R16 = 16, H_CR_R17 = 17, H_CR_R18 = 18
+ , H_CR_R19 = 19, H_CR_R20 = 20, H_CR_R21 = 21, H_CR_R22 = 22
+ , H_CR_R23 = 23, H_CR_R24 = 24, H_CR_R25 = 25, H_CR_R26 = 26
+ , H_CR_R27 = 27, H_CR_R28 = 28, H_CR_R31 = 31, H_CR_R32 = 32
+ , H_CR_R33 = 33, H_CR_R34 = 34, H_CR_R35 = 35, H_CR_R36 = 36
+ , H_CR_R37 = 37, H_CR_R38 = 38, H_CR_R39 = 39, H_CR_R40 = 40
+ , H_CR_R41 = 41, H_CR_R42 = 42, H_CR_R43 = 43, H_CR_R44 = 44
+ , H_CR_R45 = 45, H_CR_R46 = 46, H_CR_R47 = 47, H_CR_R48 = 48
+ , H_CR_R49 = 49, H_CR_R50 = 50, H_CR_R51 = 51, H_CR_R52 = 52
+ , H_CR_R53 = 53, H_CR_R54 = 54, H_CR_R55 = 55, H_CR_R56 = 56
+ , H_CR_R57 = 57, H_CR_R58 = 58, H_CR_R59 = 59, H_CR_R60 = 60
+} CR_NAMES;
+
+/* Enum declaration for Core Register A encodings.  */
+typedef enum e_ra_rn {
+  RA_R0, RA_R1, RA_R2, RA_R3
+ , RA_R4, RA_R5, RA_R6, RA_R7
+ , RA_R8, RA_R9, RA_R10, RA_R11
+ , RA_R12, RA_R13, RA_R14, RA_R15
+ , RA_R16, RA_R17, RA_R18, RA_R19
+ , RA_R20, RA_R21, RA_R22, RA_R23
+ , RA_R24, RA_R25, RA_R26, RA_R27
+ , RA_R28, RA_R29, RA_R30, RA_R31
+ , RA_R32, RA_R33, RA_R34, RA_R35
+ , RA_R36, RA_R37, RA_R38, RA_R39
+ , RA_R40, RA_R41, RA_R42, RA_R43
+ , RA_R44, RA_R45, RA_R46, RA_R47
+ , RA_R48, RA_R49, RA_R50, RA_R51
+ , RA_R52, RA_R53, RA_R54, RA_R55
+ , RA_R56, RA_R57, RA_R58, RA_R59
+ , RA_R60, RA_R61, RA_R62, RA_R63
+} E_RA_RN;
+
+/* Enum declaration for major opcode.  */
+typedef enum op_maj {
+  OPM_B = 0, OPM_BLR = 1, OPM_LD_S9 = 2, OPM_ST_S9 = 3
+ , OPM_GO = 4, OPM_X05 = 5, OPM_X06 = 6, OPM_X07 = 7
+ , OPM_SLDADDR = 12, OPM_SADDSUBSHI = 13, OPM_SMOVCMPADDH = 14, OPM_SGO = 15
+ , OPM_LDO_S = 16, OPM_LDOB_S = 17, OPM_LDOW_S = 18, OPM_LDOWX_S = 19
+ , OPM_STO_S = 20, OPM_STOB_S = 21, OPM_STOW_S = 22, OPM_SSHSUBBIMM = 23
+ , OPM_SP = 24, OPM_GP = 25, OPM_LDPCREL = 26, OPM_SMOVU8 = 27
+ , OPM_SADDCMPU7 = 28, OPM_BR_S = 29, OPM_B_S = 30, OPM_BL_S = 31
+ , OPM_PSEUDO = 32
+} OP_MAJ;
+
+/* Enum declaration for general operations type.  */
+typedef enum go_type {
+  GO_TYPE_R_R, GO_TYPE_U6, GO_TYPE_S12, GO_TYPE_CC
+} GO_TYPE;
+
+/* Enum declaration for general operations conditional subtype.  */
+typedef enum go_cc_type {
+  GO_CC_REG, GO_CC_U6
+} GO_CC_TYPE;
+
+/* Enum declaration for general operations type.  */
+typedef enum go_op {
+  GO_OP_ADD = 0, GO_OP_ADC = 1, GO_OP_SUB = 2, GO_OP_SBC = 3
+ , GO_OP_AND = 4, GO_OP_OR = 5, GO_OP_BIC = 6, GO_OP_XOR = 7
+ , GO_OP_MAX = 8, GO_OP_MIN = 9, GO_OP_MOV = 10, GO_OP_TST = 11
+ , GO_OP_CMP = 12, GO_OP_RCMP = 13, GO_OP_RSUB = 14, GO_OP_BSET = 15
+ , GO_OP_BCLR = 16, GO_OP_BTST = 17, GO_OP_BXOR = 18, GO_OP_BMSK = 19
+ , GO_OP_ADD1 = 20, GO_OP_ADD2 = 21, GO_OP_ADD3 = 22, GO_OP_SUB1 = 23
+ , GO_OP_SUB2 = 24, GO_OP_SUB3 = 25, GO_OP_MPY = 26, GO_OP_MPYH = 27
+ , GO_OP_MPYHU = 28, GO_OP_MPYU = 29, GO_OP_RES30 = 30, GO_OP_RES31 = 31
+ , GO_OP_J = 32, GO_OP_J_D = 33, GO_OP_JL = 34, GO_OP_JL_D = 35
+ , GO_OP_LP = 40, GO_OP_FLAG = 41, GO_OP_LR = 42, GO_OP_SR = 43
+ , GO_OP_SOP = 47
+} GO_OP;
+
+/* Enum declaration for general single-operand operations type.  */
+typedef enum go_sop {
+  GO_OP_SOP_ASL = 0, GO_OP_SOP_ASR = 1, GO_OP_SOP_LSR = 2, GO_OP_SOP_ROR = 3
+ , GO_OP_SOP_RRC = 4, GO_OP_SOP_SEXB = 5, GO_OP_SOP_SEXW = 6, GO_OP_SOP_EXTB = 7
+ , GO_OP_SOP_EXTW = 8, GO_OP_SOP_ABS = 9, GO_OP_SOP_NOT = 10, GO_OP_SOP_RLC = 11
+ , GO_OP_SOP_EX = 12, GO_OP_SOP_ZOP = 63, GO_OP_SOP_PSEUDO = 62
+} GO_SOP;
+
+/* Enum declaration for short add / sub immediate type.  */
+typedef enum i16ldaddr_type {
+  I16_LDADDR_LD, I16_LDADDR_LDB, I16_LDADDR_LDW, I16_LDADDR_ADD
+} I16LDADDR_TYPE;
+
+/* Enum declaration for short add / sub immediate type.  */
+typedef enum i16addsubshi_type {
+  I16_ADDSUBSHI_ADD, I16_ADDSUBSHI_SUB, I16_ADDSUBSHI_ASL, I16_ADDSUBSHI_ASR
+} I16ADDSUBSHI_TYPE;
+
+/* Enum declaration for short mov / cmp / add  with high register type.  */
+typedef enum i16movcmpaddh_type {
+  I16_MOVCMPADDH_ADD, I16_MOVCMPADDH_MOVBH, I16_MOVCMPADDH_CMP, I16_MOVCMPADDH_MOVHB
+} I16MOVCMPADDH_TYPE;
+
+/* Enum declaration for short general operations.  */
+typedef enum i16go_type {
+  I16_GO_SOP = 0, I16_GO_SUB = 2, I16_GO_AND = 4, I16_GO_OR = 5
+ , I16_GO_BIC = 6, I16_GO_XOR = 7, I16_GO_TST = 11, I16_GO_MUL64 = 12
+ , I16_GO_SEXB = 13, I16_GO_SEXW = 14, I16_GO_EXTB = 15, I16_GO_EXTW = 16
+ , I16_GO_ABS = 17, I16_GO_NOT = 18, I16_GO_NEG = 19, I16_GO_ADD1 = 20
+ , I16_GO_ADD2 = 21, I16_GO_ADD3 = 22, I16_GO_ASLM = 24, I16_GO_LSRM = 25
+ , I16_GO_ASRM = 26, I16_GO_ASL = 27, I16_GO_ASR = 28, I16_GO_LSR = 29
+ , I16_GO_TRAP = 30, I16_GO_BRK = 31
+} I16GO_TYPE;
+
+/* Enum declaration for short general operations single operand.  */
+typedef enum i16go_sop_type {
+  I16_GO_SOP_J = 0, I16_GO_SOP_J_D = 1, I16_GO_SOP_JL = 2, I16_GO_SOP_JL_D = 3
+ , I16_GO_SOP_SUB_NE = 6, I16_GO_SOP_ZOP = 7
+} I16GO_SOP_TYPE;
+
+/* Enum declaration for short general operations single operand.  */
+typedef enum i16go_zop_type {
+  I16_GO_ZOP_NOP = 0, I16_GO_ZOP_UNIMP = 1, I16_GO_ZOP_JEQ = 4, I16_GO_ZOP_JNE = 5
+ , I16_GO_ZOP_J = 6, I16_GO_ZOP_J_D = 7
+} I16GO_ZOP_TYPE;
+
+/* Enum declaration for sp based insn type.  */
+typedef enum i16sp_type {
+  I16_SP_LD, I16_SP_LDB, I16_SP_ST, I16_SP_STB
+ , I16_SP_ADD, I16_SP_ADDSUB, I16_SP_POP, I16_SP_PUSH
+} I16SP_TYPE;
+
+/* Enum declaration for sp based 1op insn type.  */
+typedef enum i16addsub_spsp_type {
+  I16_SP_ADDSUB_ADD, I16_SP_ADDSUB_SUB
+} I16ADDSUB_SPSP_TYPE;
+
+/* Enum declaration for gp-relative insn type.  */
+typedef enum i16gp_type {
+  I16_GP_LD, I16_GP_LDB, I16_GP_LDW, I16_GP_ADD
+} I16GP_TYPE;
+
+/* Enum declaration for short add / cmp immediate type.  */
+typedef enum i16addcmpu7_type {
+  I16_ADDCMPU7_ADD, I16_ADDCMPU7_CMP
+} I16ADDCMPU7_TYPE;
+
+/* Enum declaration for shift / sub / bit immediate short insn w/ u5 type.  */
+typedef enum i16shsubbimm {
+  I16_SHSUBBIMM_ASL, I16_SHSUBBIMM_LSR, I16_SHSUBBIMM_ASR, I16_SHSUBBIMM_SUB
+ , I16_SHSUBBIMM_BSET, I16_SHSUBBIMM_BCLR, I16_SHSUBBIMM_BMSK, I16_SHSUBBIMM_BTST
+} I16SHSUBBIMM;
+
+/* Enum declaration for .  */
+typedef enum i_buf {
+  B_CC, B_UNCOND_FAR
+} I_BUF;
+
+/* Enum declaration for .  */
+typedef enum i_blr {
+  BLR_BL, BLR_BR
+} I_BLR;
+
+/* Enum declaration for .  */
+typedef enum i_br {
+  BR_RC, BR_U6
+} I_BR;
+
+/* Enum declaration for .  */
+typedef enum op_bl {
+  BL_CC, BL_UNCOND_FAR
+} OP_BL;
+
+/* Enum declaration for .  */
+typedef enum i_bcc_s {
+  B_S_CC = 3
+} I_BCC_S;
+
+/* Enum declaration for .  */
+typedef enum i_ldozz {
+  LDO_LD = 0, LDO_LDB = 2, LDO_LDBX = 3, LDO_LDW = 4
+ , LDO_LDWX = 5
+} I_LDOZZ;
+
+/* Enum declaration for .  */
+typedef enum i_ldr6zzx {
+  LDR_LD = 48, LDR_LDB = 50, LDR_LDBX = 51, LDR_LDW = 52
+ , LDR_LDWX = 53
+} I_LDR6ZZX;
+
+/* Enum declaration for .  */
+typedef enum i_stozzr {
+  STO_ST = 0, STO_STB = 2, STO_STW = 4
+} I_STOZZR;
+
+/* Enum declaration for .  */
+typedef enum i_ldoaa {
+  LDOAA_NO, LDOAA_AW, LDOAA_AB, LDOAA_AS
+} I_LDOAA;
+
+/* Enum declaration for .  */
+typedef enum i_ldraa {
+  LDRAA_NO, LDRAA_AW, LDRAA_AB, LDRAA_AS
+} I_LDRAA;
+
+/* Enum declaration for .  */
+typedef enum i_stoaa {
+  STOAA_NO, STOAA_AW, STOAA_AB, STOAA_AS
+} I_STOAA;
+
+/* Enum declaration for general zero-operand operations type.  */
+typedef enum go_zop {
+  GO_OP_ZOP_SLEEP = 1, GO_OP_ZOP_SWI = 2, GO_OP_ZOP_SYNC = 3, GO_OP_ZOP_RTIE = 4
+ , GO_OP_ZOP_BRK = 5
+} GO_ZOP;
+
+/* Enum declaration for general operations type.  */
+typedef enum x05_go_op {
+  X05_ASL = 0, X05_LSR = 1, X05_ASR = 2, X05_ROR = 3
+ , X05_MUL64 = 4, X05_MULU64 = 5, X05_ADDS = 6, X05_SUBS = 7
+ , X05_DIVAW = 8, X05_ASLS = 10, X05_ASRS = 11, X05_ADDSDW = 40
+ , X05_SUBSDW = 41, X05_SOP = 47, X05_CMACRDW = 38, X05_MACDW = 16
+ , X05_MACFLW = 52, X05_MACHFLW = 55, X05_MACHLW = 54, X05_MACHULW = 53
+ , X05_MACLW = 51, X05_MACRDW = 18, X05_MACUDW = 17, X05_MSUBDW = 20
+ , X05_MULDW = 12, X05_MULFLW = 50, X05_MULHFLW = 57, X05_MULHLW = 56
+ , X05_MULLW = 49, X05_MULRDW = 14, X05_MULUDW = 13, X05_MULULW = 48
+} X05_GO_OP;
+
+/* Enum declaration for x06 extension single-operand operantion.  */
+typedef enum x05_sop_kind {
+  X05_SOP_SWAP = 0, X05_SOP_NORM = 1, X05_SOP_SAT16 = 2, X05_SOP_RND16 = 3
+ , X05_SOP_ABSSW = 4, X05_SOP_ABSS = 5, X05_SOP_NEGSW = 6, X05_SOP_NEGS = 7
+ , X05_SOP_NORMW = 8, X05_SOP_ZOP = 63
+} X05_SOP_KIND;
+
+/* Enum declaration for .  */
+typedef enum pushpop_kind {
+  PUSHPOP_B = 1, PUSHPOP_BLINK = 17
+} PUSHPOP_KIND;
+
+/* Enum declaration for .  */
+typedef enum pushpop_r_b {
+  OP_B_0
+} PUSHPOP_R_B;
+
+/* Attributes.  */
+
+/* Enum declaration for machine type selection.  */
+typedef enum mach_attr {
+  MACH_BASE, MACH_A5, MACH_ARC600, MACH_ARC700
+ , MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection.  */
+typedef enum isa_attr {
+  ISA_ARCOMPACT, ISA_MAX
+} ISA_ATTR;
+
+/* Enum declaration for can take long immediate for operand.  */
+typedef enum limm_attr {
+  LIMM_NONE, LIMM_H, LIMM_B, LIMM_BC
+ , LIMM_C
+} LIMM_ATTR;
+
+/* Number of architecture variants.  */
+#define MAX_ISAS  1
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support.  */
+
+/* Ifield attribute indices.  */
+
+/* Enum declaration for cgen_ifld attrs.  */
+typedef enum cgen_ifld_attr {
+  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
+ , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr.  */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+
+/* Enum declaration for arc ifield types.  */
+typedef enum ifield_type {
+  ARC_F_NIL, ARC_F_ANYOF, ARC_F_COND_Q, ARC_F_COND_I2
+ , ARC_F_COND_I3, ARC_F_BRCOND, ARC_F_OP__A, ARC_F_OP__B
+ , ARC_F_OP__C, ARC_F_B_5_3, ARC_F_OP_B, ARC_F_OP_C
+ , ARC_F_OP_CJ, ARC_F_H_2_0, ARC_F_H_5_3, ARC_F_OP_H
+ , ARC_F_U6, ARC_F_U6X2, ARC_F_DELAY_N, ARC_F_RES27
+ , ARC_F_F, ARC_F_CBRANCH_IMM, ARC_F_OP_A, ARC_F_S12H
+ , ARC_F_S12, ARC_F_S12X2, ARC_F_REL10, ARC_F_REL7
+ , ARC_F_REL8, ARC_F_REL13BL, ARC_F_D21L, ARC_F_D21BL
+ , ARC_F_D21H, ARC_F_D25M, ARC_F_D25H, ARC_F_REL21
+ , ARC_F_REL21BL, ARC_F_REL25, ARC_F_REL25BL, ARC_F_D9L
+ , ARC_F_D9H, ARC_F_REL9, ARC_F_U3, ARC_F_U5
+ , ARC_F_U7, ARC_F_U8, ARC_F_S9, ARC_F_U5X2
+ , ARC_F_U5X4, ARC_F_U8X4, ARC_F_S9X1, ARC_F_S9X2
+ , ARC_F_S9X4, ARC_F_DUMMY, ARC_F_OPM, ARC_F_GO_TYPE
+ , ARC_F_GO_CC_TYPE, ARC_F_GO_OP, ARC_F_I16_43, ARC_F_I16_GO
+ , ARC_F_I16_GP_TYPE, ARC_F_I16ADDCMPU7_TYPE, ARC_F_BUF, ARC_F_BR
+ , ARC_F_BLUF, ARC_F_BRSCOND, ARC_F_LDOZZX, ARC_F_LDR6ZZX
+ , ARC_F_STOZZR, ARC_F_LDOAA, ARC_F_LDRAA, ARC_F_STOAA
+ , ARC_F_LDODI, ARC_F_LDRDI, ARC_F_STODI, ARC_F_TRAPNUM
+ , ARC_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) ARC_F_MAX)
+
+/* Hardware attribute indices.  */
+
+/* Enum declaration for cgen_hw attrs.  */
+typedef enum cgen_hw_attr {
+  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr.  */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
+/* Enum declaration for arc hardware types.  */
+typedef enum cgen_hw_type {
+  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_LBIT, HW_H_ZBIT, HW_H_NBIT
+ , HW_H_CBIT, HW_H_VBIT, HW_H_UBIT, HW_H_E1
+ , HW_H_E2, HW_H_S1BIT, HW_H_S2BIT, HW_H_QCONDB
+ , HW_H_QCONDJ, HW_H_QCONDI, HW_H_UNCONDB, HW_H_UNCONDJ
+ , HW_H_UNCONDI, HW_H_I2COND, HW_H_I3COND, HW_H_DELAY
+ , HW_H_UFLAGS, HW_H_NIL, HW_H_AUFLAGS, HW_H_AUFFLAGS
+ , HW_H_DI, HW_H_INSN16, HW_H_INSN32, HW_H__AW
+ , HW_H_CR, HW_H_CR16, HW_H_R0, HW_H_GP
+ , HW_H_SP, HW_H_PCL, HW_H_NOILINK, HW_H_ILINKX
+ , HW_H_R31, HW_H_AUXR, HW_H_STATUS32, HW_H_TIMER_EXPIRE
+ , HW_H_PROF_OFFSET, HW_H_NE, HW_H_PC, HW_H_RCCS
+ , HW_H_RCC, HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices.  */
+
+/* Enum declaration for cgen_operand attrs.  */
+typedef enum cgen_operand_attr {
+  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr.  */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+
+/* Enum declaration for arc operand types.  */
+typedef enum cgen_operand_type {
+  ARC_OPERAND_PC, ARC_OPERAND_LBIT, ARC_OPERAND_ZBIT, ARC_OPERAND_NBIT
+ , ARC_OPERAND_CBIT, ARC_OPERAND_VBIT, ARC_OPERAND_S1BIT, ARC_OPERAND_S2BIT
+ , ARC_OPERAND_QCONDB, ARC_OPERAND_QCONDJ, ARC_OPERAND_QCONDI, ARC_OPERAND_UNCONDB
+ , ARC_OPERAND_UNCONDJ, ARC_OPERAND_UNCONDI, ARC_OPERAND_I2COND, ARC_OPERAND_I3COND
+ , ARC_OPERAND_DELAY_N, ARC_OPERAND__S, ARC_OPERAND__L, ARC_OPERAND_F
+ , ARC_OPERAND_F1, ARC_OPERAND_F1F, ARC_OPERAND_F0, ARC_OPERAND_R_A
+ , ARC_OPERAND_RA, ARC_OPERAND_R_B, ARC_OPERAND_RB, ARC_OPERAND_R_C
+ , ARC_OPERAND_RC, ARC_OPERAND_RH, ARC_OPERAND_R0, ARC_OPERAND_R31
+ , ARC_OPERAND_GP, ARC_OPERAND_SP, ARC_OPERAND_PCL, ARC_OPERAND_RA_0
+ , ARC_OPERAND_RB_0, ARC_OPERAND_RC_ILINK, ARC_OPERAND_RC_NOILINK, ARC_OPERAND_NE
+ , ARC_OPERAND_U6, ARC_OPERAND_U6X2, ARC_OPERAND_U3, ARC_OPERAND_U5
+ , ARC_OPERAND_U7, ARC_OPERAND_U8, ARC_OPERAND_S9, ARC_OPERAND_S12
+ , ARC_OPERAND_S12X2, ARC_OPERAND_U5X4, ARC_OPERAND_SC_U5_, ARC_OPERAND_SC_U5W
+ , ARC_OPERAND_SC_U5B, ARC_OPERAND_U8X4, ARC_OPERAND_S9X4, ARC_OPERAND_SC_S9_
+ , ARC_OPERAND_SC_S9W, ARC_OPERAND_SC_S9B, ARC_OPERAND_LABEL7, ARC_OPERAND_LABEL8
+ , ARC_OPERAND_LABEL9, ARC_OPERAND_LABEL10, ARC_OPERAND_LABEL13A, ARC_OPERAND_LABEL21
+ , ARC_OPERAND_LABEL21A, ARC_OPERAND_LABEL25, ARC_OPERAND_LABEL25A, ARC_OPERAND_DUMMY_OP
+ , ARC_OPERAND_RCCS, ARC_OPERAND_RCC, ARC_OPERAND_LDODI, ARC_OPERAND_LDRDI
+ , ARC_OPERAND_STODI, ARC_OPERAND_EXDI, ARC_OPERAND__AW, ARC_OPERAND_TRAPNUM
+ , ARC_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types.  */
+#define MAX_OPERANDS 76
+
+/* Maximum number of operands referenced by any insn.  */
+#define MAX_OPERAND_INSTANCES 26
+
+/* Insn attribute indices.  */
+
+/* Enum declaration for cgen_insn attrs.  */
+typedef enum cgen_insn_attr {
+  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_SHORT_P, CGEN_INSN_END_BOOLS
+ , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_LIMM, CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr.  */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_LIMM_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LIMM-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SHORT_P_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SHORT_P)) != 0)
+
+/* cgen.h uses things we just defined.  */
+#include "opcode/cgen.h"
+
+extern const struct cgen_ifld arc_cgen_ifld_table[];
+
+/* Attributes.  */
+extern const CGEN_ATTR_TABLE arc_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE arc_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE arc_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE arc_cgen_insn_attr_table[];
+
+/* Hardware decls.  */
+
+extern CGEN_KEYWORD arc_cgen_opval_h_Qcondb;
+extern CGEN_KEYWORD arc_cgen_opval_h_Qcondj;
+extern CGEN_KEYWORD arc_cgen_opval_h_Qcondi;
+extern CGEN_KEYWORD arc_cgen_opval_h_uncondb;
+extern CGEN_KEYWORD arc_cgen_opval_h_uncondj;
+extern CGEN_KEYWORD arc_cgen_opval_h_uncondi;
+extern CGEN_KEYWORD arc_cgen_opval_h_i2cond;
+extern CGEN_KEYWORD arc_cgen_opval_h_i3cond;
+extern CGEN_KEYWORD arc_cgen_opval_h_delay;
+extern CGEN_KEYWORD arc_cgen_opval_h_uflags;
+extern CGEN_KEYWORD arc_cgen_opval_h_nil;
+extern CGEN_KEYWORD arc_cgen_opval_h_auflags;
+extern CGEN_KEYWORD arc_cgen_opval_h_aufflags;
+extern CGEN_KEYWORD arc_cgen_opval_h_Di;
+extern CGEN_KEYWORD arc_cgen_opval_h_insn16;
+extern CGEN_KEYWORD arc_cgen_opval_h_insn32;
+extern CGEN_KEYWORD arc_cgen_opval_h__aw;
+extern CGEN_KEYWORD arc_cgen_opval_cr_names;
+extern CGEN_KEYWORD arc_cgen_opval_h_cr16;
+extern CGEN_KEYWORD arc_cgen_opval_h_r0;
+extern CGEN_KEYWORD arc_cgen_opval_h_gp;
+extern CGEN_KEYWORD arc_cgen_opval_h_sp;
+extern CGEN_KEYWORD arc_cgen_opval_h_pcl;
+extern CGEN_KEYWORD arc_cgen_opval_h_noilink;
+extern CGEN_KEYWORD arc_cgen_opval_h_ilinkx;
+extern CGEN_KEYWORD arc_cgen_opval_h_r31;
+extern CGEN_KEYWORD arc_cgen_opval_cr_names;
+extern CGEN_KEYWORD arc_cgen_opval_h_status32;
+extern CGEN_KEYWORD arc_cgen_opval_h_ne;
+extern CGEN_KEYWORD arc_cgen_opval_h_RccS;
+extern CGEN_KEYWORD arc_cgen_opval_h_Rcc;
+
+extern const CGEN_HW_ENTRY arc_cgen_hw_table[];
+
+
+
+#endif /* ARC_CPU_H */
diff --git a/opcodes/arc-ibld.c b/opcodes/arc-ibld.c
new file mode 100644
index 0000000..958dde7
--- /dev/null
+++ b/opcodes/arc-ibld.c
@@ -0,0 +1,2340 @@
+/* Instruction building/extraction support for arc. -*- C -*-
+
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
+
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006, 2007
+   Free Software Foundation, Inc.
+
+   This file is part of libopcodes.
+
+   This library is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "arc-desc.h"
+#include "arc-opc.h"
+#include "opintl.h"
+#include "safe-ctype.h"
+
+#undef  min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef  max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+/* Used by the ifield rtx function.  */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
+static const char * insert_insn_normal
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+static int extract_normal
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
+static int extract_insn_normal
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+#if CGEN_INT_INSN_P
+static void put_insn_int_value
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
+static CGEN_INLINE int fill_cache
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
+static CGEN_INLINE long extract_1
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
+#endif
+
+/* Operand insertion.  */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal.  */
+
+static CGEN_INLINE void
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
+{
+  unsigned long x,mask;
+  int shift;
+
+  x = cgen_get_insn_value (cd, bufp, word_length);
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+  cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+   ATTRS is a mask of the boolean attributes.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   The result is an error message or NULL if success.  */
+
+/* ??? This duplicates functionality with bfd's howto table and
+   bfd_install_relocation.  */
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static const char *
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
+{
+  static char errbuf[100];
+  /* Written this way to avoid undefined behaviour.  */
+  unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value.  */
+  if (length == 0)
+    return NULL;
+
+  if (word_length > 32)
+    abort ();
+
+  /* For architectures with insns smaller than the base-insn-bitsize,
+     word_length may be too big.  */
+  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+    {
+      if (word_offset == 0
+	  && word_length > total_length)
+	word_length = total_length;
+    }
+
+  /* Ensure VALUE will fit.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
+    {
+      long minval = - (1L << (length - 1));
+      unsigned long maxval = mask;
+      
+      if ((value > 0 && (unsigned long) value > maxval)
+	  || value < minval)
+	{
+	  /* xgettext:c-format */
+	  sprintf (errbuf,
+		   _("operand out of range (%ld not between %ld and %lu)"),
+		   value, minval, maxval);
+	  return errbuf;
+	}
+    }
+  else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
+    {
+      unsigned long maxval = mask;
+      unsigned long val = (unsigned long) value;
+
+      /* For hosts with a word size > 32 check to see if value has been sign
+	 extended beyond 32 bits.  If so then ignore these higher sign bits
+	 as the user is attempting to store a 32-bit signed value into an
+	 unsigned 32-bit field which is allowed.  */
+      if (sizeof (unsigned long) > 4 && ((value >> 32) == -1))
+	val &= 0xFFFFFFFF;
+
+      if (val > maxval)
+	{
+	  /* xgettext:c-format */
+	  sprintf (errbuf,
+		   _("operand out of range (0x%lx not between 0 and 0x%lx)"),
+		   val, maxval);
+	  return errbuf;
+	}
+    }
+  else
+    {
+      if (! cgen_signed_overflow_ok_p (cd))
+	{
+	  long minval = - (1L << (length - 1));
+	  long maxval =   (1L << (length - 1)) - 1;
+	  
+	  if (value < minval || value > maxval)
+	    {
+	      sprintf
+		/* xgettext:c-format */
+		(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+		 value, minval, maxval);
+	      return errbuf;
+	    }
+	}
+    }
+
+#if CGEN_INT_INSN_P
+
+  {
+    int shift;
+
+    if (CGEN_INSN_LSB0_P)
+      shift = (word_offset + start + 1) - length;
+    else
+      shift = total_length - (word_offset + start + length);
+    *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+  }
+
+#else /* ! CGEN_INT_INSN_P */
+
+  {
+    unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+    insert_1 (cd, value, start, length, word_length, bufp);
+  }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  return NULL;
+}
+
+/* Default insn builder (insert handler).
+   The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
+   that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
+   recorded in host byte order, otherwise BUFFER is an array of bytes
+   and the value is recorded in target byte order).
+   The result is an error message or NULL if success.  */
+
+static const char *
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  unsigned long value;
+  const CGEN_SYNTAX_CHAR_TYPE * syn;
+
+  CGEN_INIT_INSERT (cd);
+  value = CGEN_INSN_BASE_VALUE (insn);
+
+  /* If we're recording insns as numbers (rather than a string of bytes),
+     target byte order handling is deferred until later.  */
+
+#if CGEN_INT_INSN_P
+
+  put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
+		      CGEN_FIELDS_BITSIZE (fields), value);
+
+#else
+
+  cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+					(unsigned) CGEN_FIELDS_BITSIZE (fields)),
+		       value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  /* ??? It would be better to scan the format's fields.
+     Still need to be able to insert a value based on the operand though;
+     e.g. storing a branch displacement that got resolved later.
+     Needs more thought first.  */
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+    {
+      const char *errmsg;
+
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+	continue;
+
+      errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+				       fields, buffer, pc);
+      if (errmsg)
+	return errmsg;
+    }
+
+  return NULL;
+}
+
+#if CGEN_INT_INSN_P
+/* Cover function to store an insn value into an integral insn.  Must go here
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+
+static void
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
+{
+  /* For architectures with insns smaller than the base-insn-bitsize,
+     length may be too big.  */
+  if (length > insn_length)
+    *buf = value;
+  else
+    {
+      int shift = insn_length - length;
+      /* Written this way to avoid undefined behaviour.  */
+      CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+      *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
+    }
+}
+#endif
+
+/* Operand extraction.  */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+   Ensure sufficient bytes are cached in EX_INFO.
+   OFFSET is the offset in bytes from the start of the insn of the value.
+   BYTES is the length of the needed value.
+   Returns 1 for success, 0 for failure.  */
+
+static CGEN_INLINE int
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
+{
+  /* It's doubtful that the middle part has already been fetched so
+     we don't optimize that case.  kiss.  */
+  unsigned int mask;
+  disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+  /* First do a quick check.  */
+  mask = (1 << bytes) - 1;
+  if (((ex_info->valid >> offset) & mask) == mask)
+    return 1;
+
+  /* Search for the first byte we need to read.  */
+  for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+    if (! (mask & ex_info->valid))
+      break;
+
+  if (bytes)
+    {
+      int status;
+
+      pc += offset;
+      status = (*info->read_memory_func)
+	(pc, ex_info->insn_bytes + offset, bytes, info);
+
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, pc, info);
+	  return 0;
+	}
+
+      ex_info->valid |= ((1 << bytes) - 1) << offset;
+    }
+
+  return 1;
+}
+
+/* Subroutine of extract_normal.  */
+
+static CGEN_INLINE long
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
+{
+  unsigned long x;
+  int shift;
+
+  x = cgen_get_insn_value (cd, bufp, word_length);
+
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  return x >> shift;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+   INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
+   or sometimes less for cases like the m32r where the base insn size is 32
+   but some insns are 16 bits.
+   ATTRS is a mask of the boolean attributes.  We only need `SIGNED',
+   but for generality we take a bitmask of all of them.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   Returns 1 for success, 0 for failure.  */
+
+/* ??? The return code isn't properly used.  wip.  */
+
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static int
+extract_normal (CGEN_CPU_DESC cd,
+#if ! CGEN_INT_INSN_P
+		CGEN_EXTRACT_INFO *ex_info,
+#else
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+#endif
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
+#if ! CGEN_INT_INSN_P
+		bfd_vma pc,
+#else
+		bfd_vma pc ATTRIBUTE_UNUSED,
+#endif
+		long *valuep)
+{
+  long value, mask;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value
+     so give it a standard value of zero.  */
+  if (length == 0)
+    {
+      *valuep = 0;
+      return 1;
+    }
+
+  if (word_length > 32)
+    abort ();
+
+  /* For architectures with insns smaller than the insn-base-bitsize,
+     word_length may be too big.  */
+  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+    {
+      if (word_offset + word_length > total_length)
+	word_length = total_length - word_offset;
+    }
+
+  /* Does the value reside in INSN_VALUE, and at the right alignment?  */
+
+  if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
+    {
+      if (CGEN_INSN_LSB0_P)
+	value = insn_value >> ((word_offset + start + 1) - length);
+      else
+	value = insn_value >> (total_length - ( word_offset + start + length));
+    }
+
+#if ! CGEN_INT_INSN_P
+
+  else
+    {
+      unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+      if (word_length > 32)
+	abort ();
+
+      if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+	return 0;
+
+      value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
+    }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+  value &= mask;
+  /* sign extend? */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
+      && (value & (1L << (length - 1))))
+    value |= ~mask;
+
+  *valuep = value;
+
+  return 1;
+}
+
+/* Default insn extractor.
+
+   INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
+   The extracted fields are stored in FIELDS.
+   EX_INFO is used to handle reading variable length insns.
+   Return the length of the insn in bits, or 0 if no match,
+   or -1 if an error occurs fetching data (memory_error_func will have
+   been called).  */
+
+static int
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+  CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+  CGEN_INIT_EXTRACT (cd);
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+    {
+      int length;
+
+      if (CGEN_SYNTAX_CHAR_P (*syn))
+	continue;
+
+      length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+					ex_info, insn_value, fields, pc);
+      if (length <= 0)
+	return length;
+    }
+
+  /* We recognized and successfully extracted this insn.  */
+  return CGEN_INSN_BITSIZE (insn);
+}
+
+/* Machine generated code added here.  */
+
+const char * arc_cgen_insert_operand
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+
+/* Main entry point for operand insertion.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  It's also needed by GAS to insert operands that couldn't be
+   resolved during parsing.  */
+
+const char *
+arc_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
+{
+  const char * errmsg = NULL;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case ARC_OPERAND_EXDI :
+      errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_F :
+      errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_F0 :
+      errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_F1 :
+      errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_F1F :
+      errmsg = insert_normal (cd, fields->f_F, 0, 0, 16, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_GP :
+      break;
+    case ARC_OPERAND_LDODI :
+      errmsg = insert_normal (cd, fields->f_LDODi, 0, 0, 20, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_LDRDI :
+      errmsg = insert_normal (cd, fields->f_LDRDi, 0, 0, 16, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_NE :
+      break;
+    case ARC_OPERAND_PCL :
+      break;
+    case ARC_OPERAND_QCONDB :
+      errmsg = insert_normal (cd, fields->f_cond_Q, 0, 0, 27, 5, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_QCONDI :
+      errmsg = insert_normal (cd, fields->f_cond_Q, 0, 0, 27, 5, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_QCONDJ :
+      errmsg = insert_normal (cd, fields->f_cond_Q, 0, 0, 27, 5, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_R0 :
+      break;
+    case ARC_OPERAND_R31 :
+      break;
+    case ARC_OPERAND_RA :
+      errmsg = insert_normal (cd, fields->f_op_A, 0, 0, 26, 6, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_RA_0 :
+      errmsg = insert_normal (cd, fields->f_op_A, 0, 0, 26, 6, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_RB :
+      {
+{
+  FLD (f_op__b) = ((FLD (f_op_B)) & (7));
+  FLD (f_B_5_3) = ((unsigned int) (FLD (f_op_B)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_op__b, 0, 0, 5, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_B_5_3, 0, 0, 17, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_RB_0 :
+      {
+{
+  FLD (f_op__b) = ((FLD (f_op_B)) & (7));
+  FLD (f_B_5_3) = ((unsigned int) (FLD (f_op_B)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_op__b, 0, 0, 5, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_B_5_3, 0, 0, 17, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_RC :
+      errmsg = insert_normal (cd, fields->f_op_C, 0, 0, 20, 6, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_RC_ILINK :
+      errmsg = insert_normal (cd, fields->f_op_Cj, 0, 0, 20, 6, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_RC_NOILINK :
+      errmsg = insert_normal (cd, fields->f_op_Cj, 0, 0, 20, 6, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_R_A :
+      errmsg = insert_normal (cd, fields->f_op__a, 0, 0, 13, 3, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_R_B :
+      errmsg = insert_normal (cd, fields->f_op__b, 0, 0, 5, 3, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_R_C :
+      errmsg = insert_normal (cd, fields->f_op__c, 0, 0, 8, 3, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_RCC :
+      errmsg = insert_normal (cd, fields->f_brcond, 0, 0, 28, 4, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_RCCS :
+      errmsg = insert_normal (cd, fields->f_brscond, 0, 0, 8, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_RH :
+      {
+{
+  FLD (f_h_2_0) = ((FLD (f_op_h)) & (7));
+  FLD (f_h_5_3) = ((unsigned int) (FLD (f_op_h)) >> (3));
+}
+        errmsg = insert_normal (cd, fields->f_h_2_0, 0, 0, 8, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_h_5_3, 0, 0, 13, 3, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_SP :
+      break;
+    case ARC_OPERAND_STODI :
+      errmsg = insert_normal (cd, fields->f_STODi, 0, 0, 26, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_U6 :
+      errmsg = insert_normal (cd, fields->f_u6, 0, 0, 20, 6, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_U6X2 :
+      {
+        long value = fields->f_u6x2;
+        value = ((unsigned int) (value) >> (1));
+        errmsg = insert_normal (cd, value, 0, 0, 20, 6, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND__AW :
+      break;
+    case ARC_OPERAND__L :
+      break;
+    case ARC_OPERAND__S :
+      break;
+    case ARC_OPERAND_CBIT :
+      break;
+    case ARC_OPERAND_DELAY_N :
+      errmsg = insert_normal (cd, fields->f_delay_N, 0, 0, 26, 1, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_DUMMY_OP :
+      errmsg = insert_normal (cd, fields->f_dummy, 0, 0, 16, 16, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_I2COND :
+      errmsg = insert_normal (cd, fields->f_cond_i2, 0, 0, 5, 2, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_I3COND :
+      errmsg = insert_normal (cd, fields->f_cond_i3, 0, 0, 7, 3, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_LABEL10 :
+      {
+        long value = fields->f_rel10;
+        value = ((int) (((value) - (((pc) & (-4))))) >> (1));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 7, 9, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_LABEL13A :
+      {
+        long value = fields->f_rel13bl;
+        value = ((int) (((value) - (((pc) & (-4))))) >> (2));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_LABEL21 :
+      {
+{
+  FLD (f_d21l) = ((((unsigned int) (((FLD (f_rel21)) - (((pc) & (-4))))) >> (1))) & (1023));
+  FLD (f_d21h) = ((unsigned int) (((FLD (f_rel21)) - (((pc) & (-4))))) >> (11));
+}
+        errmsg = insert_normal (cd, fields->f_d21l, 0, 0, 5, 10, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_d21h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_LABEL21A :
+      {
+{
+  FLD (f_d21bl) = ((((unsigned int) (((FLD (f_rel21bl)) - (((pc) & (-4))))) >> (2))) & (511));
+  FLD (f_d21h) = ((unsigned int) (((FLD (f_rel21bl)) - (((pc) & (-4))))) >> (11));
+}
+        errmsg = insert_normal (cd, fields->f_d21bl, 0, 0, 5, 9, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_d21h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_LABEL25 :
+      {
+{
+  FLD (f_d21l) = ((((unsigned int) (((FLD (f_rel25)) - (((pc) & (-4))))) >> (1))) & (1023));
+  FLD (f_d25m) = ((unsigned int) (((FLD (f_rel25)) - (((pc) & (-4))))) >> (11));
+  FLD (f_d25h) = ((unsigned int) (((FLD (f_rel25)) - (((pc) & (-4))))) >> (21));
+}
+        errmsg = insert_normal (cd, fields->f_d21l, 0, 0, 5, 10, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_d25m, 0, 0, 16, 10, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_d25h, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_LABEL25A :
+      {
+{
+  FLD (f_d21bl) = ((((unsigned int) (((FLD (f_rel25bl)) - (((pc) & (-4))))) >> (2))) & (511));
+  FLD (f_d25m) = ((unsigned int) (((FLD (f_rel25bl)) - (((pc) & (-4))))) >> (11));
+  FLD (f_d25h) = ((unsigned int) (((FLD (f_rel25bl)) - (((pc) & (-4))))) >> (21));
+}
+        errmsg = insert_normal (cd, fields->f_d21bl, 0, 0, 5, 9, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_d25m, 0, 0, 16, 10, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_d25h, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_LABEL7 :
+      {
+        long value = fields->f_rel7;
+        value = ((int) (((value) - (((pc) & (-4))))) >> (1));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 10, 6, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_LABEL8 :
+      {
+        long value = fields->f_rel8;
+        value = ((int) (((value) - (((pc) & (-4))))) >> (1));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 9, 7, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_LABEL9 :
+      {
+{
+  FLD (f_d9l) = ((((unsigned int) (((FLD (f_rel9)) - (((pc) & (-4))))) >> (1))) & (127));
+  FLD (f_d9h) = ((unsigned int) (((FLD (f_rel9)) - (((pc) & (-4))))) >> (8));
+}
+        errmsg = insert_normal (cd, fields->f_d9l, 0, 0, 8, 7, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_d9h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_LBIT :
+      break;
+    case ARC_OPERAND_NBIT :
+      break;
+    case ARC_OPERAND_S12 :
+      {
+{
+  FLD (f_u6) = ((FLD (f_s12)) & (63));
+  FLD (f_s12h) = ((unsigned int) (FLD (f_s12)) >> (6));
+}
+        errmsg = insert_normal (cd, fields->f_u6, 0, 0, 20, 6, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_s12h, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_S12X2 :
+      {
+{
+  FLD (f_u6) = ((((unsigned int) (FLD (f_s12x2)) >> (1))) & (63));
+  FLD (f_s12h) = ((unsigned int) (FLD (f_s12x2)) >> (7));
+}
+        errmsg = insert_normal (cd, fields->f_u6, 0, 0, 20, 6, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_s12h, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_S1BIT :
+      break;
+    case ARC_OPERAND_S2BIT :
+      break;
+    case ARC_OPERAND_S9 :
+      {
+{
+  FLD (f_u8) = ((FLD (f_s9)) & (255));
+  FLD (f_d9h) = ((unsigned int) (FLD (f_s9)) >> (8));
+}
+        errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 32, total_length, buffer);
+        if (errmsg)
+          break;
+        errmsg = insert_normal (cd, fields->f_d9h, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, buffer);
+        if (errmsg)
+          break;
+      }
+      break;
+    case ARC_OPERAND_S9X4 :
+      {
+        long value = fields->f_s9x4;
+        value = ((unsigned int) (value) >> (2));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_SC_S9_ :
+      {
+        long value = fields->f_s9x4;
+        value = ((unsigned int) (value) >> (2));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_SC_S9B :
+      errmsg = insert_normal (cd, fields->f_s9x1, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_SC_S9W :
+      {
+        long value = fields->f_s9x2;
+        value = ((unsigned int) (value) >> (1));
+        errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_SC_U5_ :
+      {
+        long value = fields->f_u5x4;
+        value = ((unsigned int) (value) >> (2));
+        errmsg = insert_normal (cd, value, 0, 0, 11, 5, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_SC_U5B :
+      errmsg = insert_normal (cd, fields->f_u5, 0, 0, 11, 5, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_SC_U5W :
+      {
+        long value = fields->f_u5x2;
+        value = ((unsigned int) (value) >> (1));
+        errmsg = insert_normal (cd, value, 0, 0, 11, 5, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_TRAPNUM :
+      errmsg = insert_normal (cd, fields->f_trapnum, 0, 0, 5, 6, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_U3 :
+      errmsg = insert_normal (cd, fields->f_u3, 0, 0, 13, 3, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_U5 :
+      errmsg = insert_normal (cd, fields->f_u5, 0, 0, 11, 5, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_U5X4 :
+      {
+        long value = fields->f_u5x4;
+        value = ((unsigned int) (value) >> (2));
+        errmsg = insert_normal (cd, value, 0, 0, 11, 5, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_U7 :
+      errmsg = insert_normal (cd, fields->f_u7, 0, 0, 9, 7, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_U8 :
+      errmsg = insert_normal (cd, fields->f_u8, 0, 0, 8, 8, 32, total_length, buffer);
+      break;
+    case ARC_OPERAND_U8X4 :
+      {
+        long value = fields->f_u8x4;
+        value = ((unsigned int) (value) >> (2));
+        errmsg = insert_normal (cd, value, 0, 0, 8, 8, 32, total_length, buffer);
+      }
+      break;
+    case ARC_OPERAND_UNCONDB :
+      break;
+    case ARC_OPERAND_UNCONDI :
+      break;
+    case ARC_OPERAND_UNCONDJ :
+      break;
+    case ARC_OPERAND_VBIT :
+      break;
+    case ARC_OPERAND_ZBIT :
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
+	       opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+int arc_cgen_extract_operand
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+
+/* Main entry point for operand extraction.
+   The result is <= 0 for error, >0 for success.
+   ??? Actual values aren't well defined right now.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.  */
+
+int
+arc_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
+{
+  /* Assume success (for those operands that are nops).  */
+  int length = 1;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case ARC_OPERAND_EXDI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
+      break;
+    case ARC_OPERAND_F :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
+      break;
+    case ARC_OPERAND_F0 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
+      break;
+    case ARC_OPERAND_F1 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
+      break;
+    case ARC_OPERAND_F1F :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_F);
+      break;
+    case ARC_OPERAND_GP :
+      break;
+    case ARC_OPERAND_LDODI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 1, 32, total_length, pc, & fields->f_LDODi);
+      break;
+    case ARC_OPERAND_LDRDI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 1, 32, total_length, pc, & fields->f_LDRDi);
+      break;
+    case ARC_OPERAND_NE :
+      break;
+    case ARC_OPERAND_PCL :
+      break;
+    case ARC_OPERAND_QCONDB :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 5, 32, total_length, pc, & fields->f_cond_Q);
+      break;
+    case ARC_OPERAND_QCONDI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 5, 32, total_length, pc, & fields->f_cond_Q);
+      break;
+    case ARC_OPERAND_QCONDJ :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 5, 32, total_length, pc, & fields->f_cond_Q);
+      break;
+    case ARC_OPERAND_R0 :
+      break;
+    case ARC_OPERAND_R31 :
+      break;
+    case ARC_OPERAND_RA :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 6, 32, total_length, pc, & fields->f_op_A);
+      break;
+    case ARC_OPERAND_RA_0 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 6, 32, total_length, pc, & fields->f_op_A);
+      break;
+    case ARC_OPERAND_RB :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_op__b);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_B_5_3);
+        if (length <= 0) break;
+{
+  FLD (f_op_B) = ((FLD (f_op__b)) | (((FLD (f_B_5_3)) << (3))));
+}
+      }
+      break;
+    case ARC_OPERAND_RB_0 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_op__b);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 3, 32, total_length, pc, & fields->f_B_5_3);
+        if (length <= 0) break;
+{
+  FLD (f_op_B) = ((FLD (f_op__b)) | (((FLD (f_B_5_3)) << (3))));
+}
+      }
+      break;
+    case ARC_OPERAND_RC :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_op_C);
+      break;
+    case ARC_OPERAND_RC_ILINK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_op_Cj);
+      break;
+    case ARC_OPERAND_RC_NOILINK :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_op_Cj);
+      break;
+    case ARC_OPERAND_R_A :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_op__a);
+      break;
+    case ARC_OPERAND_R_B :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_op__b);
+      break;
+    case ARC_OPERAND_R_C :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 3, 32, total_length, pc, & fields->f_op__c);
+      break;
+    case ARC_OPERAND_RCC :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 4, 32, total_length, pc, & fields->f_brcond);
+      break;
+    case ARC_OPERAND_RCCS :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_brscond);
+      break;
+    case ARC_OPERAND_RH :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 3, 32, total_length, pc, & fields->f_h_2_0);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_h_5_3);
+        if (length <= 0) break;
+{
+  FLD (f_op_h) = ((FLD (f_h_2_0)) | (((FLD (f_h_5_3)) << (3))));
+}
+      }
+      break;
+    case ARC_OPERAND_SP :
+      break;
+    case ARC_OPERAND_STODI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 1, 32, total_length, pc, & fields->f_STODi);
+      break;
+    case ARC_OPERAND_U6 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_u6);
+      break;
+    case ARC_OPERAND_U6X2 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & value);
+        value = ((value) << (1));
+        fields->f_u6x2 = value;
+      }
+      break;
+    case ARC_OPERAND__AW :
+      break;
+    case ARC_OPERAND__L :
+      break;
+    case ARC_OPERAND__S :
+      break;
+    case ARC_OPERAND_CBIT :
+      break;
+    case ARC_OPERAND_DELAY_N :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 26, 1, 32, total_length, pc, & fields->f_delay_N);
+      break;
+    case ARC_OPERAND_DUMMY_OP :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_dummy);
+      break;
+    case ARC_OPERAND_I2COND :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 2, 32, total_length, pc, & fields->f_cond_i2);
+      break;
+    case ARC_OPERAND_I3COND :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 3, 32, total_length, pc, & fields->f_cond_i3);
+      break;
+    case ARC_OPERAND_LABEL10 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 7, 9, 32, total_length, pc, & value);
+        value = ((((value) << (1))) + (((pc) & (-4))));
+        fields->f_rel10 = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL13A :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 5, 11, 32, total_length, pc, & value);
+        value = ((((value) << (2))) + (((pc) & (-4))));
+        fields->f_rel13bl = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL21 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 10, 32, total_length, pc, & fields->f_d21l);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, pc, & fields->f_d21h);
+        if (length <= 0) break;
+{
+  FLD (f_rel21) = ((((((FLD (f_d21l)) << (1))) | (((FLD (f_d21h)) << (11))))) + (((pc) & (-4))));
+}
+      }
+      break;
+    case ARC_OPERAND_LABEL21A :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 9, 32, total_length, pc, & fields->f_d21bl);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 10, 32, total_length, pc, & fields->f_d21h);
+        if (length <= 0) break;
+{
+  FLD (f_rel21bl) = ((((((FLD (f_d21bl)) << (2))) | (((FLD (f_d21h)) << (11))))) + (((pc) & (-4))));
+}
+      }
+      break;
+    case ARC_OPERAND_LABEL25 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 10, 32, total_length, pc, & fields->f_d21l);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 10, 32, total_length, pc, & fields->f_d25m);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, pc, & fields->f_d25h);
+        if (length <= 0) break;
+{
+  FLD (f_rel25) = ((((((((FLD (f_d21l)) << (1))) | (((FLD (f_d25m)) << (11))))) | (((FLD (f_d25h)) << (21))))) + (((pc) & (-4))));
+}
+      }
+      break;
+    case ARC_OPERAND_LABEL25A :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 9, 32, total_length, pc, & fields->f_d21bl);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 10, 32, total_length, pc, & fields->f_d25m);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 28, 4, 32, total_length, pc, & fields->f_d25h);
+        if (length <= 0) break;
+{
+  FLD (f_rel25bl) = ((((((((FLD (f_d21bl)) << (2))) | (((FLD (f_d25m)) << (11))))) | (((FLD (f_d25h)) << (21))))) + (((pc) & (-4))));
+}
+      }
+      break;
+    case ARC_OPERAND_LABEL7 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 10, 6, 32, total_length, pc, & value);
+        value = ((((value) << (1))) + (((pc) & (-4))));
+        fields->f_rel7 = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL8 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 9, 7, 32, total_length, pc, & value);
+        value = ((((value) << (1))) + (((pc) & (-4))));
+        fields->f_rel8 = value;
+      }
+      break;
+    case ARC_OPERAND_LABEL9 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 7, 32, total_length, pc, & fields->f_d9l);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, pc, & fields->f_d9h);
+        if (length <= 0) break;
+{
+  FLD (f_rel9) = ((((((FLD (f_d9l)) << (1))) | (((FLD (f_d9h)) << (8))))) + (((pc) & (-4))));
+}
+      }
+      break;
+    case ARC_OPERAND_LBIT :
+      break;
+    case ARC_OPERAND_NBIT :
+      break;
+    case ARC_OPERAND_S12 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_u6);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, pc, & fields->f_s12h);
+        if (length <= 0) break;
+{
+  FLD (f_s12) = ((FLD (f_u6)) | (((FLD (f_s12h)) << (6))));
+}
+      }
+      break;
+    case ARC_OPERAND_S12X2 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 6, 32, total_length, pc, & fields->f_u6);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 26, 6, 32, total_length, pc, & fields->f_s12h);
+        if (length <= 0) break;
+{
+  FLD (f_s12x2) = ((((FLD (f_u6)) << (1))) | (((FLD (f_s12h)) << (7))));
+}
+      }
+      break;
+    case ARC_OPERAND_S1BIT :
+      break;
+    case ARC_OPERAND_S2BIT :
+      break;
+    case ARC_OPERAND_S9 :
+      {
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_u8);
+        if (length <= 0) break;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 1, 32, total_length, pc, & fields->f_d9h);
+        if (length <= 0) break;
+{
+  FLD (f_s9) = ((FLD (f_u8)) | (((FLD (f_d9h)) << (8))));
+}
+      }
+      break;
+    case ARC_OPERAND_S9X4 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & value);
+        value = ((value) << (2));
+        fields->f_s9x4 = value;
+      }
+      break;
+    case ARC_OPERAND_SC_S9_ :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & value);
+        value = ((value) << (2));
+        fields->f_s9x4 = value;
+      }
+      break;
+    case ARC_OPERAND_SC_S9B :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & fields->f_s9x1);
+      break;
+    case ARC_OPERAND_SC_S9W :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 7, 9, 32, total_length, pc, & value);
+        value = ((value) << (1));
+        fields->f_s9x2 = value;
+      }
+      break;
+    case ARC_OPERAND_SC_U5_ :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & value);
+        value = ((value) << (2));
+        fields->f_u5x4 = value;
+      }
+      break;
+    case ARC_OPERAND_SC_U5B :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_u5);
+      break;
+    case ARC_OPERAND_SC_U5W :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & value);
+        value = ((value) << (1));
+        fields->f_u5x2 = value;
+      }
+      break;
+    case ARC_OPERAND_TRAPNUM :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_trapnum);
+      break;
+    case ARC_OPERAND_U3 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 3, 32, total_length, pc, & fields->f_u3);
+      break;
+    case ARC_OPERAND_U5 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_u5);
+      break;
+    case ARC_OPERAND_U5X4 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & value);
+        value = ((value) << (2));
+        fields->f_u5x4 = value;
+      }
+      break;
+    case ARC_OPERAND_U7 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 7, 32, total_length, pc, & fields->f_u7);
+      break;
+    case ARC_OPERAND_U8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_u8);
+      break;
+    case ARC_OPERAND_U8X4 :
+      {
+        long value;
+        length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & value);
+        value = ((value) << (2));
+        fields->f_u8x4 = value;
+      }
+      break;
+    case ARC_OPERAND_UNCONDB :
+      break;
+    case ARC_OPERAND_UNCONDI :
+      break;
+    case ARC_OPERAND_UNCONDJ :
+      break;
+    case ARC_OPERAND_VBIT :
+      break;
+    case ARC_OPERAND_ZBIT :
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
+	       opindex);
+      abort ();
+    }
+
+  return length;
+}
+
+cgen_insert_fn * const arc_cgen_insert_handlers[] = 
+{
+  insert_insn_normal,
+};
+
+cgen_extract_fn * const arc_cgen_extract_handlers[] = 
+{
+  extract_insn_normal,
+};
+
+int arc_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma arc_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+
+/* Getting values from cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they return.
+   TODO: floating point, inlining support, remove cases where result type
+   not appropriate.  */
+
+int
+arc_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
+{
+  int value;
+
+  switch (opindex)
+    {
+    case ARC_OPERAND_EXDI :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_F :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_F0 :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_F1 :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_F1F :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_GP :
+      value = 0;
+      break;
+    case ARC_OPERAND_LDODI :
+      value = fields->f_LDODi;
+      break;
+    case ARC_OPERAND_LDRDI :
+      value = fields->f_LDRDi;
+      break;
+    case ARC_OPERAND_NE :
+      value = 0;
+      break;
+    case ARC_OPERAND_PCL :
+      value = 0;
+      break;
+    case ARC_OPERAND_QCONDB :
+      value = fields->f_cond_Q;
+      break;
+    case ARC_OPERAND_QCONDI :
+      value = fields->f_cond_Q;
+      break;
+    case ARC_OPERAND_QCONDJ :
+      value = fields->f_cond_Q;
+      break;
+    case ARC_OPERAND_R0 :
+      value = 0;
+      break;
+    case ARC_OPERAND_R31 :
+      value = 0;
+      break;
+    case ARC_OPERAND_RA :
+      value = fields->f_op_A;
+      break;
+    case ARC_OPERAND_RA_0 :
+      value = fields->f_op_A;
+      break;
+    case ARC_OPERAND_RB :
+      value = fields->f_op_B;
+      break;
+    case ARC_OPERAND_RB_0 :
+      value = fields->f_op_B;
+      break;
+    case ARC_OPERAND_RC :
+      value = fields->f_op_C;
+      break;
+    case ARC_OPERAND_RC_ILINK :
+      value = fields->f_op_Cj;
+      break;
+    case ARC_OPERAND_RC_NOILINK :
+      value = fields->f_op_Cj;
+      break;
+    case ARC_OPERAND_R_A :
+      value = fields->f_op__a;
+      break;
+    case ARC_OPERAND_R_B :
+      value = fields->f_op__b;
+      break;
+    case ARC_OPERAND_R_C :
+      value = fields->f_op__c;
+      break;
+    case ARC_OPERAND_RCC :
+      value = fields->f_brcond;
+      break;
+    case ARC_OPERAND_RCCS :
+      value = fields->f_brscond;
+      break;
+    case ARC_OPERAND_RH :
+      value = fields->f_op_h;
+      break;
+    case ARC_OPERAND_SP :
+      value = 0;
+      break;
+    case ARC_OPERAND_STODI :
+      value = fields->f_STODi;
+      break;
+    case ARC_OPERAND_U6 :
+      value = fields->f_u6;
+      break;
+    case ARC_OPERAND_U6X2 :
+      value = fields->f_u6x2;
+      break;
+    case ARC_OPERAND__AW :
+      value = 0;
+      break;
+    case ARC_OPERAND__L :
+      value = 0;
+      break;
+    case ARC_OPERAND__S :
+      value = 0;
+      break;
+    case ARC_OPERAND_CBIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_DELAY_N :
+      value = fields->f_delay_N;
+      break;
+    case ARC_OPERAND_DUMMY_OP :
+      value = fields->f_dummy;
+      break;
+    case ARC_OPERAND_I2COND :
+      value = fields->f_cond_i2;
+      break;
+    case ARC_OPERAND_I3COND :
+      value = fields->f_cond_i3;
+      break;
+    case ARC_OPERAND_LABEL10 :
+      value = fields->f_rel10;
+      break;
+    case ARC_OPERAND_LABEL13A :
+      value = fields->f_rel13bl;
+      break;
+    case ARC_OPERAND_LABEL21 :
+      value = fields->f_rel21;
+      break;
+    case ARC_OPERAND_LABEL21A :
+      value = fields->f_rel21bl;
+      break;
+    case ARC_OPERAND_LABEL25 :
+      value = fields->f_rel25;
+      break;
+    case ARC_OPERAND_LABEL25A :
+      value = fields->f_rel25bl;
+      break;
+    case ARC_OPERAND_LABEL7 :
+      value = fields->f_rel7;
+      break;
+    case ARC_OPERAND_LABEL8 :
+      value = fields->f_rel8;
+      break;
+    case ARC_OPERAND_LABEL9 :
+      value = fields->f_rel9;
+      break;
+    case ARC_OPERAND_LBIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_NBIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_S12 :
+      value = fields->f_s12;
+      break;
+    case ARC_OPERAND_S12X2 :
+      value = fields->f_s12x2;
+      break;
+    case ARC_OPERAND_S1BIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_S2BIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_S9 :
+      value = fields->f_s9;
+      break;
+    case ARC_OPERAND_S9X4 :
+      value = fields->f_s9x4;
+      break;
+    case ARC_OPERAND_SC_S9_ :
+      value = fields->f_s9x4;
+      break;
+    case ARC_OPERAND_SC_S9B :
+      value = fields->f_s9x1;
+      break;
+    case ARC_OPERAND_SC_S9W :
+      value = fields->f_s9x2;
+      break;
+    case ARC_OPERAND_SC_U5_ :
+      value = fields->f_u5x4;
+      break;
+    case ARC_OPERAND_SC_U5B :
+      value = fields->f_u5;
+      break;
+    case ARC_OPERAND_SC_U5W :
+      value = fields->f_u5x2;
+      break;
+    case ARC_OPERAND_TRAPNUM :
+      value = fields->f_trapnum;
+      break;
+    case ARC_OPERAND_U3 :
+      value = fields->f_u3;
+      break;
+    case ARC_OPERAND_U5 :
+      value = fields->f_u5;
+      break;
+    case ARC_OPERAND_U5X4 :
+      value = fields->f_u5x4;
+      break;
+    case ARC_OPERAND_U7 :
+      value = fields->f_u7;
+      break;
+    case ARC_OPERAND_U8 :
+      value = fields->f_u8;
+      break;
+    case ARC_OPERAND_U8X4 :
+      value = fields->f_u8x4;
+      break;
+    case ARC_OPERAND_UNCONDB :
+      value = 0;
+      break;
+    case ARC_OPERAND_UNCONDI :
+      value = 0;
+      break;
+    case ARC_OPERAND_UNCONDJ :
+      value = 0;
+      break;
+    case ARC_OPERAND_VBIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_ZBIT :
+      value = 0;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
+		       opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+bfd_vma
+arc_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
+{
+  bfd_vma value;
+
+  switch (opindex)
+    {
+    case ARC_OPERAND_EXDI :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_F :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_F0 :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_F1 :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_F1F :
+      value = fields->f_F;
+      break;
+    case ARC_OPERAND_GP :
+      value = 0;
+      break;
+    case ARC_OPERAND_LDODI :
+      value = fields->f_LDODi;
+      break;
+    case ARC_OPERAND_LDRDI :
+      value = fields->f_LDRDi;
+      break;
+    case ARC_OPERAND_NE :
+      value = 0;
+      break;
+    case ARC_OPERAND_PCL :
+      value = 0;
+      break;
+    case ARC_OPERAND_QCONDB :
+      value = fields->f_cond_Q;
+      break;
+    case ARC_OPERAND_QCONDI :
+      value = fields->f_cond_Q;
+      break;
+    case ARC_OPERAND_QCONDJ :
+      value = fields->f_cond_Q;
+      break;
+    case ARC_OPERAND_R0 :
+      value = 0;
+      break;
+    case ARC_OPERAND_R31 :
+      value = 0;
+      break;
+    case ARC_OPERAND_RA :
+      value = fields->f_op_A;
+      break;
+    case ARC_OPERAND_RA_0 :
+      value = fields->f_op_A;
+      break;
+    case ARC_OPERAND_RB :
+      value = fields->f_op_B;
+      break;
+    case ARC_OPERAND_RB_0 :
+      value = fields->f_op_B;
+      break;
+    case ARC_OPERAND_RC :
+      value = fields->f_op_C;
+      break;
+    case ARC_OPERAND_RC_ILINK :
+      value = fields->f_op_Cj;
+      break;
+    case ARC_OPERAND_RC_NOILINK :
+      value = fields->f_op_Cj;
+      break;
+    case ARC_OPERAND_R_A :
+      value = fields->f_op__a;
+      break;
+    case ARC_OPERAND_R_B :
+      value = fields->f_op__b;
+      break;
+    case ARC_OPERAND_R_C :
+      value = fields->f_op__c;
+      break;
+    case ARC_OPERAND_RCC :
+      value = fields->f_brcond;
+      break;
+    case ARC_OPERAND_RCCS :
+      value = fields->f_brscond;
+      break;
+    case ARC_OPERAND_RH :
+      value = fields->f_op_h;
+      break;
+    case ARC_OPERAND_SP :
+      value = 0;
+      break;
+    case ARC_OPERAND_STODI :
+      value = fields->f_STODi;
+      break;
+    case ARC_OPERAND_U6 :
+      value = fields->f_u6;
+      break;
+    case ARC_OPERAND_U6X2 :
+      value = fields->f_u6x2;
+      break;
+    case ARC_OPERAND__AW :
+      value = 0;
+      break;
+    case ARC_OPERAND__L :
+      value = 0;
+      break;
+    case ARC_OPERAND__S :
+      value = 0;
+      break;
+    case ARC_OPERAND_CBIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_DELAY_N :
+      value = fields->f_delay_N;
+      break;
+    case ARC_OPERAND_DUMMY_OP :
+      value = fields->f_dummy;
+      break;
+    case ARC_OPERAND_I2COND :
+      value = fields->f_cond_i2;
+      break;
+    case ARC_OPERAND_I3COND :
+      value = fields->f_cond_i3;
+      break;
+    case ARC_OPERAND_LABEL10 :
+      value = fields->f_rel10;
+      break;
+    case ARC_OPERAND_LABEL13A :
+      value = fields->f_rel13bl;
+      break;
+    case ARC_OPERAND_LABEL21 :
+      value = fields->f_rel21;
+      break;
+    case ARC_OPERAND_LABEL21A :
+      value = fields->f_rel21bl;
+      break;
+    case ARC_OPERAND_LABEL25 :
+      value = fields->f_rel25;
+      break;
+    case ARC_OPERAND_LABEL25A :
+      value = fields->f_rel25bl;
+      break;
+    case ARC_OPERAND_LABEL7 :
+      value = fields->f_rel7;
+      break;
+    case ARC_OPERAND_LABEL8 :
+      value = fields->f_rel8;
+      break;
+    case ARC_OPERAND_LABEL9 :
+      value = fields->f_rel9;
+      break;
+    case ARC_OPERAND_LBIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_NBIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_S12 :
+      value = fields->f_s12;
+      break;
+    case ARC_OPERAND_S12X2 :
+      value = fields->f_s12x2;
+      break;
+    case ARC_OPERAND_S1BIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_S2BIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_S9 :
+      value = fields->f_s9;
+      break;
+    case ARC_OPERAND_S9X4 :
+      value = fields->f_s9x4;
+      break;
+    case ARC_OPERAND_SC_S9_ :
+      value = fields->f_s9x4;
+      break;
+    case ARC_OPERAND_SC_S9B :
+      value = fields->f_s9x1;
+      break;
+    case ARC_OPERAND_SC_S9W :
+      value = fields->f_s9x2;
+      break;
+    case ARC_OPERAND_SC_U5_ :
+      value = fields->f_u5x4;
+      break;
+    case ARC_OPERAND_SC_U5B :
+      value = fields->f_u5;
+      break;
+    case ARC_OPERAND_SC_U5W :
+      value = fields->f_u5x2;
+      break;
+    case ARC_OPERAND_TRAPNUM :
+      value = fields->f_trapnum;
+      break;
+    case ARC_OPERAND_U3 :
+      value = fields->f_u3;
+      break;
+    case ARC_OPERAND_U5 :
+      value = fields->f_u5;
+      break;
+    case ARC_OPERAND_U5X4 :
+      value = fields->f_u5x4;
+      break;
+    case ARC_OPERAND_U7 :
+      value = fields->f_u7;
+      break;
+    case ARC_OPERAND_U8 :
+      value = fields->f_u8;
+      break;
+    case ARC_OPERAND_U8X4 :
+      value = fields->f_u8x4;
+      break;
+    case ARC_OPERAND_UNCONDB :
+      value = 0;
+      break;
+    case ARC_OPERAND_UNCONDI :
+      value = 0;
+      break;
+    case ARC_OPERAND_UNCONDJ :
+      value = 0;
+      break;
+    case ARC_OPERAND_VBIT :
+      value = 0;
+      break;
+    case ARC_OPERAND_ZBIT :
+      value = 0;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
+		       opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+void arc_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void arc_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
+
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they accept.
+   TODO: floating point, inlining support, remove cases where argument type
+   not appropriate.  */
+
+void
+arc_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
+{
+  switch (opindex)
+    {
+    case ARC_OPERAND_EXDI :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_F :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_F0 :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_F1 :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_F1F :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_GP :
+      break;
+    case ARC_OPERAND_LDODI :
+      fields->f_LDODi = value;
+      break;
+    case ARC_OPERAND_LDRDI :
+      fields->f_LDRDi = value;
+      break;
+    case ARC_OPERAND_NE :
+      break;
+    case ARC_OPERAND_PCL :
+      break;
+    case ARC_OPERAND_QCONDB :
+      fields->f_cond_Q = value;
+      break;
+    case ARC_OPERAND_QCONDI :
+      fields->f_cond_Q = value;
+      break;
+    case ARC_OPERAND_QCONDJ :
+      fields->f_cond_Q = value;
+      break;
+    case ARC_OPERAND_R0 :
+      break;
+    case ARC_OPERAND_R31 :
+      break;
+    case ARC_OPERAND_RA :
+      fields->f_op_A = value;
+      break;
+    case ARC_OPERAND_RA_0 :
+      fields->f_op_A = value;
+      break;
+    case ARC_OPERAND_RB :
+      fields->f_op_B = value;
+      break;
+    case ARC_OPERAND_RB_0 :
+      fields->f_op_B = value;
+      break;
+    case ARC_OPERAND_RC :
+      fields->f_op_C = value;
+      break;
+    case ARC_OPERAND_RC_ILINK :
+      fields->f_op_Cj = value;
+      break;
+    case ARC_OPERAND_RC_NOILINK :
+      fields->f_op_Cj = value;
+      break;
+    case ARC_OPERAND_R_A :
+      fields->f_op__a = value;
+      break;
+    case ARC_OPERAND_R_B :
+      fields->f_op__b = value;
+      break;
+    case ARC_OPERAND_R_C :
+      fields->f_op__c = value;
+      break;
+    case ARC_OPERAND_RCC :
+      fields->f_brcond = value;
+      break;
+    case ARC_OPERAND_RCCS :
+      fields->f_brscond = value;
+      break;
+    case ARC_OPERAND_RH :
+      fields->f_op_h = value;
+      break;
+    case ARC_OPERAND_SP :
+      break;
+    case ARC_OPERAND_STODI :
+      fields->f_STODi = value;
+      break;
+    case ARC_OPERAND_U6 :
+      fields->f_u6 = value;
+      break;
+    case ARC_OPERAND_U6X2 :
+      fields->f_u6x2 = value;
+      break;
+    case ARC_OPERAND__AW :
+      break;
+    case ARC_OPERAND__L :
+      break;
+    case ARC_OPERAND__S :
+      break;
+    case ARC_OPERAND_CBIT :
+      break;
+    case ARC_OPERAND_DELAY_N :
+      fields->f_delay_N = value;
+      break;
+    case ARC_OPERAND_DUMMY_OP :
+      fields->f_dummy = value;
+      break;
+    case ARC_OPERAND_I2COND :
+      fields->f_cond_i2 = value;
+      break;
+    case ARC_OPERAND_I3COND :
+      fields->f_cond_i3 = value;
+      break;
+    case ARC_OPERAND_LABEL10 :
+      fields->f_rel10 = value;
+      break;
+    case ARC_OPERAND_LABEL13A :
+      fields->f_rel13bl = value;
+      break;
+    case ARC_OPERAND_LABEL21 :
+      fields->f_rel21 = value;
+      break;
+    case ARC_OPERAND_LABEL21A :
+      fields->f_rel21bl = value;
+      break;
+    case ARC_OPERAND_LABEL25 :
+      fields->f_rel25 = value;
+      break;
+    case ARC_OPERAND_LABEL25A :
+      fields->f_rel25bl = value;
+      break;
+    case ARC_OPERAND_LABEL7 :
+      fields->f_rel7 = value;
+      break;
+    case ARC_OPERAND_LABEL8 :
+      fields->f_rel8 = value;
+      break;
+    case ARC_OPERAND_LABEL9 :
+      fields->f_rel9 = value;
+      break;
+    case ARC_OPERAND_LBIT :
+      break;
+    case ARC_OPERAND_NBIT :
+      break;
+    case ARC_OPERAND_S12 :
+      fields->f_s12 = value;
+      break;
+    case ARC_OPERAND_S12X2 :
+      fields->f_s12x2 = value;
+      break;
+    case ARC_OPERAND_S1BIT :
+      break;
+    case ARC_OPERAND_S2BIT :
+      break;
+    case ARC_OPERAND_S9 :
+      fields->f_s9 = value;
+      break;
+    case ARC_OPERAND_S9X4 :
+      fields->f_s9x4 = value;
+      break;
+    case ARC_OPERAND_SC_S9_ :
+      fields->f_s9x4 = value;
+      break;
+    case ARC_OPERAND_SC_S9B :
+      fields->f_s9x1 = value;
+      break;
+    case ARC_OPERAND_SC_S9W :
+      fields->f_s9x2 = value;
+      break;
+    case ARC_OPERAND_SC_U5_ :
+      fields->f_u5x4 = value;
+      break;
+    case ARC_OPERAND_SC_U5B :
+      fields->f_u5 = value;
+      break;
+    case ARC_OPERAND_SC_U5W :
+      fields->f_u5x2 = value;
+      break;
+    case ARC_OPERAND_TRAPNUM :
+      fields->f_trapnum = value;
+      break;
+    case ARC_OPERAND_U3 :
+      fields->f_u3 = value;
+      break;
+    case ARC_OPERAND_U5 :
+      fields->f_u5 = value;
+      break;
+    case ARC_OPERAND_U5X4 :
+      fields->f_u5x4 = value;
+      break;
+    case ARC_OPERAND_U7 :
+      fields->f_u7 = value;
+      break;
+    case ARC_OPERAND_U8 :
+      fields->f_u8 = value;
+      break;
+    case ARC_OPERAND_U8X4 :
+      fields->f_u8x4 = value;
+      break;
+    case ARC_OPERAND_UNCONDB :
+      break;
+    case ARC_OPERAND_UNCONDI :
+      break;
+    case ARC_OPERAND_UNCONDJ :
+      break;
+    case ARC_OPERAND_VBIT :
+      break;
+    case ARC_OPERAND_ZBIT :
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+		       opindex);
+      abort ();
+  }
+}
+
+void
+arc_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
+{
+  switch (opindex)
+    {
+    case ARC_OPERAND_EXDI :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_F :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_F0 :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_F1 :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_F1F :
+      fields->f_F = value;
+      break;
+    case ARC_OPERAND_GP :
+      break;
+    case ARC_OPERAND_LDODI :
+      fields->f_LDODi = value;
+      break;
+    case ARC_OPERAND_LDRDI :
+      fields->f_LDRDi = value;
+      break;
+    case ARC_OPERAND_NE :
+      break;
+    case ARC_OPERAND_PCL :
+      break;
+    case ARC_OPERAND_QCONDB :
+      fields->f_cond_Q = value;
+      break;
+    case ARC_OPERAND_QCONDI :
+      fields->f_cond_Q = value;
+      break;
+    case ARC_OPERAND_QCONDJ :
+      fields->f_cond_Q = value;
+      break;
+    case ARC_OPERAND_R0 :
+      break;
+    case ARC_OPERAND_R31 :
+      break;
+    case ARC_OPERAND_RA :
+      fields->f_op_A = value;
+      break;
+    case ARC_OPERAND_RA_0 :
+      fields->f_op_A = value;
+      break;
+    case ARC_OPERAND_RB :
+      fields->f_op_B = value;
+      break;
+    case ARC_OPERAND_RB_0 :
+      fields->f_op_B = value;
+      break;
+    case ARC_OPERAND_RC :
+      fields->f_op_C = value;
+      break;
+    case ARC_OPERAND_RC_ILINK :
+      fields->f_op_Cj = value;
+      break;
+    case ARC_OPERAND_RC_NOILINK :
+      fields->f_op_Cj = value;
+      break;
+    case ARC_OPERAND_R_A :
+      fields->f_op__a = value;
+      break;
+    case ARC_OPERAND_R_B :
+      fields->f_op__b = value;
+      break;
+    case ARC_OPERAND_R_C :
+      fields->f_op__c = value;
+      break;
+    case ARC_OPERAND_RCC :
+      fields->f_brcond = value;
+      break;
+    case ARC_OPERAND_RCCS :
+      fields->f_brscond = value;
+      break;
+    case ARC_OPERAND_RH :
+      fields->f_op_h = value;
+      break;
+    case ARC_OPERAND_SP :
+      break;
+    case ARC_OPERAND_STODI :
+      fields->f_STODi = value;
+      break;
+    case ARC_OPERAND_U6 :
+      fields->f_u6 = value;
+      break;
+    case ARC_OPERAND_U6X2 :
+      fields->f_u6x2 = value;
+      break;
+    case ARC_OPERAND__AW :
+      break;
+    case ARC_OPERAND__L :
+      break;
+    case ARC_OPERAND__S :
+      break;
+    case ARC_OPERAND_CBIT :
+      break;
+    case ARC_OPERAND_DELAY_N :
+      fields->f_delay_N = value;
+      break;
+    case ARC_OPERAND_DUMMY_OP :
+      fields->f_dummy = value;
+      break;
+    case ARC_OPERAND_I2COND :
+      fields->f_cond_i2 = value;
+      break;
+    case ARC_OPERAND_I3COND :
+      fields->f_cond_i3 = value;
+      break;
+    case ARC_OPERAND_LABEL10 :
+      fields->f_rel10 = value;
+      break;
+    case ARC_OPERAND_LABEL13A :
+      fields->f_rel13bl = value;
+      break;
+    case ARC_OPERAND_LABEL21 :
+      fields->f_rel21 = value;
+      break;
+    case ARC_OPERAND_LABEL21A :
+      fields->f_rel21bl = value;
+      break;
+    case ARC_OPERAND_LABEL25 :
+      fields->f_rel25 = value;
+      break;
+    case ARC_OPERAND_LABEL25A :
+      fields->f_rel25bl = value;
+      break;
+    case ARC_OPERAND_LABEL7 :
+      fields->f_rel7 = value;
+      break;
+    case ARC_OPERAND_LABEL8 :
+      fields->f_rel8 = value;
+      break;
+    case ARC_OPERAND_LABEL9 :
+      fields->f_rel9 = value;
+      break;
+    case ARC_OPERAND_LBIT :
+      break;
+    case ARC_OPERAND_NBIT :
+      break;
+    case ARC_OPERAND_S12 :
+      fields->f_s12 = value;
+      break;
+    case ARC_OPERAND_S12X2 :
+      fields->f_s12x2 = value;
+      break;
+    case ARC_OPERAND_S1BIT :
+      break;
+    case ARC_OPERAND_S2BIT :
+      break;
+    case ARC_OPERAND_S9 :
+      fields->f_s9 = value;
+      break;
+    case ARC_OPERAND_S9X4 :
+      fields->f_s9x4 = value;
+      break;
+    case ARC_OPERAND_SC_S9_ :
+      fields->f_s9x4 = value;
+      break;
+    case ARC_OPERAND_SC_S9B :
+      fields->f_s9x1 = value;
+      break;
+    case ARC_OPERAND_SC_S9W :
+      fields->f_s9x2 = value;
+      break;
+    case ARC_OPERAND_SC_U5_ :
+      fields->f_u5x4 = value;
+      break;
+    case ARC_OPERAND_SC_U5B :
+      fields->f_u5 = value;
+      break;
+    case ARC_OPERAND_SC_U5W :
+      fields->f_u5x2 = value;
+      break;
+    case ARC_OPERAND_TRAPNUM :
+      fields->f_trapnum = value;
+      break;
+    case ARC_OPERAND_U3 :
+      fields->f_u3 = value;
+      break;
+    case ARC_OPERAND_U5 :
+      fields->f_u5 = value;
+      break;
+    case ARC_OPERAND_U5X4 :
+      fields->f_u5x4 = value;
+      break;
+    case ARC_OPERAND_U7 :
+      fields->f_u7 = value;
+      break;
+    case ARC_OPERAND_U8 :
+      fields->f_u8 = value;
+      break;
+    case ARC_OPERAND_U8X4 :
+      fields->f_u8x4 = value;
+      break;
+    case ARC_OPERAND_UNCONDB :
+      break;
+    case ARC_OPERAND_UNCONDI :
+      break;
+    case ARC_OPERAND_UNCONDJ :
+      break;
+    case ARC_OPERAND_VBIT :
+      break;
+    case ARC_OPERAND_ZBIT :
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+		       opindex);
+      abort ();
+  }
+}
+
+/* Function to call before using the instruction builder tables.  */
+
+void
+arc_cgen_init_ibld_table (CGEN_CPU_DESC cd)
+{
+  cd->insert_handlers = & arc_cgen_insert_handlers[0];
+  cd->extract_handlers = & arc_cgen_extract_handlers[0];
+
+  cd->insert_operand = arc_cgen_insert_operand;
+  cd->extract_operand = arc_cgen_extract_operand;
+
+  cd->get_int_operand = arc_cgen_get_int_operand;
+  cd->set_int_operand = arc_cgen_set_int_operand;
+  cd->get_vma_operand = arc_cgen_get_vma_operand;
+  cd->set_vma_operand = arc_cgen_set_vma_operand;
+}
diff --git a/opcodes/arc-opc.h b/opcodes/arc-opc.h
new file mode 100644
index 0000000..0a020b2
--- /dev/null
+++ b/opcodes/arc-opc.h
@@ -0,0 +1,313 @@
+/* Instruction opcode header for arc.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef ARC_OPC_H
+#define ARC_OPC_H
+
+/* -- opc.h */
+
+#undef  CGEN_DIS_HASH_SIZE
+#define CGEN_DIS_HASH_SIZE 1024
+#undef  CGEN_DIS_HASH
+#define CGEN_DIS_HASH(buffer, value, big_p) \
+  arc_cgen_dis_hash (buffer, big_p)
+extern unsigned int arc_cgen_dis_hash (const char *, int);
+/* Override CGEN_INSN_BITSIZE for sim/common/cgen-trace.c .
+   insn extraction for simulation is fine with 32 bits, since we fetch long
+   immediates as part of the semantics if required, but for disassembly
+   we must make sure we read all the bits while we have the information how
+   to read them.  */
+#define CGEN_INSN_DISASM_BITSIZE(insn) 64
+extern char limm_str[];
+
+/* cgen can't generate correct decoders for variable-length insns,
+   so we have it generate a decoder that assumes all insns are 32 bit.
+   And even if the decoder generator bug were fixed, having the decoder
+   understand long immediates would be messy.
+   The simulator calculates instruction sizes as part of the semantics.
+   For disassembly, we redefine CGEN_EXTRACT_FN so that we can correct
+   the calculated instruction length.  */
+#undef CGEN_EXTRACT_FN
+#define CGEN_EXTRACT_FN(cd, insn) ARC_CGEN_EXTRACT_FN
+extern int arc_insn_length (unsigned long insn_value, const CGEN_INSN *insn,
+			   CGEN_EXTRACT_INFO *info, bfd_vma pc);
+static inline int
+ARC_CGEN_EXTRACT_FN (CGEN_CPU_DESC cd, const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *info, CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields, bfd_vma pc)
+{
+  static int initialized = 0;
+  /* ??? There is no suitable hook for one-time initialization.  */
+  if (!initialized)
+    {
+      static CGEN_KEYWORD_ENTRY arc_cgen_opval_limm_entry0 =
+	{ limm_str, 62, {0, {{{0, 0}}}}, 0, 0 };
+      static CGEN_KEYWORD_ENTRY arc_cgen_opval_limm_entry1 =
+	{ limm_str, 62, {0, {{{0, 0}}}}, 0, 0 };
+
+      cgen_keyword_add (&arc_cgen_opval_cr_names, &arc_cgen_opval_limm_entry0);
+      cgen_keyword_add (&arc_cgen_opval_h_noilink, &arc_cgen_opval_limm_entry1);
+      initialized = 1;
+    }
+  /* ??? sim/common/cgen-trace.c:sim_cgen_disassemble_insn uses its own
+     home-brewn instruction target-to-host conversion, which gets the
+     endianness wrong for ARC.  */
+  if (cd->endian == CGEN_ENDIAN_LITTLE)
+    insn_value = ((insn_value >> 16) & 0xffff) | (insn_value << 16);
+
+  /* First, do the normal extract handler call, but ignore its value.  */
+  ((cd)->extract_handlers[(insn)->opcode->handlers.extract]
+    (cd, insn, info, insn_value, fields, pc));
+  /* Now calculate the actual insn length, and extract any long immediate
+     if present.  */
+  return arc_insn_length (insn_value, insn, info, pc);
+}
+
+/* -- */
+/* Enum declaration for arc instruction types.  */
+typedef enum cgen_insn_type {
+  ARC_INSN_INVALID, ARC_INSN_B_S, ARC_INSN_BCC_S, ARC_INSN_BRCC_S
+ , ARC_INSN_BCC_L, ARC_INSN_BCC_L_D, ARC_INSN_B_L, ARC_INSN_B_L_D
+ , ARC_INSN_BRCC_RC, ARC_INSN_BRCC_RC_D, ARC_INSN_BRCC_U6, ARC_INSN_BRCC_U6_D
+ , ARC_INSN_BL_S, ARC_INSN_BLCC, ARC_INSN_BLCC_D, ARC_INSN_BL
+ , ARC_INSN_BL_D, ARC_INSN_LD_ABS, ARC_INSN_LD__AW_ABS, ARC_INSN_LD_AB_ABS
+ , ARC_INSN_LD_AS_ABS, ARC_INSN_LD_ABC, ARC_INSN_LD__AW_ABC, ARC_INSN_LD_AB_ABC
+ , ARC_INSN_LD_AS_ABC, ARC_INSN_LD_S_ABC, ARC_INSN_LD_S_ABU, ARC_INSN_LD_S_ABSP
+ , ARC_INSN_LD_S_GPREL, ARC_INSN_LD_S_PCREL, ARC_INSN_LDB_ABS, ARC_INSN_LDB__AW_ABS
+ , ARC_INSN_LDB_AB_ABS, ARC_INSN_LDB_AS_ABS, ARC_INSN_LDB_ABC, ARC_INSN_LDB__AW_ABC
+ , ARC_INSN_LDB_AB_ABC, ARC_INSN_LDB_AS_ABC, ARC_INSN_LDB_S_ABC, ARC_INSN_LDB_S_ABU
+ , ARC_INSN_LDB_S_ABSP, ARC_INSN_LDB_S_GPREL, ARC_INSN_LDB_X_ABS, ARC_INSN_LDB__AW_X_ABS
+ , ARC_INSN_LDB_AB_X_ABS, ARC_INSN_LDB_AS_X_ABS, ARC_INSN_LDB_X_ABC, ARC_INSN_LDB__AW_X_ABC
+ , ARC_INSN_LDB_AB_X_ABC, ARC_INSN_LDB_AS_X_ABC, ARC_INSN_LDW_ABS, ARC_INSN_LDW__AW_ABS
+ , ARC_INSN_LDW_AB_ABS, ARC_INSN_LDW_AS_ABS, ARC_INSN_LDW_ABC, ARC_INSN_LDW__AW_ABC
+ , ARC_INSN_LDW_AB_ABC, ARC_INSN_LDW_AS_ABC, ARC_INSN_LDW_S_ABC, ARC_INSN_LDW_S_ABU
+ , ARC_INSN_LDW_S_GPREL, ARC_INSN_LDW_X_ABS, ARC_INSN_LDW__AW_X_ABS, ARC_INSN_LDW_AB_X_ABS
+ , ARC_INSN_LDW_AS_X_ABS, ARC_INSN_LDW_X_ABC, ARC_INSN_LDW__AW_X_ABC, ARC_INSN_LDW_AB_X_ABC
+ , ARC_INSN_LDW_AS_X_ABC, ARC_INSN_LDW_S_X_ABU, ARC_INSN_ST_ABS, ARC_INSN_ST__AW_ABS
+ , ARC_INSN_ST_AB_ABS, ARC_INSN_ST_AS_ABS, ARC_INSN_ST_S_ABU, ARC_INSN_ST_S_ABSP
+ , ARC_INSN_STB_ABS, ARC_INSN_STB__AW_ABS, ARC_INSN_STB_AB_ABS, ARC_INSN_STB_AS_ABS
+ , ARC_INSN_STB_S_ABU, ARC_INSN_STB_S_ABSP, ARC_INSN_STW_ABS, ARC_INSN_STW__AW_ABS
+ , ARC_INSN_STW_AB_ABS, ARC_INSN_STW_AS_ABS, ARC_INSN_STW_S_ABU, ARC_INSN_ADD_L_S12__RA_
+ , ARC_INSN_ADD_CCU6__RA_, ARC_INSN_ADD_L_U6__RA_, ARC_INSN_ADD_L_R_R__RA__RC, ARC_INSN_ADD_CC__RA__RC
+ , ARC_INSN_ADD_S_ABC, ARC_INSN_ADD_S_CBU3, ARC_INSN_ADD_S_MCAH, ARC_INSN_ADD_S_ABSP
+ , ARC_INSN_ADD_S_ASSPSP, ARC_INSN_ADD_S_GP, ARC_INSN_ADD_S_R_U7, ARC_INSN_ADC_L_S12__RA_
+ , ARC_INSN_ADC_CCU6__RA_, ARC_INSN_ADC_L_U6__RA_, ARC_INSN_ADC_L_R_R__RA__RC, ARC_INSN_ADC_CC__RA__RC
+ , ARC_INSN_SUB_L_S12__RA_, ARC_INSN_SUB_CCU6__RA_, ARC_INSN_SUB_L_U6__RA_, ARC_INSN_SUB_L_R_R__RA__RC
+ , ARC_INSN_SUB_CC__RA__RC, ARC_INSN_SUB_S_CBU3, ARC_INSN_I16_GO_SUB_S_GO, ARC_INSN_SUB_S_GO_SUB_NE
+ , ARC_INSN_SUB_S_SSB, ARC_INSN_SUB_S_ASSPSP, ARC_INSN_SBC_L_S12__RA_, ARC_INSN_SBC_CCU6__RA_
+ , ARC_INSN_SBC_L_U6__RA_, ARC_INSN_SBC_L_R_R__RA__RC, ARC_INSN_SBC_CC__RA__RC, ARC_INSN_AND_L_S12__RA_
+ , ARC_INSN_AND_CCU6__RA_, ARC_INSN_AND_L_U6__RA_, ARC_INSN_AND_L_R_R__RA__RC, ARC_INSN_AND_CC__RA__RC
+ , ARC_INSN_I16_GO_AND_S_GO, ARC_INSN_OR_L_S12__RA_, ARC_INSN_OR_CCU6__RA_, ARC_INSN_OR_L_U6__RA_
+ , ARC_INSN_OR_L_R_R__RA__RC, ARC_INSN_OR_CC__RA__RC, ARC_INSN_I16_GO_OR_S_GO, ARC_INSN_BIC_L_S12__RA_
+ , ARC_INSN_BIC_CCU6__RA_, ARC_INSN_BIC_L_U6__RA_, ARC_INSN_BIC_L_R_R__RA__RC, ARC_INSN_BIC_CC__RA__RC
+ , ARC_INSN_I16_GO_BIC_S_GO, ARC_INSN_XOR_L_S12__RA_, ARC_INSN_XOR_CCU6__RA_, ARC_INSN_XOR_L_U6__RA_
+ , ARC_INSN_XOR_L_R_R__RA__RC, ARC_INSN_XOR_CC__RA__RC, ARC_INSN_I16_GO_XOR_S_GO, ARC_INSN_MAX_L_S12__RA_
+ , ARC_INSN_MAX_CCU6__RA_, ARC_INSN_MAX_L_U6__RA_, ARC_INSN_MAX_L_R_R__RA__RC, ARC_INSN_MAX_CC__RA__RC
+ , ARC_INSN_MIN_L_S12__RA_, ARC_INSN_MIN_CCU6__RA_, ARC_INSN_MIN_L_U6__RA_, ARC_INSN_MIN_L_R_R__RA__RC
+ , ARC_INSN_MIN_CC__RA__RC, ARC_INSN_MOV_L_S12_, ARC_INSN_MOV_CCU6_, ARC_INSN_MOV_L_U6_
+ , ARC_INSN_MOV_L_R_R__RC, ARC_INSN_MOV_CC__RC, ARC_INSN_MOV_S_MCAH, ARC_INSN_MOV_S_MCAHB
+ , ARC_INSN_MOV_S_R_U7, ARC_INSN_TST_L_S12_, ARC_INSN_TST_CCU6_, ARC_INSN_TST_L_U6_
+ , ARC_INSN_TST_L_R_R__RC, ARC_INSN_TST_CC__RC, ARC_INSN_TST_S_GO, ARC_INSN_CMP_L_S12_
+ , ARC_INSN_CMP_CCU6_, ARC_INSN_CMP_L_U6_, ARC_INSN_CMP_L_R_R__RC, ARC_INSN_CMP_CC__RC
+ , ARC_INSN_CMP_S_MCAH, ARC_INSN_CMP_S_R_U7, ARC_INSN_RCMP_L_S12_, ARC_INSN_RCMP_CCU6_
+ , ARC_INSN_RCMP_L_U6_, ARC_INSN_RCMP_L_R_R__RC, ARC_INSN_RCMP_CC__RC, ARC_INSN_RSUB_L_S12__RA_
+ , ARC_INSN_RSUB_CCU6__RA_, ARC_INSN_RSUB_L_U6__RA_, ARC_INSN_RSUB_L_R_R__RA__RC, ARC_INSN_RSUB_CC__RA__RC
+ , ARC_INSN_BSET_L_S12__RA_, ARC_INSN_BSET_CCU6__RA_, ARC_INSN_BSET_L_U6__RA_, ARC_INSN_BSET_L_R_R__RA__RC
+ , ARC_INSN_BSET_CC__RA__RC, ARC_INSN_BSET_S_SSB, ARC_INSN_BCLR_L_S12__RA_, ARC_INSN_BCLR_CCU6__RA_
+ , ARC_INSN_BCLR_L_U6__RA_, ARC_INSN_BCLR_L_R_R__RA__RC, ARC_INSN_BCLR_CC__RA__RC, ARC_INSN_BCLR_S_SSB
+ , ARC_INSN_BTST_L_S12_, ARC_INSN_BTST_CCU6_, ARC_INSN_BTST_L_U6_, ARC_INSN_BTST_L_R_R__RC
+ , ARC_INSN_BTST_CC__RC, ARC_INSN_BTST_S_SSB, ARC_INSN_BXOR_L_S12__RA_, ARC_INSN_BXOR_CCU6__RA_
+ , ARC_INSN_BXOR_L_U6__RA_, ARC_INSN_BXOR_L_R_R__RA__RC, ARC_INSN_BXOR_CC__RA__RC, ARC_INSN_BMSK_L_S12__RA_
+ , ARC_INSN_BMSK_CCU6__RA_, ARC_INSN_BMSK_L_U6__RA_, ARC_INSN_BMSK_L_R_R__RA__RC, ARC_INSN_BMSK_CC__RA__RC
+ , ARC_INSN_BMSK_S_SSB, ARC_INSN_ADD1_L_S12__RA_, ARC_INSN_ADD1_CCU6__RA_, ARC_INSN_ADD1_L_U6__RA_
+ , ARC_INSN_ADD1_L_R_R__RA__RC, ARC_INSN_ADD1_CC__RA__RC, ARC_INSN_I16_GO_ADD1_S_GO, ARC_INSN_ADD2_L_S12__RA_
+ , ARC_INSN_ADD2_CCU6__RA_, ARC_INSN_ADD2_L_U6__RA_, ARC_INSN_ADD2_L_R_R__RA__RC, ARC_INSN_ADD2_CC__RA__RC
+ , ARC_INSN_I16_GO_ADD2_S_GO, ARC_INSN_ADD3_L_S12__RA_, ARC_INSN_ADD3_CCU6__RA_, ARC_INSN_ADD3_L_U6__RA_
+ , ARC_INSN_ADD3_L_R_R__RA__RC, ARC_INSN_ADD3_CC__RA__RC, ARC_INSN_I16_GO_ADD3_S_GO, ARC_INSN_SUB1_L_S12__RA_
+ , ARC_INSN_SUB1_CCU6__RA_, ARC_INSN_SUB1_L_U6__RA_, ARC_INSN_SUB1_L_R_R__RA__RC, ARC_INSN_SUB1_CC__RA__RC
+ , ARC_INSN_SUB2_L_S12__RA_, ARC_INSN_SUB2_CCU6__RA_, ARC_INSN_SUB2_L_U6__RA_, ARC_INSN_SUB2_L_R_R__RA__RC
+ , ARC_INSN_SUB2_CC__RA__RC, ARC_INSN_SUB3_L_S12__RA_, ARC_INSN_SUB3_CCU6__RA_, ARC_INSN_SUB3_L_U6__RA_
+ , ARC_INSN_SUB3_L_R_R__RA__RC, ARC_INSN_SUB3_CC__RA__RC, ARC_INSN_MPY_L_S12__RA_, ARC_INSN_MPY_CCU6__RA_
+ , ARC_INSN_MPY_L_U6__RA_, ARC_INSN_MPY_L_R_R__RA__RC, ARC_INSN_MPY_CC__RA__RC, ARC_INSN_MPYH_L_S12__RA_
+ , ARC_INSN_MPYH_CCU6__RA_, ARC_INSN_MPYH_L_U6__RA_, ARC_INSN_MPYH_L_R_R__RA__RC, ARC_INSN_MPYH_CC__RA__RC
+ , ARC_INSN_MPYHU_L_S12__RA_, ARC_INSN_MPYHU_CCU6__RA_, ARC_INSN_MPYHU_L_U6__RA_, ARC_INSN_MPYHU_L_R_R__RA__RC
+ , ARC_INSN_MPYHU_CC__RA__RC, ARC_INSN_MPYU_L_S12__RA_, ARC_INSN_MPYU_CCU6__RA_, ARC_INSN_MPYU_L_U6__RA_
+ , ARC_INSN_MPYU_L_R_R__RA__RC, ARC_INSN_MPYU_CC__RA__RC, ARC_INSN_J_L_R_R___RC_NOILINK_, ARC_INSN_J_CC___RC_NOILINK_
+ , ARC_INSN_J_L_R_R___RC_ILINK_, ARC_INSN_J_CC___RC_ILINK_, ARC_INSN_J_L_S12_, ARC_INSN_J_CCU6_
+ , ARC_INSN_J_L_U6_, ARC_INSN_J_S, ARC_INSN_J_S__S, ARC_INSN_J_SEQ__S
+ , ARC_INSN_J_SNE__S, ARC_INSN_J_L_S12_D_, ARC_INSN_J_CCU6_D_, ARC_INSN_J_L_U6_D_
+ , ARC_INSN_J_L_R_R_D___RC_, ARC_INSN_J_CC_D___RC_, ARC_INSN_J_S_D, ARC_INSN_J_S__S_D
+ , ARC_INSN_JL_L_S12_, ARC_INSN_JL_CCU6_, ARC_INSN_JL_L_U6_, ARC_INSN_JL_S
+ , ARC_INSN_JL_L_R_R___RC_NOILINK_, ARC_INSN_JL_CC___RC_NOILINK_, ARC_INSN_JL_L_S12_D_, ARC_INSN_JL_CCU6_D_
+ , ARC_INSN_JL_L_U6_D_, ARC_INSN_JL_L_R_R_D___RC_, ARC_INSN_JL_CC_D___RC_, ARC_INSN_JL_S_D
+ , ARC_INSN_LP_L_S12_, ARC_INSN_LPCC_CCU6, ARC_INSN_FLAG_L_S12_, ARC_INSN_FLAG_CCU6_
+ , ARC_INSN_FLAG_L_U6_, ARC_INSN_FLAG_L_R_R__RC, ARC_INSN_FLAG_CC__RC, ARC_INSN_LR_L_R_R___RC_
+ , ARC_INSN_LR_L_S12_, ARC_INSN_LR_L_U6_, ARC_INSN_SR_L_R_R___RC_, ARC_INSN_SR_L_S12_
+ , ARC_INSN_SR_L_U6_, ARC_INSN_ASL_L_R_R__RC, ARC_INSN_ASL_L_U6_, ARC_INSN_I16_GO_ASL_S_GO
+ , ARC_INSN_ASR_L_R_R__RC, ARC_INSN_ASR_L_U6_, ARC_INSN_I16_GO_ASR_S_GO, ARC_INSN_LSR_L_R_R__RC
+ , ARC_INSN_LSR_L_U6_, ARC_INSN_I16_GO_LSR_S_GO, ARC_INSN_ROR_L_R_R__RC, ARC_INSN_ROR_L_U6_
+ , ARC_INSN_RRC_L_R_R__RC, ARC_INSN_RRC_L_U6_, ARC_INSN_SEXB_L_R_R__RC, ARC_INSN_SEXB_L_U6_
+ , ARC_INSN_I16_GO_SEXB_S_GO, ARC_INSN_SEXW_L_R_R__RC, ARC_INSN_SEXW_L_U6_, ARC_INSN_I16_GO_SEXW_S_GO
+ , ARC_INSN_EXTB_L_R_R__RC, ARC_INSN_EXTB_L_U6_, ARC_INSN_I16_GO_EXTB_S_GO, ARC_INSN_EXTW_L_R_R__RC
+ , ARC_INSN_EXTW_L_U6_, ARC_INSN_I16_GO_EXTW_S_GO, ARC_INSN_ABS_L_R_R__RC, ARC_INSN_ABS_L_U6_
+ , ARC_INSN_I16_GO_ABS_S_GO, ARC_INSN_NOT_L_R_R__RC, ARC_INSN_NOT_L_U6_, ARC_INSN_I16_GO_NOT_S_GO
+ , ARC_INSN_RLC_L_R_R__RC, ARC_INSN_RLC_L_U6_, ARC_INSN_EX_L_R_R__RC, ARC_INSN_EX_L_U6_
+ , ARC_INSN_I16_GO_NEG_S_GO, ARC_INSN_SWI, ARC_INSN_TRAP_S, ARC_INSN_BRK
+ , ARC_INSN_BRK_S, ARC_INSN_ASL_L_S12__RA_, ARC_INSN_ASL_CCU6__RA_, ARC_INSN_ASL_L_U6__RA_
+ , ARC_INSN_ASL_L_R_R__RA__RC, ARC_INSN_ASL_CC__RA__RC, ARC_INSN_ASL_S_CBU3, ARC_INSN_ASL_S_SSB
+ , ARC_INSN_I16_GO_ASLM_S_GO, ARC_INSN_LSR_L_S12__RA_, ARC_INSN_LSR_CCU6__RA_, ARC_INSN_LSR_L_U6__RA_
+ , ARC_INSN_LSR_L_R_R__RA__RC, ARC_INSN_LSR_CC__RA__RC, ARC_INSN_LSR_S_SSB, ARC_INSN_I16_GO_LSRM_S_GO
+ , ARC_INSN_ASR_L_S12__RA_, ARC_INSN_ASR_CCU6__RA_, ARC_INSN_ASR_L_U6__RA_, ARC_INSN_ASR_L_R_R__RA__RC
+ , ARC_INSN_ASR_CC__RA__RC, ARC_INSN_ASR_S_CBU3, ARC_INSN_ASR_S_SSB, ARC_INSN_I16_GO_ASRM_S_GO
+ , ARC_INSN_ROR_L_S12__RA_, ARC_INSN_ROR_CCU6__RA_, ARC_INSN_ROR_L_U6__RA_, ARC_INSN_ROR_L_R_R__RA__RC
+ , ARC_INSN_ROR_CC__RA__RC, ARC_INSN_MUL64_L_S12_, ARC_INSN_MUL64_CCU6_, ARC_INSN_MUL64_L_U6_
+ , ARC_INSN_MUL64_L_R_R__RC, ARC_INSN_MUL64_CC__RC, ARC_INSN_MUL64_S_GO, ARC_INSN_MULU64_L_S12_
+ , ARC_INSN_MULU64_CCU6_, ARC_INSN_MULU64_L_U6_, ARC_INSN_MULU64_L_R_R__RC, ARC_INSN_MULU64_CC__RC
+ , ARC_INSN_ADDS_L_S12__RA_, ARC_INSN_ADDS_CCU6__RA_, ARC_INSN_ADDS_L_U6__RA_, ARC_INSN_ADDS_L_R_R__RA__RC
+ , ARC_INSN_ADDS_CC__RA__RC, ARC_INSN_SUBS_L_S12__RA_, ARC_INSN_SUBS_CCU6__RA_, ARC_INSN_SUBS_L_U6__RA_
+ , ARC_INSN_SUBS_L_R_R__RA__RC, ARC_INSN_SUBS_CC__RA__RC, ARC_INSN_DIVAW_L_S12__RA_, ARC_INSN_DIVAW_CCU6__RA_
+ , ARC_INSN_DIVAW_L_U6__RA_, ARC_INSN_DIVAW_L_R_R__RA__RC, ARC_INSN_DIVAW_CC__RA__RC, ARC_INSN_ASLS_L_S12__RA_
+ , ARC_INSN_ASLS_CCU6__RA_, ARC_INSN_ASLS_L_U6__RA_, ARC_INSN_ASLS_L_R_R__RA__RC, ARC_INSN_ASLS_CC__RA__RC
+ , ARC_INSN_ASRS_L_S12__RA_, ARC_INSN_ASRS_CCU6__RA_, ARC_INSN_ASRS_L_U6__RA_, ARC_INSN_ASRS_L_R_R__RA__RC
+ , ARC_INSN_ASRS_CC__RA__RC, ARC_INSN_ADDSDW_L_S12__RA_, ARC_INSN_ADDSDW_CCU6__RA_, ARC_INSN_ADDSDW_L_U6__RA_
+ , ARC_INSN_ADDSDW_L_R_R__RA__RC, ARC_INSN_ADDSDW_CC__RA__RC, ARC_INSN_SUBSDW_L_S12__RA_, ARC_INSN_SUBSDW_CCU6__RA_
+ , ARC_INSN_SUBSDW_L_U6__RA_, ARC_INSN_SUBSDW_L_R_R__RA__RC, ARC_INSN_SUBSDW_CC__RA__RC, ARC_INSN_SWAP_L_R_R__RC
+ , ARC_INSN_SWAP_L_U6_, ARC_INSN_NORM_L_R_R__RC, ARC_INSN_NORM_L_U6_, ARC_INSN_RND16_L_R_R__RC
+ , ARC_INSN_RND16_L_U6_, ARC_INSN_ABSSW_L_R_R__RC, ARC_INSN_ABSSW_L_U6_, ARC_INSN_ABSS_L_R_R__RC
+ , ARC_INSN_ABSS_L_U6_, ARC_INSN_NEGSW_L_R_R__RC, ARC_INSN_NEGSW_L_U6_, ARC_INSN_NEGS_L_R_R__RC
+ , ARC_INSN_NEGS_L_U6_, ARC_INSN_NORMW_L_R_R__RC, ARC_INSN_NORMW_L_U6_, ARC_INSN_NOP_S
+ , ARC_INSN_UNIMP_S, ARC_INSN_POP_S_B, ARC_INSN_POP_S_BLINK, ARC_INSN_PUSH_S_B
+ , ARC_INSN_PUSH_S_BLINK, ARC_INSN_MULLW_L_S12__RA_, ARC_INSN_MULLW_CCU6__RA_, ARC_INSN_MULLW_L_U6__RA_
+ , ARC_INSN_MULLW_L_R_R__RA__RC, ARC_INSN_MULLW_CC__RA__RC, ARC_INSN_MACLW_L_S12__RA_, ARC_INSN_MACLW_CCU6__RA_
+ , ARC_INSN_MACLW_L_U6__RA_, ARC_INSN_MACLW_L_R_R__RA__RC, ARC_INSN_MACLW_CC__RA__RC, ARC_INSN_MACHLW_L_S12__RA_
+ , ARC_INSN_MACHLW_CCU6__RA_, ARC_INSN_MACHLW_L_U6__RA_, ARC_INSN_MACHLW_L_R_R__RA__RC, ARC_INSN_MACHLW_CC__RA__RC
+ , ARC_INSN_MULULW_L_S12__RA_, ARC_INSN_MULULW_CCU6__RA_, ARC_INSN_MULULW_L_U6__RA_, ARC_INSN_MULULW_L_R_R__RA__RC
+ , ARC_INSN_MULULW_CC__RA__RC, ARC_INSN_MACHULW_L_S12__RA_, ARC_INSN_MACHULW_CCU6__RA_, ARC_INSN_MACHULW_L_U6__RA_
+ , ARC_INSN_MACHULW_L_R_R__RA__RC, ARC_INSN_MACHULW_CC__RA__RC, ARC_INSN_CURRENT_LOOP_END, ARC_INSN_CURRENT_LOOP_END_AFTER_BRANCH
+ , ARC_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder.  */
+#define CGEN_INSN_INVALID ARC_INSN_INVALID
+
+/* Total number of insns in table.  */
+#define MAX_INSNS ((int) ARC_INSN_ARC600_CURRENT_LOOP_END_AFTER_BRANCH + 1)
+
+/* This struct records data prior to insertion or after extraction.  */
+struct cgen_fields
+{
+  int length;
+  long f_nil;
+  long f_anyof;
+  long f_cond_Q;
+  long f_cond_i2;
+  long f_cond_i3;
+  long f_brcond;
+  long f_op__a;
+  long f_op__b;
+  long f_op__c;
+  long f_B_5_3;
+  long f_op_B;
+  long f_op_C;
+  long f_op_Cj;
+  long f_h_2_0;
+  long f_h_5_3;
+  long f_op_h;
+  long f_u6;
+  long f_u6x2;
+  long f_delay_N;
+  long f_res27;
+  long f_F;
+  long f_cbranch_imm;
+  long f_op_A;
+  long f_s12h;
+  long f_s12;
+  long f_s12x2;
+  long f_rel10;
+  long f_rel7;
+  long f_rel8;
+  long f_rel13bl;
+  long f_d21l;
+  long f_d21bl;
+  long f_d21h;
+  long f_d25m;
+  long f_d25h;
+  long f_rel21;
+  long f_rel21bl;
+  long f_rel25;
+  long f_rel25bl;
+  long f_d9l;
+  long f_d9h;
+  long f_rel9;
+  long f_u3;
+  long f_u5;
+  long f_u7;
+  long f_u8;
+  long f_s9;
+  long f_u5x2;
+  long f_u5x4;
+  long f_u8x4;
+  long f_s9x1;
+  long f_s9x2;
+  long f_s9x4;
+  long f_dummy;
+  long f_opm;
+  long f_go_type;
+  long f_go_cc_type;
+  long f_go_op;
+  long f_i16_43;
+  long f_i16_go;
+  long f_i16_gp_type;
+  long f_i16addcmpu7_type;
+  long f_buf;
+  long f_br;
+  long f_bluf;
+  long f_brscond;
+  long f_ldozzx;
+  long f_ldr6zzx;
+  long f_stozzr;
+  long f_ldoaa;
+  long f_ldraa;
+  long f_stoaa;
+  long f_LDODi;
+  long f_LDRDi;
+  long f_STODi;
+  long f_trapnum;
+};
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+#endif /* ARC_OPC_H */
diff --git a/opcodes/arc-opinst.c b/opcodes/arc-opinst.c
new file mode 100644
index 0000000..94c814c
--- /dev/null
+++ b/opcodes/arc-opinst.c
@@ -0,0 +1,3816 @@
+/* Semantic operand instances for arc.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2007 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "arc-desc.h"
+#include "arc-opc.h"
+
+/* Operand references.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OP_ENT(op) ARC_OPERAND_##op
+#else
+#define OP_ENT(op) ARC_OPERAND_/**/op
+#endif
+#define INPUT CGEN_OPINST_INPUT
+#define OUTPUT CGEN_OPINST_OUTPUT
+#define END CGEN_OPINST_END
+#define COND_REF CGEN_OPINST_COND_REF
+
+static const CGEN_OPINST sfmt_empty_ops[] ATTRIBUTE_UNUSED = {
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_b_s_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "i2cond", HW_H_I2COND, CGEN_MODE_BI, OP_ENT (I2COND), 0, 0 },
+  { INPUT, "label10", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL10), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_bcc_s_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "i3cond", HW_H_I3COND, CGEN_MODE_BI, OP_ENT (I3COND), 0, 0 },
+  { INPUT, "label7", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL7), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_brcc_s_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF },
+  { INPUT, "RccS", HW_H_RCCS, CGEN_MODE_BI, OP_ENT (RCCS), 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "label8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL8), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_bcc_l_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "label21", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL21), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_b_l_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "label25", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL25), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_brcc_RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "Rcc", HW_H_RCC, CGEN_MODE_SI, OP_ENT (RCC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "label9", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL9), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_brcc_U6_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "Rcc", HW_H_RCC, CGEN_MODE_SI, OP_ENT (RCC), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "label9", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL9), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_bl_s_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "label13a", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL13A), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_blcc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "label21a", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL21A), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_bl_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "label25a", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL25A), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_bl_d_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "label25a", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (LABEL25A), 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ld_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ld__AW_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ld_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ld__AW_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ld_s_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "R_a", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_A), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ld_s_abu_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "sc_u5_", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5_), 0, 0 },
+  { OUTPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ld_s_absp_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ld_s_gprel_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "GP", HW_H_GP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "sc_s9_", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_S9_), 0, 0 },
+  { OUTPUT, "R0", HW_H_R0, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ld_s_pcrel_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "u8x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U8X4), 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb__AW_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb_as_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb__AW_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb_as_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb_s_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { OUTPUT, "R_a", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_A), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb_s_abu_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "sc_u5b", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5B), 0, 0 },
+  { OUTPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb_s_absp_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldb_s_gprel_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "GP", HW_H_GP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { INPUT, "sc_s9b", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_S9B), 0, 0 },
+  { OUTPUT, "R0", HW_H_R0, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldw_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldw__AW_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldw_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldw__AW_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldw_s_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { OUTPUT, "R_a", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_A), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldw_s_abu_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { INPUT, "sc_u5w", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5W), 0, 0 },
+  { OUTPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ldw_s_gprel_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "GP", HW_H_GP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { INPUT, "sc_s9w", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_S9W), 0, 0 },
+  { OUTPUT, "R0", HW_H_R0, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_st_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_st__AW_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_st_s_abu_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { INPUT, "sc_u5_", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5_), 0, 0 },
+  { OUTPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_st_s_absp_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 },
+  { OUTPUT, "h_memory_SI_eaddr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stb_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stb__AW_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stb_as_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stb_s_abu_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { INPUT, "sc_u5b", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5B), 0, 0 },
+  { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stb_s_absp_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 },
+  { OUTPUT, "h_memory_QI_eaddr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stw_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stw__AW_abs_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s9", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S9), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_stw_s_abu_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { INPUT, "sc_u5w", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (SC_U5W), 0, 0 },
+  { OUTPUT, "h_memory_HI_eaddr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_s_abc_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { OUTPUT, "R_a", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_A), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_s_cbu3_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "u3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U3), 0, 0 },
+  { OUTPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_s_mcah_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "Rh", HW_H_CR, CGEN_MODE_SI, OP_ENT (RH), 0, 0 },
+  { INPUT, "f_op_h", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_2_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_s_absp_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_s_asspsp_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "u5x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5X4), 0, 0 },
+  { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_s_gp_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "GP", HW_H_GP, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "s9x4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (S9X4), 0, 0 },
+  { OUTPUT, "R0", HW_H_R0, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_add_s_r_u7_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "u7", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U7), 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adc_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adc_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adc_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adc_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adc_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_I16_GO_SUB_s_go_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sub_s_go_sub_ne_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sub_s_ssb_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "u5", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5), 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_and_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_and_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_and_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_and_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_and_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mov_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, 0 },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mov_ccu6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mov_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mov_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mov_cc__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_SI, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mov_s_mcah_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Rh", HW_H_CR, CGEN_MODE_SI, OP_ENT (RH), 0, 0 },
+  { INPUT, "f_op_h", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_2_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mov_s_mcahb_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { OUTPUT, "Rh", HW_H_CR, CGEN_MODE_SI, OP_ENT (RH), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mov_s_r_u7_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "u8", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U8), 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_tst_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_tst_ccu6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_tst_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_tst_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_tst_cc__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_tst_s_go_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_cmp_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_cmp_ccu6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_cmp_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_cmp_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_cmp_cc__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_cmp_s_mcah_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "Rh", HW_H_CR, CGEN_MODE_SI, OP_ENT (RH), 0, 0 },
+  { INPUT, "f_op_h", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_2_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_cmp_s_r_u7_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "u7", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U7), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_btst_s_ssb_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "u5", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U5), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mpy_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mpy_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mpy_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mpy_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mpy_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_L_r_r___RC_noilink__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "RC_noilink", HW_H_NOILINK, CGEN_MODE_SI, OP_ENT (RC_NOILINK), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_Cj", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { INPUT, "h_auxr_SI_12", HW_H_AUXR, CGEN_MODE_SI, 0, 12, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_cc___RC_noilink__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RC_noilink", HW_H_NOILINK, CGEN_MODE_SI, OP_ENT (RC_NOILINK), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_Cj", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { INPUT, "h_auxr_SI_12", HW_H_AUXR, CGEN_MODE_SI, 0, 12, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_L_r_r___RC_ilink__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "RC_ilink", HW_H_ILINKX, CGEN_MODE_SI, OP_ENT (RC_ILINK), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_Cj", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { INPUT, "h_auxr_SI_12", HW_H_AUXR, CGEN_MODE_SI, 0, 12, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_cc___RC_ilink__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RC_ilink", HW_H_ILINKX, CGEN_MODE_SI, OP_ENT (RC_ILINK), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_Cj", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { INPUT, "h_auxr_SI_12", HW_H_AUXR, CGEN_MODE_SI, 0, 12, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_ccu6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_s_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_s__S_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R31", HW_H_R31, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_seq__S_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R31", HW_H_R31, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_L_s12_d__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_ccu6_d__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_L_u6_d__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_L_r_r_d___RC__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_j_cc_d___RC__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_jl_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_jl_ccu6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_jl_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_jl_s_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_jl_L_r_r___RC_noilink__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RC_noilink", HW_H_NOILINK, CGEN_MODE_SI, OP_ENT (RC_NOILINK), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_jl_cc___RC_noilink__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RC_noilink", HW_H_NOILINK, CGEN_MODE_SI, OP_ENT (RC_NOILINK), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_jl_L_r_r_d___RC__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_jl_cc_d___RC__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_jl_s_d_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_31", HW_H_CR, CGEN_MODE_SI, 0, 31, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_lp_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12x2", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12X2), 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_2", HW_H_AUXR, CGEN_MODE_SI, 0, 2, COND_REF },
+  { OUTPUT, "h_auxr_SI_3", HW_H_AUXR, CGEN_MODE_SI, 0, 3, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_lpcc_ccu6_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "U6x2", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6X2), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_2", HW_H_AUXR, CGEN_MODE_SI, 0, 2, COND_REF },
+  { OUTPUT, "h_auxr_SI_3", HW_H_AUXR, CGEN_MODE_SI, 0, 3, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_flag_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 },
+  { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_flag_ccu6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_flag_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_flag_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_flag_cc__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_lr_L_r_r___RC__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_INT, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_RC", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_lr_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_s12", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_lr_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_INT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_auxr_SI_U6", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sr_L_r_r___RC__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_INT, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_RC", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sr_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, 0 },
+  { OUTPUT, "h_auxr_SI_s12", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sr_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_INT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_U6", HW_H_AUXR, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asl_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asl_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asr_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asr_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_rrc_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_rrc_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sexb_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_QI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sexb_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_QI, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sexw_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_HI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_sexw_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_HI, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_abs_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_abs_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_not_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_not_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ex_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_USI, OP_ENT (RC), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_SI_RC", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "h_memory_SI_RC", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_ex_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_USI, OP_ENT (U6), 0, 0 },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_SI_U6", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "h_memory_SI_U6", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_swi_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_0", HW_H_CR, CGEN_MODE_SI, 0, 0, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_trap_s_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, 0 },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "trapnum", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (TRAPNUM), 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_0", HW_H_CR, CGEN_MODE_SI, 0, 0, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_brk_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asl_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asl_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asl_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asl_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asl_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mul64_L_s12__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF },
+  { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mul64_ccu6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF },
+  { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mul64_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF },
+  { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mul64_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF },
+  { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mul64_cc__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF },
+  { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mul64_s_go_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, COND_REF },
+  { INPUT, "R_c", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_C), 0, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "h_cr_SI_58", HW_H_CR, CGEN_MODE_SI, 0, 58, COND_REF },
+  { OUTPUT, "h_cr_SI_59", HW_H_CR, CGEN_MODE_SI, 0, 59, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adds_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adds_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adds_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adds_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_adds_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "cbit", HW_H_CBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_divaw_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_SI, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_divaw_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_divaw_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_divaw_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_divaw_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asls_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_SI, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asls_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asls_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asls_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_asls_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_swap_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_swap_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_norm_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_rnd16_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_rnd16_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_abssw_L_r_r__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_HI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_abssw_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_HI, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_abss_L_u6__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_SI, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_nop_s_ops[] ATTRIBUTE_UNUSED = {
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_pop_s_b_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "h_memory_SI_SP", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_pop_s_blink_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_USI, 0, 0, 0 },
+  { INPUT, "h_memory_SI_SP", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "R31", HW_H_R31, CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_push_s_b_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R_b", HW_H_CR16, CGEN_MODE_SI, OP_ENT (R_B), 0, 0 },
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_SI_SP", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_push_s_blink_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "R31", HW_H_R31, CGEN_MODE_SI, 0, 0, 0 },
+  { INPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "SP", HW_H_SP, CGEN_MODE_SI, 0, 0, 0 },
+  { OUTPUT, "h_memory_SI_SP", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mullw_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mullw_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mullw_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mullw_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_mullw_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_maclw_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_maclw_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_maclw_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_maclw_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_maclw_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_machulw_L_s12__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { INPUT, "s12", HW_H_SINT, CGEN_MODE_INT, OP_ENT (S12), 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, 0 },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_machulw_ccu6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_machulw_L_u6__RA__ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "U6", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (U6), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_machulw_L_r_r__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RA", HW_H_CR, CGEN_MODE_SI, OP_ENT (RA), 0, 0 },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, 0 },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, 0 },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_machulw_cc__RA__RC_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "F", HW_H_UFLAGS, CGEN_MODE_UINT, OP_ENT (F), 0, COND_REF },
+  { INPUT, "Qcondb", HW_H_QCONDB, CGEN_MODE_BI, OP_ENT (QCONDB), 0, 0 },
+  { INPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { INPUT, "RC", HW_H_CR, CGEN_MODE_SI, OP_ENT (RC), 0, COND_REF },
+  { INPUT, "f_op_B", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "f_op_C", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
+  { INPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { INPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_4", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "h_memory_HI_add__DFLT_pc_add__DFLT_4_2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "RB", HW_H_CR, CGEN_MODE_SI, OP_ENT (RB), 0, COND_REF },
+  { OUTPUT, "h_cr_SI_56", HW_H_CR, CGEN_MODE_SI, 0, 56, COND_REF },
+  { OUTPUT, "h_cr_SI_57", HW_H_CR, CGEN_MODE_SI, 0, 57, COND_REF },
+  { OUTPUT, "nbit", HW_H_NBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s1bit", HW_H_S1BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "s2bit", HW_H_S2BIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "vbit", HW_H_VBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "zbit", HW_H_ZBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_current_loop_end_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_2", HW_H_AUXR, CGEN_MODE_SI, 0, 2, COND_REF },
+  { INPUT, "h_auxr_SI_3", HW_H_AUXR, CGEN_MODE_SI, 0, 3, 0 },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_cr_SI_60", HW_H_CR, CGEN_MODE_SI, 0, 60, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "lbit", HW_H_LBIT, CGEN_MODE_BI, 0, 0, 0 },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_60", HW_H_CR, CGEN_MODE_SI, 0, 60, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+static const CGEN_OPINST sfmt_current_loop_end_after_branch_ops[] ATTRIBUTE_UNUSED = {
+  { INPUT, "h_auxr_SI_2", HW_H_AUXR, CGEN_MODE_SI, 0, 2, COND_REF },
+  { INPUT, "h_auxr_SI_3", HW_H_AUXR, CGEN_MODE_SI, 0, 3, COND_REF },
+  { INPUT, "h_auxr_SI_34", HW_H_AUXR, CGEN_MODE_SI, 0, 34, COND_REF },
+  { INPUT, "h_auxr_SI_37", HW_H_AUXR, CGEN_MODE_SI, 0, 37, COND_REF },
+  { INPUT, "h_cr_SI_60", HW_H_CR, CGEN_MODE_SI, 0, 60, COND_REF },
+  { INPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { INPUT, "h_prof_offset_SI_0", HW_H_PROF_OFFSET, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_status32_SI_0", HW_H_STATUS32, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_timer_expire_SI_0", HW_H_TIMER_EXPIRE, CGEN_MODE_SI, 0, 0, COND_REF },
+  { INPUT, "h_ubit_BI", HW_H_UBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "lbit", HW_H_LBIT, CGEN_MODE_BI, 0, 0, COND_REF },
+  { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { OUTPUT, "h_auxr_SI_11", HW_H_AUXR, CGEN_MODE_SI, 0, 11, COND_REF },
+  { OUTPUT, "h_auxr_SI_33", HW_H_AUXR, CGEN_MODE_SI, 0, 33, COND_REF },
+  { OUTPUT, "h_cr_SI_29", HW_H_CR, CGEN_MODE_SI, 0, 29, COND_REF },
+  { OUTPUT, "h_cr_SI_60", HW_H_CR, CGEN_MODE_SI, 0, 60, COND_REF },
+  { OUTPUT, "h_e1_BI", HW_H_E1, CGEN_MODE_BI, 0, 0, COND_REF },
+  { OUTPUT, "h_memory_UHI_countp", HW_H_MEMORY, CGEN_MODE_UHI, 0, 0, COND_REF },
+  { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
+  { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
+};
+
+#undef OP_ENT
+#undef INPUT
+#undef OUTPUT
+#undef END
+#undef COND_REF
+
+/* Operand instance lookup table.  */
+
+static const CGEN_OPINST *arc_cgen_opinst_table[MAX_INSNS] = {
+  0,
+  & sfmt_b_s_ops[0],
+  & sfmt_bcc_s_ops[0],
+  & sfmt_brcc_s_ops[0],
+  & sfmt_bcc_l_ops[0],
+  & sfmt_bcc_l_ops[0],
+  & sfmt_b_l_ops[0],
+  & sfmt_b_l_ops[0],
+  & sfmt_brcc_RC_ops[0],
+  & sfmt_brcc_RC_ops[0],
+  & sfmt_brcc_U6_ops[0],
+  & sfmt_brcc_U6_ops[0],
+  & sfmt_bl_s_ops[0],
+  & sfmt_blcc_ops[0],
+  & sfmt_blcc_ops[0],
+  & sfmt_bl_ops[0],
+  & sfmt_bl_d_ops[0],
+  & sfmt_ld_abs_ops[0],
+  & sfmt_ld__AW_abs_ops[0],
+  & sfmt_ld__AW_abs_ops[0],
+  & sfmt_ld_abs_ops[0],
+  & sfmt_ld_abc_ops[0],
+  & sfmt_ld__AW_abc_ops[0],
+  & sfmt_ld__AW_abc_ops[0],
+  & sfmt_ld_abc_ops[0],
+  & sfmt_ld_s_abc_ops[0],
+  & sfmt_ld_s_abu_ops[0],
+  & sfmt_ld_s_absp_ops[0],
+  & sfmt_ld_s_gprel_ops[0],
+  & sfmt_ld_s_pcrel_ops[0],
+  & sfmt_ldb_abs_ops[0],
+  & sfmt_ldb__AW_abs_ops[0],
+  & sfmt_ldb__AW_abs_ops[0],
+  & sfmt_ldb_as_abs_ops[0],
+  & sfmt_ldb_abc_ops[0],
+  & sfmt_ldb__AW_abc_ops[0],
+  & sfmt_ldb__AW_abc_ops[0],
+  & sfmt_ldb_as_abc_ops[0],
+  & sfmt_ldb_s_abc_ops[0],
+  & sfmt_ldb_s_abu_ops[0],
+  & sfmt_ldb_s_absp_ops[0],
+  & sfmt_ldb_s_gprel_ops[0],
+  & sfmt_ldb_abs_ops[0],
+  & sfmt_ldb__AW_abs_ops[0],
+  & sfmt_ldb__AW_abs_ops[0],
+  & sfmt_ldb_as_abs_ops[0],
+  & sfmt_ldb_abc_ops[0],
+  & sfmt_ldb__AW_abc_ops[0],
+  & sfmt_ldb__AW_abc_ops[0],
+  & sfmt_ldb_as_abc_ops[0],
+  & sfmt_ldw_abs_ops[0],
+  & sfmt_ldw__AW_abs_ops[0],
+  & sfmt_ldw__AW_abs_ops[0],
+  & sfmt_ldw_abs_ops[0],
+  & sfmt_ldw_abc_ops[0],
+  & sfmt_ldw__AW_abc_ops[0],
+  & sfmt_ldw__AW_abc_ops[0],
+  & sfmt_ldw_abc_ops[0],
+  & sfmt_ldw_s_abc_ops[0],
+  & sfmt_ldw_s_abu_ops[0],
+  & sfmt_ldw_s_gprel_ops[0],
+  & sfmt_ldw_abs_ops[0],
+  & sfmt_ldw__AW_abs_ops[0],
+  & sfmt_ldw__AW_abs_ops[0],
+  & sfmt_ldw_abs_ops[0],
+  & sfmt_ldw_abc_ops[0],
+  & sfmt_ldw__AW_abc_ops[0],
+  & sfmt_ldw__AW_abc_ops[0],
+  & sfmt_ldw_abc_ops[0],
+  & sfmt_ldw_s_abu_ops[0],
+  & sfmt_st_abs_ops[0],
+  & sfmt_st__AW_abs_ops[0],
+  & sfmt_st__AW_abs_ops[0],
+  & sfmt_st_abs_ops[0],
+  & sfmt_st_s_abu_ops[0],
+  & sfmt_st_s_absp_ops[0],
+  & sfmt_stb_abs_ops[0],
+  & sfmt_stb__AW_abs_ops[0],
+  & sfmt_stb__AW_abs_ops[0],
+  & sfmt_stb_as_abs_ops[0],
+  & sfmt_stb_s_abu_ops[0],
+  & sfmt_stb_s_absp_ops[0],
+  & sfmt_stw_abs_ops[0],
+  & sfmt_stw__AW_abs_ops[0],
+  & sfmt_stw__AW_abs_ops[0],
+  & sfmt_stw_abs_ops[0],
+  & sfmt_stw_s_abu_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_add_s_abc_ops[0],
+  & sfmt_add_s_cbu3_ops[0],
+  & sfmt_add_s_mcah_ops[0],
+  & sfmt_add_s_absp_ops[0],
+  & sfmt_add_s_asspsp_ops[0],
+  & sfmt_add_s_gp_ops[0],
+  & sfmt_add_s_r_u7_ops[0],
+  & sfmt_adc_L_s12__RA__ops[0],
+  & sfmt_adc_ccu6__RA__ops[0],
+  & sfmt_adc_L_u6__RA__ops[0],
+  & sfmt_adc_L_r_r__RA__RC_ops[0],
+  & sfmt_adc_cc__RA__RC_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_add_s_cbu3_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_sub_s_go_sub_ne_ops[0],
+  & sfmt_sub_s_ssb_ops[0],
+  & sfmt_add_s_asspsp_ops[0],
+  & sfmt_adc_L_s12__RA__ops[0],
+  & sfmt_adc_ccu6__RA__ops[0],
+  & sfmt_adc_L_u6__RA__ops[0],
+  & sfmt_adc_L_r_r__RA__RC_ops[0],
+  & sfmt_adc_cc__RA__RC_ops[0],
+  & sfmt_and_L_s12__RA__ops[0],
+  & sfmt_and_ccu6__RA__ops[0],
+  & sfmt_and_L_u6__RA__ops[0],
+  & sfmt_and_L_r_r__RA__RC_ops[0],
+  & sfmt_and_cc__RA__RC_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_and_L_s12__RA__ops[0],
+  & sfmt_and_ccu6__RA__ops[0],
+  & sfmt_and_L_u6__RA__ops[0],
+  & sfmt_and_L_r_r__RA__RC_ops[0],
+  & sfmt_and_cc__RA__RC_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_and_L_s12__RA__ops[0],
+  & sfmt_and_ccu6__RA__ops[0],
+  & sfmt_and_L_u6__RA__ops[0],
+  & sfmt_and_L_r_r__RA__RC_ops[0],
+  & sfmt_and_cc__RA__RC_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_and_L_s12__RA__ops[0],
+  & sfmt_and_ccu6__RA__ops[0],
+  & sfmt_and_L_u6__RA__ops[0],
+  & sfmt_and_L_r_r__RA__RC_ops[0],
+  & sfmt_and_cc__RA__RC_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_mov_L_s12__ops[0],
+  & sfmt_mov_ccu6__ops[0],
+  & sfmt_mov_L_u6__ops[0],
+  & sfmt_mov_L_r_r__RC_ops[0],
+  & sfmt_mov_cc__RC_ops[0],
+  & sfmt_mov_s_mcah_ops[0],
+  & sfmt_mov_s_mcahb_ops[0],
+  & sfmt_mov_s_r_u7_ops[0],
+  & sfmt_tst_L_s12__ops[0],
+  & sfmt_tst_ccu6__ops[0],
+  & sfmt_tst_L_u6__ops[0],
+  & sfmt_tst_L_r_r__RC_ops[0],
+  & sfmt_tst_cc__RC_ops[0],
+  & sfmt_tst_s_go_ops[0],
+  & sfmt_cmp_L_s12__ops[0],
+  & sfmt_cmp_ccu6__ops[0],
+  & sfmt_cmp_L_u6__ops[0],
+  & sfmt_cmp_L_r_r__RC_ops[0],
+  & sfmt_cmp_cc__RC_ops[0],
+  & sfmt_cmp_s_mcah_ops[0],
+  & sfmt_cmp_s_r_u7_ops[0],
+  & sfmt_cmp_L_s12__ops[0],
+  & sfmt_cmp_ccu6__ops[0],
+  & sfmt_cmp_L_u6__ops[0],
+  & sfmt_cmp_L_r_r__RC_ops[0],
+  & sfmt_cmp_cc__RC_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_and_L_s12__RA__ops[0],
+  & sfmt_and_ccu6__RA__ops[0],
+  & sfmt_and_L_u6__RA__ops[0],
+  & sfmt_and_L_r_r__RA__RC_ops[0],
+  & sfmt_and_cc__RA__RC_ops[0],
+  & sfmt_sub_s_ssb_ops[0],
+  & sfmt_and_L_s12__RA__ops[0],
+  & sfmt_and_ccu6__RA__ops[0],
+  & sfmt_and_L_u6__RA__ops[0],
+  & sfmt_and_L_r_r__RA__RC_ops[0],
+  & sfmt_and_cc__RA__RC_ops[0],
+  & sfmt_sub_s_ssb_ops[0],
+  & sfmt_tst_L_s12__ops[0],
+  & sfmt_tst_ccu6__ops[0],
+  & sfmt_tst_L_u6__ops[0],
+  & sfmt_tst_L_r_r__RC_ops[0],
+  & sfmt_tst_cc__RC_ops[0],
+  & sfmt_btst_s_ssb_ops[0],
+  & sfmt_and_L_s12__RA__ops[0],
+  & sfmt_and_ccu6__RA__ops[0],
+  & sfmt_and_L_u6__RA__ops[0],
+  & sfmt_and_L_r_r__RA__RC_ops[0],
+  & sfmt_and_cc__RA__RC_ops[0],
+  & sfmt_and_L_s12__RA__ops[0],
+  & sfmt_and_ccu6__RA__ops[0],
+  & sfmt_and_L_u6__RA__ops[0],
+  & sfmt_and_L_r_r__RA__RC_ops[0],
+  & sfmt_and_cc__RA__RC_ops[0],
+  & sfmt_sub_s_ssb_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_add_L_s12__RA__ops[0],
+  & sfmt_add_ccu6__RA__ops[0],
+  & sfmt_add_L_u6__RA__ops[0],
+  & sfmt_add_L_r_r__RA__RC_ops[0],
+  & sfmt_add_cc__RA__RC_ops[0],
+  & sfmt_mpy_L_s12__RA__ops[0],
+  & sfmt_mpy_ccu6__RA__ops[0],
+  & sfmt_mpy_L_u6__RA__ops[0],
+  & sfmt_mpy_L_r_r__RA__RC_ops[0],
+  & sfmt_mpy_cc__RA__RC_ops[0],
+  & sfmt_mpy_L_s12__RA__ops[0],
+  & sfmt_mpy_ccu6__RA__ops[0],
+  & sfmt_mpy_L_u6__RA__ops[0],
+  & sfmt_mpy_L_r_r__RA__RC_ops[0],
+  & sfmt_mpy_cc__RA__RC_ops[0],
+  & sfmt_mpy_L_s12__RA__ops[0],
+  & sfmt_mpy_ccu6__RA__ops[0],
+  & sfmt_mpy_L_u6__RA__ops[0],
+  & sfmt_mpy_L_r_r__RA__RC_ops[0],
+  & sfmt_mpy_cc__RA__RC_ops[0],
+  & sfmt_mpy_L_s12__RA__ops[0],
+  & sfmt_mpy_ccu6__RA__ops[0],
+  & sfmt_mpy_L_u6__RA__ops[0],
+  & sfmt_mpy_L_r_r__RA__RC_ops[0],
+  & sfmt_mpy_cc__RA__RC_ops[0],
+  & sfmt_j_L_r_r___RC_noilink__ops[0],
+  & sfmt_j_cc___RC_noilink__ops[0],
+  & sfmt_j_L_r_r___RC_ilink__ops[0],
+  & sfmt_j_cc___RC_ilink__ops[0],
+  & sfmt_j_L_s12__ops[0],
+  & sfmt_j_ccu6__ops[0],
+  & sfmt_j_L_u6__ops[0],
+  & sfmt_j_s_ops[0],
+  & sfmt_j_s__S_ops[0],
+  & sfmt_j_seq__S_ops[0],
+  & sfmt_j_seq__S_ops[0],
+  & sfmt_j_L_s12_d__ops[0],
+  & sfmt_j_ccu6_d__ops[0],
+  & sfmt_j_L_u6_d__ops[0],
+  & sfmt_j_L_r_r_d___RC__ops[0],
+  & sfmt_j_cc_d___RC__ops[0],
+  & sfmt_j_s_ops[0],
+  & sfmt_j_s__S_ops[0],
+  & sfmt_jl_L_s12__ops[0],
+  & sfmt_jl_ccu6__ops[0],
+  & sfmt_jl_L_u6__ops[0],
+  & sfmt_jl_s_ops[0],
+  & sfmt_jl_L_r_r___RC_noilink__ops[0],
+  & sfmt_jl_cc___RC_noilink__ops[0],
+  & sfmt_jl_L_s12__ops[0],
+  & sfmt_jl_ccu6__ops[0],
+  & sfmt_jl_L_u6__ops[0],
+  & sfmt_jl_L_r_r_d___RC__ops[0],
+  & sfmt_jl_cc_d___RC__ops[0],
+  & sfmt_jl_s_d_ops[0],
+  & sfmt_lp_L_s12__ops[0],
+  & sfmt_lpcc_ccu6_ops[0],
+  & sfmt_flag_L_s12__ops[0],
+  & sfmt_flag_ccu6__ops[0],
+  & sfmt_flag_L_u6__ops[0],
+  & sfmt_flag_L_r_r__RC_ops[0],
+  & sfmt_flag_cc__RC_ops[0],
+  & sfmt_lr_L_r_r___RC__ops[0],
+  & sfmt_lr_L_s12__ops[0],
+  & sfmt_lr_L_u6__ops[0],
+  & sfmt_sr_L_r_r___RC__ops[0],
+  & sfmt_sr_L_s12__ops[0],
+  & sfmt_sr_L_u6__ops[0],
+  & sfmt_asl_L_r_r__RC_ops[0],
+  & sfmt_asl_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_asr_L_r_r__RC_ops[0],
+  & sfmt_asr_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_asr_L_r_r__RC_ops[0],
+  & sfmt_asr_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_asr_L_r_r__RC_ops[0],
+  & sfmt_asr_L_u6__ops[0],
+  & sfmt_rrc_L_r_r__RC_ops[0],
+  & sfmt_rrc_L_u6__ops[0],
+  & sfmt_sexb_L_r_r__RC_ops[0],
+  & sfmt_sexb_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_sexw_L_r_r__RC_ops[0],
+  & sfmt_sexw_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_sexb_L_r_r__RC_ops[0],
+  & sfmt_sexb_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_sexw_L_r_r__RC_ops[0],
+  & sfmt_sexw_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_abs_L_r_r__RC_ops[0],
+  & sfmt_abs_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_not_L_r_r__RC_ops[0],
+  & sfmt_not_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_rrc_L_r_r__RC_ops[0],
+  & sfmt_rrc_L_u6__ops[0],
+  & sfmt_ex_L_r_r__RC_ops[0],
+  & sfmt_ex_L_u6__ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_swi_ops[0],
+  & sfmt_trap_s_ops[0],
+  & sfmt_brk_ops[0],
+  & sfmt_brk_ops[0],
+  & sfmt_asl_L_s12__RA__ops[0],
+  & sfmt_asl_ccu6__RA__ops[0],
+  & sfmt_asl_L_u6__RA__ops[0],
+  & sfmt_asl_L_r_r__RA__RC_ops[0],
+  & sfmt_asl_cc__RA__RC_ops[0],
+  & sfmt_add_s_cbu3_ops[0],
+  & sfmt_sub_s_ssb_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_asl_L_s12__RA__ops[0],
+  & sfmt_asl_ccu6__RA__ops[0],
+  & sfmt_asl_L_u6__RA__ops[0],
+  & sfmt_asl_L_r_r__RA__RC_ops[0],
+  & sfmt_asl_cc__RA__RC_ops[0],
+  & sfmt_sub_s_ssb_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_asl_L_s12__RA__ops[0],
+  & sfmt_asl_ccu6__RA__ops[0],
+  & sfmt_asl_L_u6__RA__ops[0],
+  & sfmt_asl_L_r_r__RA__RC_ops[0],
+  & sfmt_asl_cc__RA__RC_ops[0],
+  & sfmt_add_s_cbu3_ops[0],
+  & sfmt_sub_s_ssb_ops[0],
+  & sfmt_I16_GO_SUB_s_go_ops[0],
+  & sfmt_asl_L_s12__RA__ops[0],
+  & sfmt_asl_ccu6__RA__ops[0],
+  & sfmt_asl_L_u6__RA__ops[0],
+  & sfmt_asl_L_r_r__RA__RC_ops[0],
+  & sfmt_asl_cc__RA__RC_ops[0],
+  & sfmt_mul64_L_s12__ops[0],
+  & sfmt_mul64_ccu6__ops[0],
+  & sfmt_mul64_L_u6__ops[0],
+  & sfmt_mul64_L_r_r__RC_ops[0],
+  & sfmt_mul64_cc__RC_ops[0],
+  & sfmt_mul64_s_go_ops[0],
+  & sfmt_mul64_L_s12__ops[0],
+  & sfmt_mul64_ccu6__ops[0],
+  & sfmt_mul64_L_u6__ops[0],
+  & sfmt_mul64_L_r_r__RC_ops[0],
+  & sfmt_mul64_cc__RC_ops[0],
+  & sfmt_adds_L_s12__RA__ops[0],
+  & sfmt_adds_ccu6__RA__ops[0],
+  & sfmt_adds_L_u6__RA__ops[0],
+  & sfmt_adds_L_r_r__RA__RC_ops[0],
+  & sfmt_adds_cc__RA__RC_ops[0],
+  & sfmt_adds_L_s12__RA__ops[0],
+  & sfmt_adds_ccu6__RA__ops[0],
+  & sfmt_adds_L_u6__RA__ops[0],
+  & sfmt_adds_L_r_r__RA__RC_ops[0],
+  & sfmt_adds_cc__RA__RC_ops[0],
+  & sfmt_divaw_L_s12__RA__ops[0],
+  & sfmt_divaw_ccu6__RA__ops[0],
+  & sfmt_divaw_L_u6__RA__ops[0],
+  & sfmt_divaw_L_r_r__RA__RC_ops[0],
+  & sfmt_divaw_cc__RA__RC_ops[0],
+  & sfmt_asls_L_s12__RA__ops[0],
+  & sfmt_asls_ccu6__RA__ops[0],
+  & sfmt_asls_L_u6__RA__ops[0],
+  & sfmt_asls_L_r_r__RA__RC_ops[0],
+  & sfmt_asls_cc__RA__RC_ops[0],
+  & sfmt_asls_L_s12__RA__ops[0],
+  & sfmt_asls_ccu6__RA__ops[0],
+  & sfmt_asls_L_u6__RA__ops[0],
+  & sfmt_asls_L_r_r__RA__RC_ops[0],
+  & sfmt_asls_cc__RA__RC_ops[0],
+  & sfmt_asls_L_s12__RA__ops[0],
+  & sfmt_asls_ccu6__RA__ops[0],
+  & sfmt_asls_L_u6__RA__ops[0],
+  & sfmt_asls_L_r_r__RA__RC_ops[0],
+  & sfmt_asls_cc__RA__RC_ops[0],
+  & sfmt_asls_L_s12__RA__ops[0],
+  & sfmt_asls_ccu6__RA__ops[0],
+  & sfmt_asls_L_u6__RA__ops[0],
+  & sfmt_asls_L_r_r__RA__RC_ops[0],
+  & sfmt_asls_cc__RA__RC_ops[0],
+  & sfmt_swap_L_r_r__RC_ops[0],
+  & sfmt_swap_L_u6__ops[0],
+  & sfmt_swap_L_r_r__RC_ops[0],
+  & sfmt_norm_L_u6__ops[0],
+  & sfmt_rnd16_L_r_r__RC_ops[0],
+  & sfmt_rnd16_L_u6__ops[0],
+  & sfmt_abssw_L_r_r__RC_ops[0],
+  & sfmt_abssw_L_u6__ops[0],
+  & sfmt_rnd16_L_r_r__RC_ops[0],
+  & sfmt_abss_L_u6__ops[0],
+  & sfmt_abssw_L_r_r__RC_ops[0],
+  & sfmt_abssw_L_u6__ops[0],
+  & sfmt_rnd16_L_r_r__RC_ops[0],
+  & sfmt_rnd16_L_u6__ops[0],
+  & sfmt_swap_L_r_r__RC_ops[0],
+  & sfmt_swap_L_u6__ops[0],
+  & sfmt_nop_s_ops[0],
+  & sfmt_nop_s_ops[0],
+  & sfmt_pop_s_b_ops[0],
+  & sfmt_pop_s_blink_ops[0],
+  & sfmt_push_s_b_ops[0],
+  & sfmt_push_s_blink_ops[0],
+  & sfmt_mullw_L_s12__RA__ops[0],
+  & sfmt_mullw_ccu6__RA__ops[0],
+  & sfmt_mullw_L_u6__RA__ops[0],
+  & sfmt_mullw_L_r_r__RA__RC_ops[0],
+  & sfmt_mullw_cc__RA__RC_ops[0],
+  & sfmt_maclw_L_s12__RA__ops[0],
+  & sfmt_maclw_ccu6__RA__ops[0],
+  & sfmt_maclw_L_u6__RA__ops[0],
+  & sfmt_maclw_L_r_r__RA__RC_ops[0],
+  & sfmt_maclw_cc__RA__RC_ops[0],
+  & sfmt_maclw_L_s12__RA__ops[0],
+  & sfmt_maclw_ccu6__RA__ops[0],
+  & sfmt_maclw_L_u6__RA__ops[0],
+  & sfmt_maclw_L_r_r__RA__RC_ops[0],
+  & sfmt_maclw_cc__RA__RC_ops[0],
+  & sfmt_mullw_L_s12__RA__ops[0],
+  & sfmt_mullw_ccu6__RA__ops[0],
+  & sfmt_mullw_L_u6__RA__ops[0],
+  & sfmt_mullw_L_r_r__RA__RC_ops[0],
+  & sfmt_mullw_cc__RA__RC_ops[0],
+  & sfmt_machulw_L_s12__RA__ops[0],
+  & sfmt_machulw_ccu6__RA__ops[0],
+  & sfmt_machulw_L_u6__RA__ops[0],
+  & sfmt_machulw_L_r_r__RA__RC_ops[0],
+  & sfmt_machulw_cc__RA__RC_ops[0],
+  & sfmt_current_loop_end_ops[0],
+  & sfmt_current_loop_end_after_branch_ops[0],
+  & sfmt_current_loop_end_after_branch_ops[0],
+};
+
+/* Function to call before using the operand instance table.  */
+
+void
+arc_cgen_init_opinst_table (cd)
+     CGEN_CPU_DESC cd;
+{
+  int i;
+  const CGEN_OPINST **oi = & arc_cgen_opinst_table[0];
+  CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
+  for (i = 0; i < MAX_INSNS; ++i)
+    insns[i].opinst = oi[i];
+}
diff --git a/opcodes/arcompact-dis.c b/opcodes/arcompact-dis.c
new file mode 100644
index 0000000..545eecb
--- /dev/null
+++ b/opcodes/arcompact-dis.c
@@ -0,0 +1,3833 @@
+/* Instruction printing code for the ARC.
+   Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
+   Contributed by Doug Evans (dje@cygnus.com).
+
+   Sources derived from work done by Sankhya Technologies (www.sankhya.com)
+
+   Cleaned up , Comments Added, Support For A700 instructions by
+   Saurabh Verma (saurabh.verma@codito.com)
+   Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
+
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include <ansidecl.h>
+#include "dis-asm.h"
+#include "opcode/arc.h"
+#include "elf-bfd.h"
+#include "elf/arc.h"
+#include <string.h>
+
+#include <ctype.h>
+#include <stdarg.h>
+#include "arc-dis.h"
+#include "arc-ext.h"
+
+  /*
+    warning: implicit declaration of function `printf_unfiltered'
+    if dbg is 1 then this definition is required
+  */
+  void printf_unfiltered (const char *,...);
+static bfd_vma bfd_getm32 (unsigned int);
+static bfd_vma bfd_getm32_ac (unsigned int) ATTRIBUTE_UNUSED;
+struct arcDisState arcAnalyzeInstr (bfd_vma, disassemble_info*);
+
+
+#ifndef dbg
+#define dbg	(0)
+#endif
+
+  /*
+    Ravi:
+    : undefined reference to `printf_unfiltered'
+    if dbg is 1 then this definition is required
+  */
+#if dbg
+  void printf_unfiltered (const char *,...)
+ {
+   va_list args;
+   va_start (args, format);
+   vfprintf_unfiltered (gdb_stdout, format, args);
+   va_end (args);
+ }
+#endif
+
+#undef _NELEM
+#define _NELEM(ary)	(sizeof(ary) / sizeof(ary[0]))
+
+#define BIT(word,n)       ((word) & (1 << n))
+#define BITS(word,s,e)    (((word) << (31-e)) >> (s+(31-e)))
+#define OPCODE(word)      (BITS ((word), 27, 31))
+#define FIELDA(word)      (BITS ((word), 0, 5))
+#define FIELDb(word)      (BITS ((word), 24, 26))
+#define FIELDB(word)      (BITS ((word), 12, 14))
+#define FIELDC(word)      (BITS ((word), 6, 11))
+#define OPCODE_AC(word)   (BITS ((word), 11, 15))
+#define FIELDA_AC(word)   (BITS ((word), 0, 2))
+#define FIELDB_AC(word)   (BITS ((word), 8, 10))
+#define FIELDC_AC(word)   (BITS ((word), 5, 7))
+#define FIELDU_AC(word)   (BITS ((word), 0, 4))
+
+/*
+ * FIELDS_AC is the 11-bit signed immediate value used for
+ * GP-relative instructions.
+ */
+#define FIELDS_AC(word)   (BITS (((signed int) word), 0, 8))
+
+/*
+ * FIELDD is signed in all of its uses, so we make sure argument is
+ * treated as signed for bit shifting purposes.
+ */
+#define FIELDD(word)      (BITS (((signed int) word), 16, 23))
+
+/*
+ * FIELDD9 is the 9-bit signed immediate value used for
+ * load/store instructions.
+ */
+#define FIELDD9(word)     ((BITS(((signed int)word),15,15) << 8) | (BITS((word),16,23)))
+
+/*
+ * FIELDS is the 12-bit signed immediate value
+ */
+#define FIELDS(word)      ((BITS(((signed int)word),0,5) << 6) | (BITS((word),6,11)))					\
+
+/*
+ * FIELD S9 is the 9-bit signed immediate value used for
+ * bbit0/bbit instruction
+ */
+#define FIELDS9(word)     (((BITS(((signed int)word),15,15) << 7) | (BITS((word),17,23))) << 1)
+#define FIELDS9_FLAG(word)     (((BITS(((signed int)word),0,5) << 6) | (BITS((word),6,11))) )
+
+#define PUT_NEXT_WORD_IN(a) {		\
+	if (is_limm==1 && !NEXT_WORD(1))       	\
+	  mwerror(state, "Illegal limm reference in last instruction!\n"); \
+        a = ((state->words[1] & 0xff00) | (state->words[1] & 0xff)) << 16; \
+        a |= ((state->words[1] & 0xff0000) | (state->words[1] & 0xff000000)) >> 16;	\
+	}
+
+#define CHECK_NULLIFY() do{		\
+	state->nullifyMode = BITS(state->words[0],5,5);	\
+	}while(0)
+
+#define CHECK_COND_NULLIFY() do {		\
+	state->nullifyMode = BITS(state->words[0],5,5);	\
+	cond = BITS(state->words[0],0,4);	\
+	}while(0)
+
+#define CHECK_FLAG_COND_NULLIFY() do{	\
+	if (is_shimm == 0) {			\
+	  flag = BIT(state->words[0],15);	\
+	  state->nullifyMode = BITS(state->words[0],5,5); \
+	  cond = BITS(state->words[0],0,4);	\
+	}					\
+	}while(0)
+
+#define CHECK_FLAG_COND() {		\
+	if (is_shimm == 0) {			\
+	  flag = BIT(state->words[0],15);	\
+	  cond = BITS(state->words[0],0,4);	\
+	}					\
+	}
+
+#define CHECK_FLAG() {			\
+	flag = BIT(state->words[0],15);	\
+	}
+
+#define CHECK_COND() {		                \
+	if (is_shimm == 0) {			\
+	  cond = BITS(state->words[0],0,4);	\
+	}					\
+	}
+
+#define CHECK_FIELD(field) {			\
+	if (field == 62) {			\
+	  is_limm++;				\
+	  field##isReg = 0;			\
+	  PUT_NEXT_WORD_IN(field);		\
+	  limm_value = field;			\
+	}					\
+	}
+
+#define CHECK_FIELD_A() {			\
+	fieldA = FIELDA(state->words[0]);	\
+	if (fieldA == 62) {			\
+	  fieldAisReg = 0;			\
+	  fieldA = 0;				\
+	}					\
+	}
+
+#define FIELD_B() {				\
+	fieldB = (FIELDB(state->words[0]) << 3);\
+	fieldB |= FIELDb(state->words[0]);	\
+	if (fieldB == 62) {			\
+	  fieldBisReg = 0;			\
+	  fieldB = 0;				\
+	}					\
+	}
+
+#define FIELD_C() {				\
+	fieldC = FIELDC(state->words[0]);	\
+	if (fieldC == 62) {  			\
+	  fieldCisReg = 0; 			\
+	}					\
+	}
+/********** Aurora SIMD ARC 8 - bit constant **********/
+#define FIELD_U8() {                            \
+                                                \
+          fieldC  = BITS(state->words[0],15,16);\
+          fieldC  = fieldC <<6;                 \
+          fieldC |= FIELDC(state->words[0]);    \
+          fieldCisReg = 0;                      \
+        }
+
+#define CHECK_FIELD_B() {			\
+	fieldB = (FIELDB(state->words[0]) << 3);\
+	fieldB |= FIELDb(state->words[0]);	\
+	CHECK_FIELD(fieldB);			\
+	}
+
+#define CHECK_FIELD_C() {			\
+	fieldC = FIELDC(state->words[0]);	\
+	CHECK_FIELD(fieldC);			\
+	}
+
+#define FIELD_C_S() {				\
+	fieldC_S = (FIELDC_S(state->words[0]) << 3);	\
+	}
+
+#define FIELD_B_S() {				\
+	fieldB_S = (FIELDB_S(state->words[0]) << 3);	\
+	}
+
+#define CHECK_FIELD_H_AC() {			\
+	fieldC = ((FIELDA_AC(state->words[0])) << 3);	\
+	fieldC |= FIELDC_AC(state->words[0]);	\
+	CHECK_FIELD(fieldC);			\
+	}
+
+#define FIELD_H_AC() {				\
+	fieldC = ((FIELDA_AC(state->words[0])) << 3);	\
+	fieldC |= FIELDC_AC(state->words[0]);	\
+	if (fieldC > 60) {  			\
+	  fieldCisReg = 0; 			\
+	  fieldC = 0;				\
+	}					\
+	}
+
+#define FIELD_C_AC() {				\
+	fieldC = FIELDC_AC(state->words[0]);	\
+	if (fieldC > 3) {  			\
+	  fieldC += 8;  			\
+	}				  	\
+	}
+
+#define FIELD_B_AC() {				\
+	fieldB = FIELDB_AC(state->words[0]);	\
+	if (fieldB > 3) {  			\
+	  fieldB += 8; 				\
+	}				  	\
+	}
+
+#define FIELD_A_AC() {				\
+	fieldA = FIELDA_AC(state->words[0]);	\
+	if (fieldA > 3) {  			\
+	  fieldA += 8; 				\
+	}				  	\
+	}
+
+#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
+#define IS_REG(x)   (field##x##isReg)
+#define IS_SIMD_128_REG(x)  (usesSimdReg##x == 1)
+#define IS_SIMD_16_REG(x)   (usesSimdReg##x == 2)
+#define IS_SIMD_DATA_REG(x) (usesSimdReg##x == 3)
+#define WRITE_FORMAT_LB_Rx_RB(x)     WRITE_FORMAT(x,"[","]","","")
+#define WRITE_FORMAT_x_COMMA_LB(x)   WRITE_FORMAT(x,"",",[","",",[")
+#define WRITE_FORMAT_COMMA_x_RB(x)   WRITE_FORMAT(x,",","]",",","]")
+#define WRITE_FORMAT_x_RB(x)         WRITE_FORMAT(x,"","]","","]")
+#define WRITE_FORMAT_COMMA_x(x)      WRITE_FORMAT(x,",","",",","")
+#define WRITE_FORMAT_x_COMMA(x)      WRITE_FORMAT(x,"",",","",",")
+#define WRITE_FORMAT_x(x)            WRITE_FORMAT(x,"","","","")
+#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat(formatString,              \
+                                     (IS_SIMD_128_REG(x) ? cb1"%S"ca1:  \
+                                      IS_SIMD_16_REG(x)  ? cb1"%I"ca1:  \
+                                      IS_SIMD_DATA_REG(x)? cb1"%D"ca1:  \
+                                      IS_REG(x)          ? cb1"%r"ca1:  \
+                                      usesAuxReg         ?  cb"%a"ca :  \
+                                      IS_SMALL(x) ? cb"%d"ca : cb"%h"ca))
+
+#define WRITE_FORMAT_LB() strcat(formatString, "[")
+#define WRITE_FORMAT_RB() strcat(formatString, "]")
+#define WRITE_COMMENT(str)	(state->comm[state->commNum++] = (str))
+#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT("nop");
+
+#define NEXT_WORD(x) (offset += 4, state->words[x])
+
+#define NEXT_WORD_AC(x) (offset += 2, state->words[x])
+
+#define add_target(x) 	(state->targets[state->tcnt++] = (x))
+
+static char comment_prefix[] = "\t; ";
+short int enable_simd = 0;
+
+static const char *
+core_reg_name(struct arcDisState *state, int val)
+{
+  if (state->coreRegName)
+    return (*state->coreRegName)(state->_this, val);
+  return 0;
+}
+
+static const char *
+aux_reg_name(struct arcDisState *state, int val)
+{
+  if (state->auxRegName)
+    return (*state->auxRegName)(state->_this, val);
+  return 0;
+}
+
+static const char *
+cond_code_name(struct arcDisState *state, int val)
+{
+  if (state->condCodeName)
+    return (*state->condCodeName)(state->_this, val);
+  return 0;
+}
+
+static const char *
+instruction_name(struct arcDisState *state, int op1, int op2, int *flags)
+{
+  if (state->instName)
+    return (*state->instName)(state->_this, op1, op2, flags);
+  return 0;
+}
+
+static void
+mwerror(struct arcDisState *state, const char *msg)
+{
+  if (state->err != 0)
+    (*state->err)(state->_this, (msg));
+}
+
+static const char *
+post_address(struct arcDisState *state, int addr)
+{
+  static char id[3*_NELEM(state->addresses)];
+  unsigned int j, i = state->acnt;
+  if (i < _NELEM(state->addresses)) {
+    state->addresses[i] = addr;
+    ++state->acnt;
+    j = i*3;
+    id[j+0] = '@';
+    id[j+1] = '0'+i;
+    id[j+2] = 0;
+    return id+j;
+  }
+  return "";
+}
+
+static void
+my_sprintf (struct arcDisState *state, char *buf, const char*format, ...)
+{
+  char *bp;
+  const char *p;
+  int size, leading_zero, regMap[2];
+  long auxNum;
+  va_list ap;
+
+  va_start(ap,format);
+  bp = buf;
+  *bp = 0;
+  p = format;
+  auxNum = -1;
+  regMap[0] = 0;
+  regMap[1] = 0;
+  while (1)
+    switch(*p++) {
+    case 0: goto DOCOMM; /*(return) */
+    default:
+      *bp++ = p[-1];
+      break;
+    case '%':
+      size = 0;
+      leading_zero = 0;
+    RETRY: ;
+      switch(*p++)
+	{
+	case '0':
+	case '1':
+	case '2':
+	case '3':
+	case '4':
+	case '5':
+	case '6':
+	case '7':
+	case '8':
+	case '9':
+	  {
+	    /* size. */
+	    size = p[-1]-'0';
+	    if (size == 0) leading_zero = 1; /* e.g. %08x */
+	    while (*p >= '0' && *p <= '9')
+	      size = size*10+*p-'0', p++;
+	    goto RETRY;
+	  }
+#define inc_bp() bp = bp+strlen(bp)
+
+	case 'h':
+	  {
+	    unsigned u = va_arg(ap,int);
+	    /*
+	     * Hex.  We can change the format to 0x%08x in
+	     * one place, here, if we wish.
+	     * We add underscores for easy reading.
+	     */
+#define CDT_DEBUG
+	    if (u > 65536)
+#ifndef CDT_DEBUG
+	      sprintf(bp,"0x%x_%04x",u >> 16, u & 0xffff);
+#else
+	      sprintf(bp,"0x%08x",u);
+#endif // CDT_DEBUG
+	    else
+	      sprintf(bp,"0x%x",u);
+	    inc_bp();
+	  }
+	  break;
+	case 'X': case 'x':
+	  {
+	    int val = va_arg(ap,int);
+	    if (size != 0)
+	      if (leading_zero) sprintf(bp,"%0*x",size,val);
+	      else sprintf(bp,"%*x",size,val);
+	    else sprintf(bp,"%x",val);
+	    inc_bp();
+	  }
+	  break;
+	case 'd':
+	  {
+	    int val = va_arg(ap,int);
+	    if (size != 0) sprintf(bp,"%*d",size,val);
+	    else sprintf(bp,"%d",val);
+	    inc_bp();
+	  }
+	  break;
+	case 'r':
+	  {
+	    /* Register. */
+	    int val = va_arg(ap,int);
+
+#define REG2NAME(num, name) case num: sprintf(bp,""name); \
+			regMap[(num<32)?0:1] |= 1<<(num-((num<32)?0:32)); break;
+	    switch (val)
+	      {
+		REG2NAME(26, "gp");
+		REG2NAME(27, "fp");
+		REG2NAME(28, "sp");
+		REG2NAME(29, "ilink1");
+		REG2NAME(30, "ilink2");
+		REG2NAME(31, "blink");
+		REG2NAME(60, "lp_count");
+		REG2NAME(63, "pcl");
+	      default:
+		{
+		  const char *ext;
+		  ext = core_reg_name(state, val);
+		  if (ext) sprintf(bp, "%s", ext);
+		  else     sprintf(bp,"r%d",val);
+		}break;
+	      }
+	    inc_bp();
+	  } break;
+
+	case 'a':
+	  {
+	  /* Aux Register. */
+	    int val = va_arg(ap,int);
+	    char *ret;
+	    ret = arc_aux_reg_name(val);
+	    if(ret)
+	      sprintf(bp,"%s",ret);
+	    else
+	      {
+		const char *ext;
+		  ext = aux_reg_name(state, val);
+		  if (ext) sprintf(bp, "%s", ext);
+		  else     my_sprintf(state, bp,"%h",val);
+	      }
+
+	    inc_bp();
+	  }
+	  break;
+	case 's':
+	  {
+	    sprintf(bp,"%s",va_arg(ap,char*));
+	    inc_bp();
+	  }
+	  break;
+	case '*':
+	  {
+	    va_arg(ap,char*);
+	    inc_bp();
+	    break;
+	  }
+
+	  /* SIMD operands follow*/
+	case 'S':
+	  {
+	    int val = va_arg (ap,int);
+
+	    sprintf (bp, "vr%d",val);
+	    inc_bp ();
+	    break;
+	  }
+	case 'I':
+	  {
+	    int val = va_arg (ap,int);
+
+	    sprintf (bp, "i%d",val);
+	    inc_bp ();
+	    break;
+	  }
+	case 'D':
+	  {
+	    int val = va_arg (ap,int);
+
+	    sprintf (bp, "dr%d",val);
+	    inc_bp ();
+	    break;
+	  }
+	  /* SIMD operands end */
+	default:
+	  fprintf(stderr,"?? format %c\n",p[-1]);
+	  break;
+	}
+    }
+
+
+ DOCOMM: *bp = 0;
+
+}
+
+static void
+write_comments_(struct arcDisState *state, int shimm, int is_limm, long limm_value)
+{
+  if (state->commentBuffer != 0)
+    {
+      int i;
+      if (is_limm)
+	{
+	  const char *name = post_address(state, limm_value+shimm);
+	  if (*name != 0) WRITE_COMMENT(name);
+	}
+      for(i = 0; i < state->commNum; i++)
+	{
+	  if (i == 0) strcpy(state->commentBuffer, comment_prefix);
+	  else  strcat(state->commentBuffer, ", ");
+	  strncat(state->commentBuffer, state->comm[i], sizeof(state->commentBuffer));
+	}
+    }
+}
+
+#define write_comments2(x)	write_comments_(state, x, is_limm, limm_value)
+#define write_comments()	write_comments2(0)
+
+static const char *condName[] =
+{
+  /* 0..15. */
+  ""   , "z"  , "nz" , "p"  , "n"  , "c"  , "nc" , "v"  ,
+  "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz",
+  "ss" , "sc"
+
+};
+
+static void
+write_instr_name_(struct arcDisState *state,
+		  const char *instrName,
+		  int cond,
+		  int condCodeIsPartOfName,
+		  int flag,
+		  int signExtend,
+		  int addrWriteBack,
+		  int directMem)
+{
+  strcpy(state->instrBuffer, instrName);
+  if (cond > 0)
+    {
+      int condlim = 0; /* condition code limit*/
+      const char *cc = 0;
+      if (!condCodeIsPartOfName) strcat(state->instrBuffer, ".");
+      condlim = 18;
+      if (cond < condlim)
+	cc = condName[cond];
+      else
+	cc = cond_code_name(state, cond);
+      if (!cc) cc = "???";
+      strcat(state->instrBuffer, cc);
+    }
+  if (flag) strcat(state->instrBuffer, ".f");
+  if (state->nullifyMode)
+    strcat(state->instrBuffer, ".d");
+  if (signExtend)    strcat(state->instrBuffer, ".x");
+  switch (addrWriteBack)
+  {
+    case 1: strcat(state->instrBuffer, ".a"); break;
+    case 2: strcat(state->instrBuffer, ".ab"); break;
+    case 3: strcat(state->instrBuffer, ".as"); break;
+  }
+  if (directMem)     strcat(state->instrBuffer, ".di");
+}
+
+#define write_instr_name()	{\
+  write_instr_name_(state, instrName,cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem); \
+ formatString[0] = '\0'; \
+}
+
+enum
+{
+  op_BC = 0, op_BLC = 1, op_LD  = 2, op_ST = 3, op_MAJOR_4  = 4,
+  op_MAJOR_5 = 5, op_SIMD=6,      op_LD_ADD = 12, op_ADD_SUB_SHIFT  = 13,
+  op_ADD_MOV_CMP = 14, op_S = 15, op_LD_S = 16, op_LDB_S = 17,
+  op_LDW_S = 18, op_LDWX_S  = 19, op_ST_S = 20, op_STB_S = 21,
+  op_STW_S = 22, op_Su5     = 23, op_SP   = 24, op_GP    = 25, op_Pcl = 26,
+  op_MOV_S = 27, op_ADD_CMP = 28, op_BR_S = 29, op_B_S   = 30, op_BL_S = 31
+};
+
+extern disassemble_info tm_print_insn_info;
+
+/*
+ * bfd_getm32 - To retrieve the upper 16-bits of the ARCtangent-A5
+ *              basecase (32-bit) instruction
+ */
+static bfd_vma
+bfd_getm32 (data)
+     unsigned int data;
+{
+   bfd_vma value = 0;
+
+   value = ((data & 0xff00) | (data & 0xff)) << 16;
+   value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
+   return value;
+}
+
+/*
+ * bfd_getm32_ac - To retrieve the upper 8-bits of the ARCompact
+ *                 16-bit instruction
+ */
+static bfd_vma
+bfd_getm32_ac (data)
+     unsigned int data;
+{
+   bfd_vma value = 0;
+
+   value = ((data & 0xff) << 8 | (data & 0xff00) >> 8);
+   return value;
+}
+
+/*
+ * sign_extend - Sign Extend the value
+ *
+ */
+static int
+sign_extend (int value, int bits)
+{
+  if (BIT(value, (bits-1)))
+    value |= (0xffffffff << bits);
+  return value;
+}
+
+/* dsmOneArcInst - This module is used to identify the instruction
+ *		   and to decode them based on the ARCtangent-A5
+ *                 instruction set architecture.
+ *                 First, the major opcode is computed. Based on the
+ *		   major opcode and sub opcode, the instruction is
+ * 		   identified. The appropriate decoding class is assigned
+ *		   based on the instruction.Further subopcode 2 is used in
+ *                 cases where decoding upto subopcode1 is not possible.
+ *
+ *		   The instruction is then decoded accordingly.
+ */
+static int
+dsmOneArcInst (bfd_vma addr, struct arcDisState *state, disassemble_info * info)
+{
+
+  int subopcode, mul;
+  int condCodeIsPartOfName=0;
+  int decodingClass;
+  const char *instrName;
+  int fieldAisReg=1, fieldBisReg=1, fieldCisReg=1;
+  int fieldA=0, fieldB=0, fieldC=0;
+  int flag=0, cond=0, is_shimm=0, is_limm=0;
+  long limm_value=0;
+  int signExtend=0, addrWriteBack=0, directMem=0;
+  int is_linked=0;
+  int offset=0;
+  int usesAuxReg = 0;
+  int usesSimdRegA= 0, usesSimdRegB=0, usesSimdRegC=0,simd_scale_u8=-1;
+  int flags = !E_ARC_MACH_A4;
+  char formatString[60];
+
+  state->nullifyMode = BR_exec_when_no_jump;
+  state->isBranch = 0;
+
+  state->_mem_load = 0;
+  state->_ea_present = 0;
+  state->_load_len = 0;
+  state->ea_reg1 = no_reg;
+  state->ea_reg2 = no_reg;
+  state->_offset = 0;
+  state->_addrWriteBack = 0;
+
+  state->instructionLen = info->bytes_per_line;
+
+  /* ARCtangent-A5 basecase instruction and little-endian mode */
+  if ((info->endian == BFD_ENDIAN_LITTLE) && (state->instructionLen == 4))
+    state->words[0] = bfd_getm32(state->words[0]);
+
+  if (state->instructionLen == 4)
+  {
+    if (!NEXT_WORD(0))
+      return 0;
+    /* Get the major opcode of the ARCtangent-A5 32-bit instruction. */
+    state->_opcode = OPCODE(state->words[0]);
+  }
+  else
+  {
+    /* ARCompact 16-bit instruction */
+    if (!NEXT_WORD_AC(0))
+      return 0;
+    /* Get the major opcode of the ARCompact 16-bit instruction. */
+    state->_opcode = OPCODE_AC(state->words[0]);
+  }
+
+  instrName = 0;
+  decodingClass = 0; /* default! */
+  mul = 0;
+  condCodeIsPartOfName=0;
+  state->commNum = 0;
+  state->tcnt = 0;
+  state->acnt = 0;
+  state->flow = noflow;
+
+  if (state->commentBuffer)
+    state->commentBuffer[0] = '\0';
+
+  /* Find the match for the opcode. Once the major opcode category is
+   * identified, get the subopcode to determine the exact instruction.
+   * Based on the instruction identified, select the decoding class.
+   * If condition code is part of the instruction name, then set the
+   * flag 'condCodeIsPartOfName'.
+   * For branch, jump instructions set 'isBranch' (state->isBranch).
+   */
+
+  switch (state->_opcode)
+    {
+    case op_BC:
+    /* Branch Conditionally */
+      instrName = "b";
+      decodingClass = 13;
+      condCodeIsPartOfName = 1;
+      state->isBranch = 1;
+      break;
+
+    case op_BLC:
+    /* Branch and Link, Compare and Branch  */
+      decodingClass = 9;
+      state->isBranch = 1;
+      switch (BITS(state->words[0],16,16))
+      {
+	case 0:
+	  if (!instrName)
+	    instrName = "bl";
+	  decodingClass = 13;
+      	  condCodeIsPartOfName = 1;
+	  break;
+	case 1:
+	  switch (BITS(state->words[0],0,3))
+	  {
+	    case 0: instrName = "breq"; break;
+	    case 1: instrName = "brne"; break;
+	    case 2: instrName = "brlt"; break;
+	    case 3: instrName = "brge"; break;
+	    case 4: instrName = "brlo"; break;
+	    case 5: instrName = "brhs"; break;
+	    case 14: instrName = "bbit0"; break;
+	    case 15: instrName = "bbit1"; break;
+	    default:
+	      instrName = "??? (0[3])";
+	      state->flow = invalid_instr;
+	      break;
+	  }
+	  break;
+	default:
+	  instrName = "??? (0[3])";
+	  state->flow = invalid_instr;
+	  break;
+      }
+      break;
+
+    case op_LD:
+    /* Load register with offset [major opcode 2]  */
+      decodingClass = 6;
+      switch (BITS(state->words[0],7,8))
+      {
+	case 0: instrName  = "ld";  state->_load_len = 4; break;
+	case 1: instrName  = "ldb"; state->_load_len = 1; break;
+	case 2: instrName  = "ldw"; state->_load_len = 2; break;
+	default:
+	  instrName = "??? (0[3])";
+	  state->flow = invalid_instr;
+	  break;
+      }
+      break;
+
+    case op_ST:
+    /* Store register with offset [major opcode 0x03] */
+      decodingClass = 7;
+      switch (BITS(state->words[0],1,2))
+      {
+	case 0: instrName = "st";  break;
+	case 1: instrName = "stb"; break;
+  	case 2: instrName = "stw"; break;
+	default:
+	  instrName = "??? (2[3])";
+	  state->flow = invalid_instr;
+	  break;
+      }
+      break;
+
+    case op_MAJOR_4:
+    /* ARC 32-bit basecase instructions with 3 Operands */
+      decodingClass = 0;  /* Default for 3 operand instructions */
+      subopcode = BITS(state->words[0],16,21);
+      switch (subopcode)
+        {
+	case 0: instrName = "add";  break;
+	case 1: instrName = "adc";  break;
+	case 2: instrName = "sub";  break;
+	case 3: instrName = "sbc";  break;
+	case 4: instrName = "and";  break;
+	case 5: instrName = "or";   break;
+	case 6: instrName = "bic";  break;
+	case 7: instrName = "xor";  break;
+	case 8: instrName = "max";  break;
+	case 9: instrName = "min";  break;
+	case 10:
+	  {
+	    if(state->words[0] == 0x264a7000)
+	      {
+		instrName = "nop";
+		decodingClass = 26;
+	      }
+	    else
+	      {
+		instrName = "mov";
+		decodingClass = 12;
+	      }
+	    break;
+	  }
+	case 11: instrName = "tst"; decodingClass = 2; break;
+	case 12: instrName = "cmp"; decodingClass = 2; break;
+	case 13: instrName = "rcmp"; decodingClass = 2; break;
+	case 14: instrName = "rsub"; break;
+	case 15: instrName = "bset"; break;
+	case 16: instrName = "bclr"; break;
+	case 17: instrName = "btst"; decodingClass = 2; break;
+	case 18: instrName = "bxor"; break;
+	case 19: instrName = "bmsk"; break;
+	case 20: instrName = "add1"; break;
+	case 21: instrName = "add2"; break;
+	case 22: instrName = "add3"; break;
+	case 23: instrName = "sub1"; break;
+	case 24: instrName = "sub2"; break;
+	case 25: instrName = "sub3"; break;
+	case 26: instrName = "mpylo"; break;
+	case 27: instrName = "mpyhi"; break;
+	case 28: instrName = "mpyhiu";break;
+	case 29: instrName = "mpylou";break;
+        case 32:
+        case 33:
+	  instrName = "j";
+        case 34:
+        case 35:
+	  if (!instrName) instrName = "jl";
+	  decodingClass = 4;
+	  condCodeIsPartOfName = 1;
+          state->isBranch = 1;
+	  break;
+        case 40:
+	  instrName = "lp";
+	  decodingClass = 11;
+	  condCodeIsPartOfName = 1;
+          state->isBranch = 1;
+	  break;
+        case 41: instrName = "flag"; decodingClass = 3; break;
+        case 42: instrName = "lr"; decodingClass = 10;  break;
+        case 43: instrName = "sr"; decodingClass =  8;  break;
+        case 47:
+	  decodingClass = 1;
+          switch (BITS(state->words[0],0,5)) /* Checking based on Subopcode2 */
+	  {
+	  case 0: instrName = "asl";  break;
+	  case 1: instrName = "asr";  break;
+	  case 2: instrName = "lsr";  break;
+	  case 3: instrName = "ror";  break;
+	  case 4: instrName = "rrc";  break;
+	  case 5: instrName = "sexb"; break;
+	  case 6: instrName = "sexw"; break;
+	  case 7: instrName = "extb"; break;
+	  case 8: instrName = "extw"; break;
+	  case 9: instrName = "abs";  break;
+	  case 10: instrName = "not"; break;
+	  case 11: instrName = "rlc"; break;
+	  case 12:  instrName = "ex";
+
+
+	    decodingClass = 34;
+	    break; // ramana adds
+
+	  case 63:
+	    decodingClass = 26;
+	    switch (BITS(state->words[0],24,26))
+	      {
+	      case 1 : instrName = "sleep"; decodingClass = 32; break;
+	      case 2 :
+		if((info->mach) == ARC_MACH_ARC7)
+		  instrName = "trap0";
+		else
+		  instrName = "swi";
+		break;
+	      case 3:
+
+		if(BITS(state->words[0],22,23) == 1)
+		  instrName = "sync" ;
+
+		break;
+	      case 4 : instrName = "rtie" ; break;
+	      case 5 : instrName = "brk"; break;
+	      default:
+
+		instrName = "???";
+		state->flow=invalid_instr;
+		break;
+	      }
+	    break;
+	  }
+	  break;
+      }
+
+      if (!instrName)
+      {
+        subopcode = BITS(state->words[0],17,21);
+	decodingClass = 5;
+	switch (subopcode)
+    	{
+	  case 24: instrName  = "ld";   state->_load_len = 4; break;
+	  case 25: instrName  = "ldb";  state->_load_len = 1; break;
+	  case 26: instrName  = "ldw";  state->_load_len = 2; break;
+	  default:
+	    instrName = "??? (0[3])";
+	    state->flow = invalid_instr;
+	    break;
+	}
+      }
+      break;
+
+    case op_MAJOR_5:
+    /* ARC 32-bit extension instructions */
+      decodingClass = 0;  /* Default for Major opcode 5 ... */
+      subopcode = BITS(state->words[0],16,21);
+      switch (subopcode)
+      {
+	case 0: instrName = "asl"; break;
+	case 1: instrName = "lsr"; break;
+	case 2: instrName = "asr"; break;
+	case 3: instrName = "ror"; break;
+	case 4: instrName = "mul64"; mul =1; decodingClass = 2; break;
+	case 5: instrName = "mulu64"; mul =1; decodingClass = 2; break;
+
+	  /* ARC A700 */
+      case 6: instrName = "adds" ;break;
+
+      case 7: instrName = "subs"; break;
+      case 8: instrName = "divaw"; break;
+      case 0xA: instrName = "asls"; break;
+      case 0xB: instrName = "asrs"; break;
+      case 0x28: instrName = "addsdw";break;
+      case 0x29: instrName = "subsdw"; break;
+
+      case 47:
+	switch(BITS(state->words[0],0,5))
+	  {
+	  case 0: instrName = "swap"; decodingClass = 1; break;
+	  case 1: instrName = "norm"; decodingClass = 1; break;
+	    /* ARC A700 DSP Extensions */
+	  case 2: instrName = "sat16"; decodingClass = 1; break;
+	  case 3: instrName = "rnd16"; decodingClass = 1; break;
+	  case 4: instrName = "abssw"; decodingClass = 1; break;
+	  case 5: instrName = "abss"; decodingClass = 1; break;
+	  case 6: instrName = "negsw"; decodingClass = 1; break;
+	  case 7: instrName = "negs"; decodingClass = 1; break;
+
+
+	  case 8: instrName = "normw"; decodingClass = 1; break;
+	  default:
+	    instrName = "???";
+	    state->flow =invalid_instr;
+	    break;
+
+	  }
+	break;
+      default:
+	instrName = "??? (2[3])";
+	state->flow = invalid_instr;
+	break;
+      }
+    break;
+
+
+    /* Aurora SIMD instruction support*/
+  case op_SIMD:
+
+    if (enable_simd)
+      {
+	decodingClass = 42;
+	subopcode     = BITS(state->words[0], 17, 23);
+
+	switch (subopcode)
+	  {
+
+	  case 68:
+	    instrName = "vld32";
+	    decodingClass = 37;
+	    usesSimdRegA=1;
+	    usesSimdRegB=2;
+	    usesSimdRegC=0;
+	    simd_scale_u8 = 2;
+	    break;
+
+	  case 72:
+	    instrName = "vld64";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 3;
+	    break;
+
+	  case 74:
+	    instrName = "vld64w";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 3;
+	    break;
+
+	  case 70:
+	    instrName = "vld32wl";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 2;
+	    break;
+
+	  case 66:
+	    instrName = "vld32wh";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 2;
+	    break;
+
+	  case 76:
+	    instrName = "vld128";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 4;
+	    break;
+
+	  case 78:
+	    {
+	      short  sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vld128r";
+		  decodingClass = 38;
+		  usesSimdRegA  = 1;
+		  usesSimdRegB  = usesSimdRegC = 0;
+		  break;
+		default:
+		  instrName = "SIMD";
+		  state->flow = invalid_instr;
+		}
+	    }
+	    break;
+	  case 71:
+	    instrName = "vst16_0";
+	    decodingClass = 37;
+	    usesSimdRegA = 1;
+	    usesSimdRegB = 2;
+	    usesSimdRegC = 0;
+	    simd_scale_u8 = 1;
+	    break;
+
+	  case 81:
+	    instrName = "vst16_1";
+	    decodingClass = 37;
+	    usesSimdRegA = 1;
+	    usesSimdRegB = 2;
+	    usesSimdRegC = 0;
+	    simd_scale_u8 = 1;
+	    break;
+
+	  case 67:
+	    instrName = "vst16_2";
+	    decodingClass = 37;
+	    usesSimdRegA = 1;
+	    usesSimdRegB = 2;
+	    usesSimdRegC = 0;
+	    simd_scale_u8 = 1;
+	    break;
+
+	  case 75:
+	    instrName = "vst16_3";
+	    decodingClass = 37;
+	    usesSimdRegA = 1;
+	    usesSimdRegB = 2;
+	    usesSimdRegC = 0;
+	    simd_scale_u8 = 1;
+	    break;
+
+	  case 83:
+	    instrName = "vst16_4";
+	    decodingClass = 37;
+	    usesSimdRegA = 1;
+	    usesSimdRegB = 2;
+	    usesSimdRegC = 0;
+	    simd_scale_u8 = 1;
+	    break;
+
+	  case 89:
+	    instrName = "vst16_5";
+	    decodingClass = 37;
+	    usesSimdRegA = 1;
+	    usesSimdRegB = 2;
+	    usesSimdRegC = 0;
+	    simd_scale_u8 = 1;
+	    break;
+
+	  case 91:
+	    instrName = "vst16_6";
+	    decodingClass = 37;
+	    usesSimdRegA = 1;
+	    usesSimdRegB = 2;
+	    usesSimdRegC = 0;
+	    simd_scale_u8 = 1;
+	    break;
+
+	  case 93:
+	    instrName = "vst16_7";
+	    decodingClass = 37;
+	    usesSimdRegA = 1;
+	    usesSimdRegB = 2;
+	    usesSimdRegC = 0;
+	    simd_scale_u8 = 1;
+	    break;
+
+	  case 69:
+	    instrName = "vst32_0";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 2;
+	    break;
+
+	  case 82:
+	    instrName = "vst32_2";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 2;
+	    break;
+
+	  case 86:
+	    instrName = "vst32_4";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 2;
+	    break;
+
+	  case 88:
+	    instrName = "vst32_6";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 2;
+	    break;
+
+	  case 73:
+	    instrName = "vst64";
+	    decodingClass = 37 ;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 3;
+	    break;
+
+	  case 77:
+	    instrName = "vst128";
+	    decodingClass = 37;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = 2;
+	    usesSimdRegC  = 0;
+	    simd_scale_u8 = 4;
+	    break;
+
+	  case 79:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vst128r";
+		  decodingClass = 38;
+		  usesSimdRegA = 1;
+		  usesSimdRegB = usesSimdRegC = 0;
+		  break;
+
+		default:
+		  instrName = "SIMD";
+		  state->flow = invalid_instr;
+		}
+
+	    }
+	    break;
+	  case 80:
+	    instrName = "vmvw";
+	    usesSimdRegA = usesSimdRegB = 1;
+	    usesSimdRegC = 0;
+	    decodingClass = 39;
+	    break;
+
+	  case 84:
+	    instrName = "vmvzw";
+	    decodingClass = 39;
+	    usesSimdRegA = usesSimdRegB = 1;
+	    usesSimdRegC = 0;
+	    break;
+
+	  case 90:
+	    instrName = "vmovw";
+	    decodingClass = 39;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = usesSimdRegC = 0;
+	    break;
+
+	  case 94:
+	    instrName = "vmovzw";
+	    decodingClass = 39;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = usesSimdRegC = 0;
+	    break;
+
+	  case 85:
+	    instrName = "vmvaw";
+	    decodingClass = 39;
+	    usesSimdRegA  = usesSimdRegB = 1;
+	    usesSimdRegC  = 0;
+	    break;
+
+	  case 95:
+	    instrName = "vmovaw";
+	    decodingClass = 39;
+	    usesSimdRegA  = 1;
+	    usesSimdRegB  = usesSimdRegC = 0;
+	    break;
+
+	  case 10:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vaddw"; decodingClass = 42;
+		  usesSimdRegA = usesSimdRegB = usesSimdRegC =1;
+		  break;
+
+		case 1:
+		  instrName = "vaddaw"; decodingClass = 42;
+		  usesSimdRegA = usesSimdRegB = usesSimdRegC =1;
+		  break;
+
+		case 2:
+		  instrName = "vbaddw"; decodingClass = 42;
+		  usesSimdRegA = usesSimdRegB = 1;
+		  usesSimdRegC = 0;
+		  break;
+		}
+	      break;
+	    }
+
+	  case 11:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vsubw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+
+		case 1:
+		  instrName = "vsubaw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+
+		case 2:
+		  instrName = "vbsubw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+		}
+	    }
+	    break;
+
+	  case 12:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vmulw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+
+		case 1:
+		  instrName = "vmulaw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+
+		case 2:
+		  instrName = "vbmulw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+
+		case 3:
+		  instrName = "vbmulaw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+		}
+	    }
+	    break;
+
+	  case 13:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vmulfw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+
+		case 1:
+		  instrName = "vmulfaw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+
+		case 2:
+		  instrName = "vbmulfw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+		}
+	    }
+	    break;
+
+	  case 15:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vsummw";
+		  decodingClass = 42;
+		  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+		case 2:
+		  instrName = "vbrsubw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+		}
+	    }
+	    break;
+
+	  case 23:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vmr7w";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+
+		case 1:
+		  instrName = "vmr7aw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+
+
+		case 2:
+		  switch (BITS(state->words[0], 0, 5))
+		    {
+		    case 0:
+		      instrName = "vaddsuw";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 1:
+		      instrName = "vabsw";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 2:
+		      instrName = "vsignw";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 3:
+		      instrName = "vupbw";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 4:
+		      instrName = "vexch1";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 5:
+		      instrName = "vexch2";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 6:
+		      instrName = "vexch4";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 7:
+		      instrName = "vupsbw";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 8:
+		      instrName = "vdirun";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = usesSimdRegA = 0;
+		      break;
+
+		    case 9:
+		      instrName = "vdorun";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = usesSimdRegA = 0;
+		      break;
+
+		    case 10:
+		      instrName = "vdiwr";
+		      decodingClass = 40;
+		      usesSimdRegB  = 3;
+		      usesSimdRegA  = usesSimdRegC = 0;
+		      fieldCisReg   = 1;
+		      break;
+
+		    case 11:
+		      instrName = "vdowr";
+		      decodingClass = 40;
+		      usesSimdRegB  = 3;
+		      usesSimdRegA  = usesSimdRegC = 0;
+		      fieldCisReg   = 1;
+		      break;
+
+		    case 12:
+		      instrName = "vdird";
+		      decodingClass = 40;
+		      usesSimdRegB  = 1;
+		      usesSimdRegC  = 3;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 13:
+		      instrName = "vdord";
+		      decodingClass = 40;
+		      usesSimdRegB  = 1;
+		      usesSimdRegC  = 3;
+		      usesSimdRegA  = 0;
+		      break;
+
+		    case 63:
+		      {
+			switch (BITS(state->words[0], 24, 25))
+			  {
+			  case 0:
+			    instrName = "vrec";
+			    decodingClass = 43;
+			    usesSimdRegC  = 0;
+			    usesSimdRegB  = usesSimdRegA = 0;
+			    break;
+
+			  case 1:
+			    instrName = "vrecrun";
+			    decodingClass = 43;
+			    usesSimdRegC  = 0;
+			    usesSimdRegA  = usesSimdRegB = 0;
+			    break;
+
+			  case 2:
+			    instrName = "vrun";
+			    decodingClass = 43;
+			    usesSimdRegC  = 0;
+			    usesSimdRegB  = usesSimdRegA = 0;
+			    break;
+
+			  case 3:
+			    instrName = "vendrec";
+			    decodingClass = 43;
+			    usesSimdRegC  = 0;
+			    usesSimdRegB  = usesSimdRegA = 0;
+			    break;
+			  }
+		      }
+		      break;
+		    }
+		  break;
+
+		case 3:
+		  switch (BITS(state->words[0], 0, 2))
+		    {
+		    case 1:
+		      instrName = "vabsaw";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+		    case 3:
+		      instrName = "vupbaw";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+		    case 7:
+		      instrName = "vupsbaw";
+		      decodingClass = 40;
+		      usesSimdRegC  = usesSimdRegB = 1;
+		      usesSimdRegA  = 0;
+		      break;
+		    }
+		  break;
+		}
+	    }
+	    break;
+
+	  case 16:
+	    instrName = "vasrw";
+	    decodingClass = 42;
+	    usesSimdRegA  = usesSimdRegB = 1;
+	    usesSimdRegC  = 2;
+	    break;
+
+	  case 48:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vasrwi";
+		  decodingClass = 41;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+		case 2:
+		  instrName = "vasrrwi";
+		  decodingClass = 41;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+		}
+	    }
+	    break;
+
+	  case 59:
+	    instrName = "vasrsrwi";
+	    decodingClass = 41;
+	    usesSimdRegA  = usesSimdRegB = 1;
+	    usesSimdRegC  = 0;
+	    break;
+
+	  case 18:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vmaxw";
+		  usesSimdRegC = 1;
+		  break;
+		case 1:
+		  instrName = "vmaxaw";
+		  usesSimdRegC = 1;
+		  break;
+		case 2:
+		  instrName = "vbmaxw";
+		  usesSimdRegC = 0;
+		  break;
+		}
+	      decodingClass = 42;
+	      usesSimdRegA  = usesSimdRegB = 1;
+	      break;
+	    }
+
+	  case 19:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vminw";
+		  usesSimdRegC = 1;
+		  break;
+		case 1:
+		  instrName = "vminaw";
+		  usesSimdRegC = 0;
+		  break;
+		case 2:
+		  instrName = "vbminw";
+		  usesSimdRegC = 0;
+		  break;
+		}
+	      decodingClass = 42;
+	      usesSimdRegA  = usesSimdRegB = 1;
+	      break;
+	    }
+
+	  case 14:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vdifw";
+		  break;
+		case 1:
+		  instrName = "vdifaw";
+		  break;
+		case 2:
+		  instrName = "vmrb";
+		  break;
+		}
+	      decodingClass = 42;
+	      usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	      break;
+	    }
+
+	  case 24:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vand";
+		  decodingClass = 42;
+		  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+		case 1:
+		  instrName = "vandaw";
+		  decodingClass = 42;
+		  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+		}
+	      break;
+	    }
+
+	  case 25:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vor";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+		  break;
+		}
+	      break;
+	    }
+
+	  case 26:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vxor";
+		  break;
+		case 1:
+		  instrName = "vxoraw";
+		  break;
+		}
+	      decodingClass = 42;
+	      usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	      break;
+	    }
+
+	  case 27:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vbic";
+		  break;
+		case 1:
+		  instrName = "vbicaw";
+		  break;
+		}
+	      decodingClass = 42;
+	      usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	      break;
+	    }
+
+	  case 4:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vavb";
+		  break;
+		case 2:
+		  instrName = "vavrb";
+		  break;
+		}
+	      decodingClass = 42;
+	      usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	      break;
+	    }
+
+	  case 28:
+	    instrName = "veqw";
+	    decodingClass = 42;
+	    usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	    break;
+
+	  case 29:
+	    instrName = "vnew";
+	    decodingClass = 42;
+	    usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	    break;
+
+	  case 30:
+	    instrName = "vlew";
+	    decodingClass = 42;
+	    usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	    break;
+
+	  case 31:
+	    instrName = "vltw";
+	    decodingClass = 42;
+	    usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	    break;
+
+	  case 49:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vasrpwbi";
+		  decodingClass = 41;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+		case 2:
+		  instrName = "vasrrpwbi";
+		  decodingClass = 41;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+		}
+	      break;
+	    }
+
+	  case 5:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vsr8";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 2;
+		  break;
+
+		case 1:
+		  instrName = "vsr8aw";
+		  decodingClass = 42;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 2;
+		  break;
+		}
+	      break;
+	    }
+
+	  case 37:
+	    {
+	      short sub_subopcode = BITS(state->words[0], 15, 16);
+	      switch (sub_subopcode)
+		{
+		case 0:
+		  instrName = "vsr8i";
+		  decodingClass = 41;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+
+		case 1:
+		  instrName = "vsr8awi";
+		  decodingClass = 41;
+		  usesSimdRegA  = usesSimdRegB = 1;
+		  usesSimdRegC  = 0;
+		  break;
+		}
+	      break;
+	    }
+
+	  case 20:
+	  case 21:
+	  case 22:
+	    {
+	      short subopcode2 = BITS(state->words[0], 15, 18);
+	      switch (subopcode2)
+		{
+		case 0:
+		  instrName = "vmr1w";
+		  break;
+
+		case 2:
+		  instrName = "vmr2w";
+		  break;
+
+		case 4:
+		  instrName = "vmr3w";
+		  break;
+
+		case 6:
+		  instrName = "vmr4w";
+		  break;
+
+		case 8:
+		  instrName = "vmr5w";
+		  break;
+
+		case 10:
+		  instrName = "vmr6w";
+		  break;
+
+		case 1:
+		  instrName = "vmr1aw";
+		  break;
+
+		case 3:
+		  instrName = "vmr2aw";
+		  break;
+
+		case 5:
+		  instrName = "vmr3aw";
+		  break;
+
+		case 7:
+		  instrName = "vmr4aw";
+		  break;
+
+		case 9:
+		  instrName = "vmr5aw";
+		  break;
+
+		case 11:
+		  instrName = "vmr6aw";
+		  break;
+
+		}
+
+	      decodingClass = 42;
+	      usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	      break;
+	    }
+
+
+	  case 7:
+	  case 6:
+	    {
+	      switch (BITS(state->words[0], 16, 19))
+		{
+		case 15:
+		  instrName = "vh264ft";
+		  break;
+		case 14:
+		  instrName = "vh264f";
+		  break;
+		case 13:
+		  instrName = "vvc1ft";
+		  break;
+		case 12:
+		  instrName = "vvc1f";
+		  break;
+		}
+	      decodingClass = 42;
+	      usesSimdRegA  = usesSimdRegB = usesSimdRegC = 1;
+	      break;
+
+	    }
+
+	  case 92:
+	    instrName = "vd6tapf";
+	    decodingClass = 39;
+	    usesSimdRegA  = usesSimdRegB = 1;
+	    usesSimdRegC  = 0;
+	    break;
+
+	  case 55:
+	    instrName = "vinti";
+	    decodingClass = 43;
+	    usesSimdRegA  = usesSimdRegB = usesSimdRegC = 0;
+	    break;
+
+	  default:
+	    instrName = "SIMD";
+	    state->flow = invalid_instr;
+	    break;
+	  }
+      }
+    else
+      {
+	instrName = "???_SIMD";
+	state->flow = invalid_instr;
+      }
+	break;
+
+
+    case op_LD_ADD:
+    /* Load/Add resister-register */
+      decodingClass = 15;  /* default for Major opcode 12 ... */
+      switch(BITS(state->words[0],3,4))
+	{
+	case 0: instrName = "ld_s"; break;
+	case 1: instrName = "ldb_s"; break;
+	case 2: instrName = "ldw_s"; break;
+	case 3: instrName = "add_s"; break;
+        default:
+	  instrName = "??? (2[3])";
+	  state->flow = invalid_instr;
+	  break;
+	}
+      break;
+
+  case op_ADD_SUB_SHIFT:
+    /* Add/sub/shift immediate */
+    decodingClass = 16;  /* default for Major opcode 13 ... */
+    switch(BITS(state->words[0],3,4))
+      {
+      case 0: instrName = "add_s"; break;
+      case 1: instrName = "sub_s"; break;
+      case 2: instrName = "asl_s"; break;
+      case 3: instrName = "asr_s"; break;
+      default:
+	instrName = "??? (2[3])";
+	state->flow = invalid_instr;
+	break;
+      }
+    break;
+
+    case op_ADD_MOV_CMP:
+    /* One Dest/Source can be any of r0 - r63 */
+      decodingClass = 17;  /* default for Major opcode 14 ... */
+      switch(BITS(state->words[0],3,4))
+      {
+	case 0: instrName = "add_s"; break;
+	case 1:
+	case 3: instrName = "mov_s"; decodingClass = 18; break;
+	case 2: instrName = "cmp_s"; decodingClass = 18; break;
+        default:
+	  instrName = "??? (2[3])";
+	  state->flow = invalid_instr;
+	  break;
+      }
+      break;
+
+    case op_S:
+    /* ARCompact 16-bit instructions, General ops/ single ops */
+      decodingClass = 22;  /* default for Major opcode 15 ... */
+      switch(BITS(state->words[0],0,4))
+      {
+	case 0:
+	  decodingClass = 27;
+          switch(BITS(state->words[0],5,7))
+	  {
+            case 0 : instrName = "j_s";
+            case 2 : if (!instrName) instrName = "jl_s";
+	             state->isBranch = 1;
+		     state->nullifyMode = BR_exec_when_no_jump;
+		     break;
+            case 1 : if (!instrName) instrName = "j_s.d";
+            case 3 : if (!instrName) instrName = "jl_s.d";
+          	     state->isBranch = 1;
+		     state->nullifyMode = BR_exec_always;
+		     break;
+            case 6 : instrName = "sub_s.ne";
+	             decodingClass = 35;
+	             break;
+            case 7 :
+	      decodingClass = 26;
+              switch(BITS(state->words[0],8,10))
+	      {
+              	case 0 : instrName = "nop_s"; break;
+
+		  /* Unimplemented instruction reserved in ARC700 */
+	        case 1: instrName = "unimp_s";break;
+
+
+	        case 4: instrName = "jeq_s [blink]";
+		case 5: if (!instrName) instrName = "jne_s [blink]";
+		case 6:
+		  if (!instrName)
+		    instrName = "j_s [blink]";
+		  state->isBranch = 1;
+		  state->nullifyMode = BR_exec_when_no_jump;
+		  break;
+		case 7:
+		  if (!instrName)
+		    {
+		      instrName = "j_s.d [blink]";
+		      state->flow = indirect_jump;
+		      state->register_for_indirect_jump = 31; /* blink is r31 */
+		    }
+		  state->isBranch = 1;
+		  state->nullifyMode = BR_exec_always;
+		  break;
+                default:
+		  instrName = "??? (2[3])";
+	      	  state->flow = invalid_instr;
+		  break;
+	      }
+	      break;
+            default:
+	      instrName = "??? (2[3])";
+	      state->flow = invalid_instr;
+	      break;
+	  }
+	  break;
+        case 2 : instrName = "sub_s"; break;
+        case 4 : instrName = "and_s"; break;
+        case 5 : instrName = "or_s"; break;
+        case 6 : instrName = "bic_s"; break;
+        case 7 : instrName = "xor_s"; break;
+	case 11: instrName = "tst_s"; decodingClass = 14; break;
+	case 12: instrName = "mul64_s"; mul =1; decodingClass = 14; break;
+	case 13: instrName = "sexb_s"; decodingClass = 14; break;
+	case 14: instrName = "sexw_s"; decodingClass = 14; break;
+	case 15: instrName = "extb_s"; decodingClass = 14; break;
+	case 16: instrName = "extw_s"; decodingClass = 14; break;
+	case 17: instrName = "abs_s"; decodingClass = 14; break;
+	case 18: instrName = "not_s"; decodingClass = 14; break;
+	case 19: instrName = "neg_s"; decodingClass = 14; break;
+        case 20: instrName = "add1_s"; break;
+        case 21: instrName = "add2_s"; break;
+        case 22: instrName = "add3_s"; break;
+        case 24: instrName = "asl_s"; break;
+        case 25: instrName = "lsr_s"; break;
+        case 26: instrName = "asr_s"; break;
+        case 27: instrName = "asl_s"; decodingClass = 14; break;
+        case 28: instrName = "asr_s"; decodingClass = 14; break;
+        case 29: instrName = "lsr_s"; decodingClass = 14; break;
+      case 30: instrName = "trap_s"; decodingClass = 33; break;
+      case 31: instrName = "brk_s"; decodingClass = 26; break;
+
+        default:
+	  instrName = "??? (2[3])";
+	  state->flow = invalid_instr;
+	  break;
+      }
+      break;
+
+       case op_LD_S:
+    /* ARCompact 16-bit Load with offset, Major Opcode 0x10 */
+      instrName = "ld_s";
+      decodingClass = 28;
+      break;
+
+    case op_LDB_S:
+    /* ARCompact 16-bit Load with offset, Major Opcode 0x11 */
+      instrName = "ldb_s";
+      decodingClass = 28;
+      break;
+
+    case op_LDW_S:
+    /* ARCompact 16-bit Load with offset, Major Opcode 0x12 */
+      instrName = "ldw_s";
+      decodingClass = 28;
+      break;
+
+    case op_LDWX_S:
+    /* ARCompact 16-bit Load with offset, Major Opcode 0x13 */
+      instrName = "ldw_s.x";
+      decodingClass = 28;
+      break;
+
+    case op_ST_S:
+    /* ARCompact 16-bit Store with offset, Major Opcode 0x14 */
+      instrName = "st_s";
+      decodingClass = 28;
+      break;
+
+    case op_STB_S:
+    /* ARCompact 16-bit Store with offset, Major Opcode 0x15 */
+      instrName = "stb_s";
+      decodingClass = 28;
+      break;
+
+    case op_STW_S:
+    /* ARCompact 16-bit Store with offset, Major Opcode 0x16 */
+      instrName = "stw_s";
+      decodingClass = 28;
+      break;
+
+    case op_Su5:
+    /* ARCompact 16-bit involving unsigned 5-bit immediate operand */
+      decodingClass = 23;  /* default for major opcode 0x17 ... */
+      switch (BITS(state->words[0],5,7))
+      {
+	case 0: instrName = "asl_s"; break;
+	case 1: instrName = "lsr_s"; break;
+	case 2: instrName = "asr_s"; break;
+	case 3: instrName = "sub_s"; break;
+	case 4: instrName = "bset_s"; break;
+	case 5: instrName = "bclr_s"; break;
+	case 6: instrName = "bmsk_s"; break;
+	case 7: instrName = "btst_s"; decodingClass = 21; break;
+      }
+      break;
+
+    case op_SP:
+    /* ARCompact 16-bit Stack pointer-based instructions */
+      decodingClass = 19;  /* default for Stack pointer-based insns ... */
+      switch (BITS(state->words[0],5,7))
+      {
+        case 0: instrName = "ld_s"; break;
+        case 1: instrName = "ldb_s"; break;
+        case 2: instrName = "st_s"; break;
+        case 3: instrName = "stb_s"; break;
+        case 4: instrName = "add_s"; break;
+        case 5:
+      	  if (!BITS(state->words[0],8,8))
+	    instrName = "add_s";
+	  else
+	    instrName = "sub_s";
+	  break;
+        case 6: instrName = "pop_s"; decodingClass = 31; break;
+        case 7: instrName = "push_s"; decodingClass = 31; break;
+	default:
+          instrName = "??? (2[3])";
+          state->flow = invalid_instr;
+	  break;
+      }
+    break;
+
+    case op_GP:
+    /* ARCompact 16-bit Gp-based ld/add (data aligned offset) */
+      decodingClass = 20;  /* default for gp-relative insns ... */
+      switch (BITS(state->words[0],9,10))
+      {
+        case 0: instrName = "ld_s"; break;
+        case 1: instrName = "ldb_s"; break;
+        case 2: instrName = "ldw_s"; break;
+        case 3: instrName = "add_s"; break;
+      }
+      break;
+
+    case op_Pcl:
+    /* ARCompact 16-bit Pcl-based ld (32-bit aligned offset) */
+      instrName = "ld_s";
+      decodingClass = 29;
+      break;
+
+    case op_MOV_S:
+    /* ARCompact 16-bit Move immediate */
+      instrName = "mov_s";
+      decodingClass = 30;
+      break;
+
+    case op_ADD_CMP:
+    /* ARCompact 16-bit Add/compare immediate */
+      decodingClass = 21;  /* default for major opcode 0x1c ... */
+      if (BIT(state->words[0],7))
+	instrName = "cmp_s";
+      else
+	instrName = "add_s";
+      break;
+
+    case op_BR_S:
+    /* ARCompact 16-bit Branch conditionally on reg z/nz */
+      decodingClass = 25; /* Default for BR_S instruction ... */
+      if (BIT(state->words[0],7))
+	instrName = "brne_s";
+      else
+	instrName = "breq_s";
+      state->isBranch = 1;
+      break;
+
+    case op_B_S:
+    /* ARCompact 16-bit Branch conditionally */
+      decodingClass = 24; /* Default for B_S instruction ... */
+      state->isBranch = 1;
+      switch (BITS(state->words[0],9,10))
+      {
+	case 0: instrName = "b_s"; break;
+	case 1: instrName = "beq_s"; break;
+	case 2: instrName = "bne_s"; break;
+	case 3:
+          switch (BITS(state->words[0],6,8))
+	  {
+	    case 0: instrName = "bgt_s"; break;
+	    case 1: instrName = "bge_s"; break;
+	    case 2: instrName = "blt_s"; break;
+	    case 3: instrName = "ble_s"; break;
+	    case 4: instrName = "bhi_s"; break;
+	    case 5: instrName = "bhs_s"; break;
+	    case 6: instrName = "blo_s"; break;
+	    case 7: instrName = "bls_s"; break;
+	  }
+	  break;
+      }
+      break;
+
+    case op_BL_S:
+    /* ARCompact 16-bit Branch and link unconditionally */
+      decodingClass = 24; /* Default for B_S instruction ... */
+      instrName = "bl_s";
+      state->isBranch = 1;
+      break;
+
+    default:
+      instrName = instruction_name (state, state->_opcode, 0, &flags);
+      if (!instrName)
+	{
+	  instrName = "???";
+	  state->flow=invalid_instr;
+	}
+      break;
+  }
+
+  /* Maybe we should be checking for extension instructions over here
+   * instead of all over this crazy switch case. */
+  if (state->flow == invalid_instr)
+    {
+      if (!((state->_opcode == op_SIMD) && enable_simd))
+	instrName = instruction_name(state,state->_opcode,
+				     state->words[0],
+				     &flags);
+
+      if (state->instructionLen == 2)
+	{
+	  switch (flags)
+	    {
+	    case AC_SYNTAX_3OP:
+	      decodingClass = 22;
+	      break;
+	    case AC_SYNTAX_2OP:
+	      decodingClass = 14;
+	      break;
+	    case AC_SYNTAX_1OP:
+	      decodingClass = 36;
+	      break;
+	    case AC_SYNTAX_NOP:
+	      decodingClass = 26;
+	      break;
+	    default:
+	      mwerror(state, "Invalid syntax class\n");
+	    }
+	}
+      else
+	{
+/* Must do the above for this one too */
+	  switch (flags)
+	    {
+	    case AC_SYNTAX_3OP:
+	      decodingClass = 0;
+	      break;
+	    case AC_SYNTAX_2OP:
+	      decodingClass = 1;
+	      break;
+	    case AC_SYNTAX_1OP:
+	      decodingClass = 32;
+	      break;
+	    case AC_SYNTAX_NOP:
+	      break;
+	    case AC_SYNTAX_SIMD:
+	      break;
+	    default:
+	      mwerror(state, "Invalid syntax class\n");
+	    }
+	}
+
+      if (!instrName)
+	{
+	  instrName = "???";
+	  state->flow=invalid_instr;
+	}
+    }
+
+  fieldAisReg = fieldBisReg = fieldCisReg = 1; /* assume regs for now */
+  flag = cond = is_shimm = is_limm = 0;
+  signExtend = addrWriteBack = directMem = 0;
+  usesAuxReg = 0;
+
+  /* The following module decodes the instruction */
+  switch (decodingClass)
+  {
+    case 0:
+
+      /* For ARCtangent 32-bit instructions with 3 operands */
+
+      subopcode = BITS(state->words[0],22,23);
+      switch (subopcode)
+      {
+	case 0:
+
+          /* Either fieldB or fieldC or both can be a limm value;
+	   * fieldA can be 0;
+           */
+
+          CHECK_FIELD_C();
+     	  if (!is_limm)
+	  {
+	    /* If fieldC is not a limm, then fieldB may be a limm value */
+            CHECK_FIELD_B();
+	  }
+      	  else
+	  {
+            FIELD_B();
+      	    if (!fieldBisReg)
+	      fieldB = fieldC;
+	  }
+      	  CHECK_FIELD_A();
+      	  CHECK_FLAG();
+	  break;
+
+	case 1:
+
+          /* fieldB may ba a limm value
+	   * fieldC is a shimm (unsigned 6-bit immediate)
+	   * fieldA can be 0
+           */
+
+          CHECK_FIELD_B();
+          FIELD_C();
+	  fieldCisReg = 0;
+          /* Say ea is not present, so only one of us will do the
+	     name lookup. */
+	  state->_offset += fieldB, state->_ea_present = 0;
+      	  CHECK_FIELD_A();
+      	  CHECK_FLAG();
+	  break;
+
+	case 2:
+
+          /* fieldB may ba a limm value
+	   * fieldC is a shimm (signed 12-bit immediate)
+	   * fieldA can be 0
+           */
+
+	  fieldCisReg = 0;
+          fieldC = FIELDS(state->words[0]);
+          CHECK_FIELD_B();
+          /* Say ea is not present, so only one of us will do the
+	     name lookup. */
+	  state->_offset += fieldB, state->_ea_present = 0;
+	  if (is_limm)
+	    fieldAisReg = fieldA = 0;
+	  else
+	    fieldA = fieldB;
+      	  CHECK_FLAG();
+	  break;
+
+	case 3:
+
+          /* fieldB may ba a limm value
+	   * fieldC may be a limm or a shimm (unsigned 6-bit immediate)
+	   * fieldA can be 0
+	   * Conditional instructions
+           */
+
+          CHECK_FIELD_B();
+	  /* fieldC is a shimm (unsigned 6-bit immediate) */
+	  if (is_limm)
+	  {
+	    fieldAisReg = fieldA = 0;
+            FIELD_C();
+            if (BIT(state->words[0],5))
+	      fieldCisReg = 0;
+	    else if (fieldC == 62)
+	    {
+              fieldCisReg = 0;
+	      fieldC = fieldB;
+	    }
+	  }
+	  else
+	  {
+	    fieldA = fieldB;
+            if (BIT(state->words[0],5))
+	    {
+              FIELD_C();
+              fieldCisReg = 0;
+	    }
+	    else
+	    {
+              CHECK_FIELD_C();
+	    }
+	  }
+      	  CHECK_FLAG_COND();
+	  break;
+      }
+
+      write_instr_name();
+      WRITE_FORMAT_x(A);
+      WRITE_FORMAT_COMMA_x(B);
+      WRITE_FORMAT_COMMA_x(C);
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+      write_comments();
+      break;
+
+    case 1:
+
+      /* For ARCtangent 32-bit instructions with 2 operands */
+
+      /* field C is either a register or limm (different!) */
+      CHECK_FIELD_C();
+      FIELD_B();
+      CHECK_FLAG();
+
+      if (BITS(state->words[0],22,23) == 1 )
+	fieldCisReg = 0;
+      if (fieldCisReg) state->ea_reg1 = fieldC;
+      /* field C is either a shimm (same as fieldC) or limm (different!) */
+      /* Say ea is not present, so only one of us will do the name lookup. */
+      else state->_offset += fieldB, state->_ea_present = 0;
+
+      write_instr_name();
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(C);
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+      write_comments();
+      break;
+
+    case 2:
+
+      /* For BTST, CMP, MUL64, MULU64 instruction */
+
+      /* field C is either a register or limm (different!) */
+      subopcode =  BITS(state->words[0],22,23);
+      if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0],5))))
+      {
+      	CHECK_FIELD_C();
+	if (is_limm)
+	{
+	  FIELD_B();
+	  if (!fieldBisReg)
+	    fieldB = fieldC;
+	}
+	else
+	{
+      	  CHECK_FIELD_B();
+	}
+      }
+      else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0],5))))
+      {
+	FIELD_C();
+	fieldCisReg = 0;
+      	CHECK_FIELD_B();
+      }
+      else if (subopcode == 2)
+      {
+	FIELD_B();
+	fieldC = FIELDS(state->words[0]);
+	fieldCisReg = 0;
+      }
+      if (subopcode == 3)
+	CHECK_COND();
+
+      if (fieldCisReg) state->ea_reg1 = fieldC;
+      /* field C is either a shimm (same as fieldC) or limm (different!) */
+      /* Say ea is not present, so only one of us will do the name lookup. */
+      else state->_offset += fieldB, state->_ea_present = 0;
+
+      write_instr_name();
+      if (mul)
+      {
+	/* For Multiply instructions, the first operand is 0 */
+	WRITE_FORMAT_x(A);
+	WRITE_FORMAT_COMMA_x(B);
+        WRITE_FORMAT_COMMA_x(C);
+        WRITE_NOP_COMMENT();
+        my_sprintf(state, state->operandBuffer, formatString, 0, fieldB, fieldC);
+      }
+      else
+      {
+	WRITE_FORMAT_x(B);
+        WRITE_FORMAT_COMMA_x(C);
+        WRITE_NOP_COMMENT();
+        my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+      }
+      write_comments();
+      break;
+
+    case 3:
+      /*
+       * For FLAG instruction
+       */
+      subopcode =  BITS(state->words[0],22,23);
+
+      if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0],5))))
+      {
+        CHECK_FIELD_C();
+      }
+      else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0],5))))
+      {
+        FIELD_C();
+	fieldCisReg = 0;
+      }
+      else if (subopcode == 2)
+      {
+	fieldC = FIELDS(state->words[0]);
+	fieldCisReg = 0;
+      }
+      if (subopcode == 3)
+        CHECK_COND();
+      flag = 0;  /* this is the FLAG instruction -- it's redundant */
+
+      write_instr_name();
+      WRITE_FORMAT_x(C);
+      my_sprintf(state, state->operandBuffer, formatString, fieldC);
+      write_comments();
+      break;
+
+    case 4:
+      /*
+       * For op_JC -- jump to address specified.
+       *     Also covers jump and link--bit 9 of the instr. word
+       *     selects whether linked, thus "is_linked" is set above.
+       */
+      subopcode =  BITS(state->words[0],22,23);
+      if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0],5))))
+      {
+        CHECK_FIELD_C();
+	/* ilink registers */
+	if (fieldC == 29 || fieldC == 31)
+      	  CHECK_FLAG();
+      }
+      else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0],5))))
+      {
+        FIELD_C();
+	fieldCisReg = 0;
+      }
+      else if (subopcode == 2)
+      {
+	fieldC = FIELDS(state->words[0]);
+	fieldCisReg = 0;
+      }
+
+      if (subopcode == 3)
+        CHECK_COND();
+
+      state->nullifyMode = BITS(state->words[0],16,16);
+
+      if (!fieldCisReg)
+	{
+	  state->flow = is_linked ? direct_call : direct_jump;
+	  add_target(fieldC);
+	}
+      else
+	{
+	  state->flow = is_linked ? indirect_call : indirect_jump;
+	  /*
+	   * We should also treat this as indirect call if NOT linked
+	   * but the preceding instruction was a "lr blink,[status]"
+	   * and we have a delay slot with "add blink,blink,2".
+	   * For now we can't detect such.
+	   */
+	  state->register_for_indirect_jump = fieldC;
+	}
+
+      write_instr_name();
+      strcat(formatString,
+	     IS_REG(C)?"[%r]":"%s"); /* address/label name */
+
+      if (IS_REG(C))
+	my_sprintf(state, state->operandBuffer, formatString, fieldC);
+      else
+	my_sprintf(state, state->operandBuffer, formatString,
+		   post_address(state, fieldC));
+      write_comments();
+      break;
+
+    case 5:
+      /* LD instruction.  B and C can be regs, or one or both can be limm. */
+
+      CHECK_FIELD_A();
+      CHECK_FIELD_B();
+
+      if(FIELDA(state->words[0]) == 62)
+	{
+	  instrName = "prefetch";
+	}
+
+
+
+      if (is_limm)
+      {
+        FIELD_C();
+        if (!fieldCisReg)
+          fieldC = fieldB;
+      }
+      else
+      {
+        CHECK_FIELD_C();
+      }
+      if (dbg) printf("5:b reg %d %d c reg %d %d  \n",
+		      fieldBisReg,fieldB,fieldCisReg,fieldC);
+      state->_offset = 0;
+      state->_ea_present = 1;
+      if (fieldBisReg) state->ea_reg1 = fieldB; else state->_offset += fieldB;
+      if (fieldCisReg) state->ea_reg2 = fieldC; else state->_offset += fieldC;
+      state->_mem_load = 1;
+
+      directMem     = BIT(state->words[0],15);
+      /* Check if address writeback is allowed before decoding the
+	 address writeback field of a load instruction.*/
+      if (fieldBisReg && (fieldB != 62))
+        addrWriteBack = BITS(state->words[0],22,23);
+      signExtend    = BIT(state->words[0],16);
+
+      write_instr_name();
+
+      /* Check for prefetch or ld 0,...*/
+      if(IS_REG(A))
+	WRITE_FORMAT_x_COMMA_LB(A);
+      else
+	{
+	  strcat(formatString,"%*");
+	  WRITE_FORMAT_LB();
+	}
+
+
+      if (fieldBisReg || fieldB != 0)
+	WRITE_FORMAT_x(B);
+      else
+	fieldB = fieldC;
+
+      WRITE_FORMAT_COMMA_x_RB(C);
+      my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+      write_comments();
+      break;
+
+    case 6:
+      /* LD instruction. */
+      CHECK_FIELD_B();
+      CHECK_FIELD_A();
+      /* Support for Prefetch */
+      /* Fixme :: Check for A700 within this function */
+
+      if(FIELDA(state->words[0]) == 62)
+	{
+	  instrName = "prefetch";
+	}
+
+      fieldC = FIELDD9(state->words[0]);
+      fieldCisReg = 0;
+
+      if (dbg) printf_unfiltered("6:b reg %d %d c 0x%x  \n",
+				 fieldBisReg,fieldB,fieldC);
+      state->_ea_present = 1;
+      state->_offset = fieldC;
+      state->_mem_load = 1;
+      if (fieldBisReg) state->ea_reg1 = fieldB;
+      /* field B is either a shimm (same as fieldC) or limm (different!) */
+      /* Say ea is not present, so only one of us will do the name lookup. */
+      else state->_offset += fieldB, state->_ea_present = 0;
+
+      directMem     = BIT(state->words[0],11);
+      /* Check if address writeback is allowed before decoding the
+	 address writeback field of a load instruction.*/
+      if (fieldBisReg && (fieldB != 62))
+        addrWriteBack = BITS(state->words[0],9,10);
+      signExtend    = BIT(state->words[0],6);
+
+      write_instr_name();
+      if(IS_REG(A))
+	WRITE_FORMAT_x_COMMA_LB(A);
+      else
+	{
+	  strcat(formatString,"%*");
+	  WRITE_FORMAT_LB();
+	}
+      if (!fieldBisReg)
+	{
+	  fieldB = state->_offset;
+	  WRITE_FORMAT_x_RB(B);
+	}
+      else
+	{
+	  WRITE_FORMAT_x(B);
+	  WRITE_FORMAT_COMMA_x_RB(C);
+	}
+      my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+      write_comments();
+      break;
+
+    case 7:
+      /* ST instruction. */
+      CHECK_FIELD_B ();
+      CHECK_FIELD_C ();
+      state->source_operand.registerNum = fieldC;
+      state->sourceType = fieldCisReg ? ARC_REGISTER : ARC_LIMM;
+      fieldA  = FIELDD9 (state->words[0]); /* shimm */
+      fieldAisReg = 0;
+
+      /* [B,A offset] */
+      if (dbg) printf_unfiltered("7:b reg %d %x off %x\n",
+				 fieldBisReg,fieldB,fieldA);
+      state->_ea_present = 1;
+      state->_offset = fieldA;
+      if (fieldBisReg) state->ea_reg1 = fieldB;
+      /*
+       * field B is either a shimm (same as fieldA) or limm (different!)
+       * Say ea is not present, so only one of us will do the name lookup.
+       * (for is_limm we do the name translation here).
+       */
+      else
+	state->_offset += fieldB, state->_ea_present = 0;
+
+      directMem     = BIT (state->words[0], 5);
+      addrWriteBack = BITS (state->words[0], 3, 4);
+      state->_addrWriteBack = addrWriteBack;
+      write_instr_name ();
+      WRITE_FORMAT_x_COMMA_LB (C);
+      if (fieldA == 0)
+      {
+        WRITE_FORMAT_x_RB(B);
+      }
+      else
+      {
+	WRITE_FORMAT_x(B);
+        fieldAisReg = 0;
+        WRITE_FORMAT_COMMA_x_RB(A);
+      }
+      my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
+      write_comments2(fieldA);
+      break;
+
+    case 8:
+      /* SR instruction */
+      CHECK_FIELD_B();
+      switch (BITS(state->words[0],22,23))
+      {
+ 	case 0:
+          if (is_limm)
+          {
+       	    FIELD_C();
+      	    if (!fieldCisReg)
+	      fieldC = fieldB;
+      	  }
+      	  else
+	  {
+	    CHECK_FIELD_C();
+	  }
+	  break;
+	case 1:
+	  FIELD_C();
+	  fieldCisReg = 0;
+	  break;
+	case 2:
+	  fieldC = FIELDS(state->words[0]);
+	  fieldCisReg = 0;
+	  break;
+      }
+
+      write_instr_name();
+      WRITE_FORMAT_x_COMMA_LB(B);
+      /* Try to print B as an aux reg if it is not a core reg. */
+      usesAuxReg = 1;
+      WRITE_FORMAT_x(C);
+      WRITE_FORMAT_RB();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+      write_comments();
+      break;
+
+    case 9:
+      /* BBIT0/BBIT1 Instruction */
+
+      CHECK_FIELD_C();
+      if (is_limm || BIT(state->words[0],4))
+      {
+	fieldCisReg = 0;
+        FIELD_B();
+      }
+      else
+      {
+        CHECK_FIELD_B();
+      }
+      fieldAisReg = fieldA = 0;
+      fieldA = FIELDS9(state->words[0]);
+      fieldA += (addr & ~0x3);
+      CHECK_NULLIFY();
+
+      write_instr_name();
+
+      add_target(fieldA);
+      state->flow = state->_opcode == op_BLC ? direct_call : direct_jump;
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(C);
+      strcat(formatString, ",%s"); /* address/label name */
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC, post_address(state, fieldA));
+      write_comments();
+      break;
+
+    case 10:
+      /* LR instruction */
+      CHECK_FIELD_B();
+      switch (BITS(state->words[0],22,23))
+      {
+ 	case 0:
+	  CHECK_FIELD_C(); break;
+	case 1:
+	  FIELD_C();
+	  fieldCisReg = 0;
+	  break;
+	case 2:
+	  fieldC = FIELDS(state->words[0]);
+	  fieldCisReg = 0;
+	  break;
+      }
+
+      write_instr_name();
+      WRITE_FORMAT_x_COMMA_LB(B);
+      /* Try to print B as an aux reg if it is not a core reg. */
+      usesAuxReg = 1;
+      WRITE_FORMAT_x(C);
+      WRITE_FORMAT_RB();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+      write_comments();
+      break;
+
+    case 11:
+      /* lp instruction */
+
+      if (BITS(state->words[0],22,23) == 3)
+      {
+        FIELD_C();
+        CHECK_COND();
+      }
+      else
+      {
+	fieldC = FIELDS(state->words[0]);
+      }
+
+      fieldC = fieldC << 1;
+      fieldC += (addr & ~0x3);
+
+      write_instr_name();
+
+      /* This address could be a label we know.  Convert it. */
+      add_target(fieldC);
+      state->flow = state->_opcode == op_BLC ? direct_call : direct_jump;
+
+      fieldCisReg = 0;
+      strcat(formatString, "%s"); /* address/label name */
+      my_sprintf(state, state->operandBuffer, formatString, post_address(state, fieldC));
+      write_comments();
+      break;
+
+    case 12:
+      /* MOV instruction */
+      FIELD_B();
+      subopcode = BITS(state->words[0],22,23);
+      if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0],5))))
+      {
+      	CHECK_FIELD_C();
+      }
+      else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0],5))))
+      {
+      	FIELD_C();
+	fieldCisReg = 0;
+      }
+      else if (subopcode == 2)
+      {
+	fieldC = FIELDS(state->words[0]);
+	fieldCisReg = 0;
+      }
+      if (subopcode == 3)
+      {
+        CHECK_FLAG_COND();
+      }
+      else
+      {
+        CHECK_FLAG();
+      }
+
+     write_instr_name();
+     WRITE_FORMAT_x(B);
+     WRITE_FORMAT_COMMA_x(C);
+     WRITE_NOP_COMMENT();
+     my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+     break;
+
+    case 13:
+    /* "B", "BL" instruction */
+
+      fieldA = 0;
+      if ((state->_opcode == op_BC  && (BIT(state->words[0],16))) ||
+ 	  (state->_opcode == op_BLC && (BIT(state->words[0],17))))
+      {
+	/* unconditional branch s25 or branch and link d25 */
+        fieldA = (BITS(state->words[0],0,4)) << 10;
+      }
+      fieldA |= BITS(state->words[0],6,15);
+
+      if (state->_opcode == op_BLC)
+      {
+	  /* Fix for Bug #553.  A bl unconditional has only 9 bits in the
+	   * least order bits. */
+	fieldA = fieldA << 9;
+        fieldA |= BITS(state->words[0],18,26);
+	fieldA = fieldA << 2;
+      }
+      else
+      {
+	fieldA = fieldA << 10;
+        fieldA |= BITS(state->words[0],17,26);
+	fieldA = fieldA << 1;
+      }
+
+      if ((state->_opcode == op_BC  && (BIT(state->words[0],16))) ||
+ 	  (state->_opcode == op_BLC && (BIT(state->words[0],17))))
+	/* unconditional branch s25 or branch and link d25 */
+        fieldA = sign_extend(fieldA, 25);
+      else
+	/* conditional branch s21 or branch and link d21 */
+        fieldA = sign_extend(fieldA, 21);
+
+      fieldA += (addr & ~0x3);
+
+      if (BIT(state->words[0],16) && state->_opcode == op_BC)
+        CHECK_NULLIFY();
+      else
+	/* Checking for bl unconditionally FIX For Bug #553 */
+	if((state->_opcode == op_BLC && BITS(state->words[0],16,17) == 2 )
+	   ||(state->_opcode == op_BC && (BIT(state->words[0],16))))
+	    CHECK_NULLIFY();
+	  else
+	    CHECK_COND_NULLIFY();
+
+
+
+      write_instr_name();
+      /* This address could be a label we know.  Convert it. */
+      add_target(fieldA); /* For debugger. */
+      state->flow = state->_opcode == op_BLC /* BL */
+          ? direct_call
+          : direct_jump;
+        /* indirect calls are achieved by "lr blink,[status]; */
+        /*      lr dest<- func addr; j [dest]" */
+
+      strcat(formatString, "%s"); /* address/label name */
+      my_sprintf(state, state->operandBuffer, formatString, post_address(state, fieldA));
+      write_comments();
+      break;
+
+    case 14:
+
+      /* Extension Instructions */
+
+      FIELD_C_AC();
+      FIELD_B_AC();
+
+      write_instr_name();
+      if (mul)
+      {
+        fieldA = fieldAisReg = 0;
+	WRITE_FORMAT_x(A);
+        WRITE_FORMAT_COMMA_x(B);
+      }
+      else
+        WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(C);
+      WRITE_NOP_COMMENT();
+      if (mul)
+        my_sprintf(state, state->operandBuffer, formatString, 0, fieldB, fieldC);
+      else
+        my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+      break;
+
+    case 15:
+
+      /* ARCompact 16-bit Load/Add resister-register */
+
+      FIELD_C_AC();
+      FIELD_B_AC();
+      FIELD_A_AC();
+
+      write_instr_name();
+
+      if (BITS(state->words[0],3,4) != 3)
+      {
+        WRITE_FORMAT_x_COMMA_LB(A);
+	WRITE_FORMAT_x(B);
+	WRITE_FORMAT_COMMA_x_RB(C);
+      }
+      else
+      {
+        WRITE_FORMAT_x(A);
+        WRITE_FORMAT_COMMA_x(B);
+        WRITE_FORMAT_COMMA_x(C);
+      }
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+      break;
+
+    case 16:
+
+    /* ARCompact 16-bit Add/Sub/Shift instructions */
+
+      FIELD_C_AC();
+      FIELD_B_AC();
+      fieldA = FIELDA_AC(state->words[0]);
+      fieldAisReg = 0;
+
+      write_instr_name();
+      WRITE_FORMAT_x(C);
+      WRITE_FORMAT_COMMA_x(B);
+      WRITE_FORMAT_COMMA_x(A);
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
+      break;
+
+    case 17:
+
+      /* add_s instruction, one Dest/Source can be any of r0 - r63 */
+
+      CHECK_FIELD_H_AC();
+      FIELD_B_AC();
+
+      write_instr_name();
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(B);
+      WRITE_FORMAT_COMMA_x(C);
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC);
+      break;
+
+    case 18:
+
+      /* mov_s/cmp_s instruction, one Dest/Source can be any of r0 - r63 */
+
+      if ((BITS(state->words[0],3,4) == 1) || (BITS(state->words[0],3,4) == 2))
+      {
+      	CHECK_FIELD_H_AC();
+      }
+      else if (BITS(state->words[0],3,4) == 3)
+      {
+	FIELD_H_AC();
+      }
+      FIELD_B_AC();
+
+      write_instr_name();
+      if (BITS(state->words[0],3,4) == 3)
+      {
+        WRITE_FORMAT_x(C);
+        WRITE_FORMAT_COMMA_x(B);
+        WRITE_NOP_COMMENT();
+        my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB);
+      }
+      else
+      {
+        WRITE_FORMAT_x(B);
+        WRITE_FORMAT_COMMA_x(C);
+        WRITE_NOP_COMMENT();
+        my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+      }
+      break;
+
+    case 19:
+
+      /* Stack pointer-based instructions [major opcode 0x18] */
+
+      if (BITS(state->words[0],5,7) == 5)
+        fieldA = 28;
+      else
+      {
+        FIELD_B_AC();
+	fieldA = fieldB;
+      }
+      fieldB = 28; /* Field B is the stack pointer register */
+      fieldC = (FIELDU_AC(state->words[0])) << 2;
+      fieldCisReg = 0;
+
+      write_instr_name();
+
+      switch (BITS(state->words[0],5,7))
+      {
+	case 0:
+	case 1:
+	case 2:
+	case 3:
+          WRITE_FORMAT_x_COMMA_LB(A);
+	  WRITE_FORMAT_x(B);
+	  WRITE_FORMAT_COMMA_x_RB(C);
+	  break;
+	case 4:
+	case 5:
+          WRITE_FORMAT_x(A);
+          WRITE_FORMAT_COMMA_x(B);
+          WRITE_FORMAT_COMMA_x(C);
+	  break;
+      }
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+      break;
+
+    case 20:
+
+      /* gp-relative instructions [major opcode 0x19] */
+
+      fieldA = 0;
+      fieldB = 26; /* Field B is the gp register */
+      fieldC = FIELDS_AC(state->words[0]);
+      switch (BITS(state->words[0],9,10))
+      {
+	case 0:
+	case 3:
+	  fieldC = fieldC << 2; break;
+	case 2:
+	  fieldC = fieldC << 1; break;
+      }
+      fieldCisReg = 0;
+
+      write_instr_name();
+
+      if (BITS(state->words[0],9,10) != 3)
+      {
+        WRITE_FORMAT_x_COMMA_LB(A);
+	WRITE_FORMAT_x(B);
+	WRITE_FORMAT_COMMA_x_RB(C);
+      }
+      else
+      {
+        WRITE_FORMAT_x(A);
+        WRITE_FORMAT_COMMA_x(B);
+        WRITE_FORMAT_COMMA_x(C);
+      }
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+      break;
+
+    case 21:
+
+      /* add/cmp/btst instructions [major opcode 28] */
+
+      FIELD_B_AC();
+      if (state->_opcode == op_Su5)
+        fieldC = (BITS(state->words[0],0,4));
+      else
+        fieldC = (BITS(state->words[0],0,6));
+      fieldCisReg = 0;
+      write_instr_name();
+
+      if (!BIT(state->words[0],7))
+      {
+        WRITE_FORMAT_x(B);
+        WRITE_FORMAT_COMMA_x(B);
+        WRITE_FORMAT_COMMA_x(C);
+        WRITE_NOP_COMMENT();
+        my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC);
+      }
+      else
+      {
+        WRITE_FORMAT_x(B);
+        WRITE_FORMAT_COMMA_x(C);
+        WRITE_NOP_COMMENT();
+        my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+      }
+      break;
+
+    case 22:
+
+      /* ARCompact 16-bit instructions, General ops/ single ops */
+
+      FIELD_C_AC();
+      FIELD_B_AC();
+
+      write_instr_name();
+
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(B);
+      WRITE_FORMAT_COMMA_x(C);
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC);
+      break;
+
+    case 23:
+
+      /* Shift/subtract/bit immediate instructions [major opcode 23] */
+
+      FIELD_B_AC();
+      fieldC = FIELDU_AC(state->words[0]);
+      fieldCisReg = 0;
+      write_instr_name();
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(B);
+      WRITE_FORMAT_COMMA_x(C);
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC);
+      break;
+
+    case 24:
+
+      /* ARCompact 16-bit Branch conditionally */
+
+      if (state->_opcode == op_BL_S)
+      {
+        fieldA = (BITS(state->words[0],0,10)) << 2;
+	fieldA = sign_extend(fieldA, 13);
+      }
+      else if (BITS(state->words[0],9,10) != 3)
+      {
+        fieldA = (BITS(state->words[0],0,8)) << 1;
+	fieldA = sign_extend(fieldA, 10);
+      }
+      else
+      {
+        fieldA = (BITS(state->words[0],0,5)) << 1;
+	fieldA = sign_extend(fieldA, 7);
+      }
+      fieldA += (addr & ~0x3);
+
+      write_instr_name();
+      /* This address could be a label we know.  Convert it. */
+      add_target(fieldA); /* For debugger. */
+      state->flow = state->_opcode == op_BL_S /* BL */
+          ? direct_call
+          : direct_jump;
+        /* indirect calls are achieved by "lr blink,[status]; */
+        /*      lr dest<- func addr; j [dest]" */
+
+      strcat(formatString, "%s"); /* address/label name */
+      my_sprintf(state, state->operandBuffer, formatString, post_address(state, fieldA));
+      write_comments();
+      break;
+
+    case 25:
+
+      /* ARCompact 16-bit Branch conditionally on reg z/nz */
+
+      FIELD_B_AC();
+      fieldC = (BITS(state->words[0],0,6)) << 1;
+      fieldC = sign_extend (fieldC, 8);
+
+      fieldC += (addr & ~0x3);
+      fieldA = fieldAisReg = fieldCisReg = 0;
+
+      write_instr_name();
+      /* This address could be a label we know.  Convert it. */
+      add_target(fieldC); /* For debugger. */
+
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(A);
+      strcat(formatString, ",%s"); /* address/label name */
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldA, post_address(state, fieldC));
+      write_comments();
+      break;
+
+    case 26:
+
+      /* Zero operand Instructions */
+
+      write_instr_name();
+      state->operandBuffer[0] = '\0';
+      break;
+
+    case 27:
+
+      /* j_s instruction */
+
+      FIELD_B_AC ();
+      state->register_for_indirect_jump = fieldB;
+      write_instr_name ();
+      strcat (formatString,"[%r]");
+      my_sprintf (state, state->operandBuffer, formatString, fieldB);
+      break;
+
+    case 28:
+
+      /* Load/Store with offset */
+
+      FIELD_C_AC();
+      FIELD_B_AC();
+      switch (state->_opcode)
+      {
+	case op_LD_S :
+	case op_ST_S :
+      	  fieldA = (FIELDU_AC(state->words[0])) << 2;
+	  break;
+	case op_LDB_S :
+	case op_STB_S :
+      	  fieldA = (FIELDU_AC(state->words[0]));
+	  break;
+	case op_LDW_S :
+	case op_LDWX_S :
+	case op_STW_S :
+      	  fieldA = (FIELDU_AC(state->words[0])) << 1;
+	  break;
+      }
+      fieldAisReg = 0;
+
+      write_instr_name();
+
+      WRITE_FORMAT_x_COMMA_LB(C);
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(A);
+      WRITE_FORMAT_RB();
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
+      write_comments();
+      break;
+
+    case 29:
+
+      /* Load pc-relative */
+
+      FIELD_B_AC();
+      fieldC = 63;
+      fieldA = (BITS(state->words[0],0,7)) << 2;
+      fieldAisReg = 0;
+
+      write_instr_name();
+
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(C);
+      WRITE_FORMAT_COMMA_x(A);
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC, fieldA);
+      write_comments();
+      break;
+
+    case 30:
+
+      /* mov immediate */
+
+      FIELD_B_AC();
+      fieldC = (BITS(state->words[0],0,7));
+      fieldCisReg = 0;
+
+      write_instr_name();
+
+      WRITE_FORMAT_x(B);
+      WRITE_FORMAT_COMMA_x(C);
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+      write_comments();
+      break;
+
+    case 31:
+
+      /* push/pop instructions */
+
+      if (BITS(state->words[0],0,4) == 1)
+      {
+        FIELD_B_AC();
+      }
+      else if (BITS(state->words[0],0,4) == 17)
+	fieldB = 31;
+
+      write_instr_name();
+
+      WRITE_FORMAT_x(B);
+      WRITE_NOP_COMMENT();
+      my_sprintf(state, state->operandBuffer, formatString, fieldB);
+      break;
+
+    case 32:
+
+      /* Single operand instruction */
+
+      if (!BITS(state->words[0],22,23))
+      {
+        CHECK_FIELD_C();
+      }
+      else
+      {
+	FIELD_C();
+	fieldCisReg = 0;
+      }
+
+      write_instr_name();
+
+      if (!fieldC)
+        state->operandBuffer[0] = '\0';
+      else
+      {
+        WRITE_FORMAT_x(C);
+        WRITE_NOP_COMMENT();
+        my_sprintf(state, state->operandBuffer, formatString, fieldC);
+      }
+      break;
+
+  case 33:
+    /* For trap_s and the class of instructions that have
+       unsigned 6 bits in the fields B and C in A700 16 bit
+       instructions */
+    fieldC = FIELDC_AC(state->words[0]);
+    fieldB = FIELDB_AC(state->words[0]);
+    fieldCisReg = 0;
+    fieldBisReg = 0;
+    write_instr_name();
+    strcat(formatString,"%d");
+    my_sprintf(state,state->operandBuffer,formatString, ((fieldB << 3) | fieldC));
+    break;
+
+  case 34:
+    /* For ex.di and its class of instructions within op_major_4
+       This class is different from the normal set of instructions
+       in op_major_4 because this uses bit 15 as .di and the second
+       operand is actually a memory operand.
+       This is of the class
+       <op>.<di> b,[c] and <op>.<di> b,[limm]
+    */
+
+
+    /* field C is either a register or limm (different!) */
+
+    CHECK_FIELD_C();
+    FIELD_B();
+    directMem = BIT(state->words[0],15);
+
+
+    if (BITS(state->words[0],22,23) == 1 )
+      fieldCisReg = 0;
+    if (fieldCisReg)
+      state->ea_reg1 = fieldC;
+
+    write_instr_name();
+    WRITE_FORMAT_x_COMMA_LB(B);
+
+    WRITE_FORMAT_x_RB(C);
+
+    WRITE_NOP_COMMENT();
+    my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+    write_comments();
+    break;
+
+  case 35:
+
+    /* sub_s.ne instruction */
+
+    FIELD_B_AC();
+    write_instr_name();
+    strcat(formatString,"%r,%r,%r");
+    my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldB);
+    break;
+
+  case 36:
+
+    FIELD_B_AC();
+
+    write_instr_name();
+
+    WRITE_FORMAT_x(B);
+    WRITE_NOP_COMMENT();
+    my_sprintf(state, state->operandBuffer, formatString, fieldB);
+
+    break;
+    /*******SIMD instructions decoding follows*************/
+  case 37:
+  case 39:
+  case 41:
+    /*fieldA is vr register
+      fieldB is I register
+      fieldC is a constant
+      %*,[%(,%<]
+      or
+      %*,%(,%<
+      or
+      %*,%(,%u
+    */
+
+    CHECK_FIELD_A();
+
+    CHECK_FIELD_B();
+    if (decodingClass == 41)
+       {
+	 FIELD_C();
+       }
+    else
+      {
+	FIELD_U8();
+
+	if (simd_scale_u8>0)
+	  fieldC = fieldC << simd_scale_u8;
+      }
+
+    fieldCisReg = 0;
+
+    write_instr_name();
+    (decodingClass == 37 ? WRITE_FORMAT_x_COMMA_LB(A) :
+                           WRITE_FORMAT_x_COMMA(A));
+    WRITE_FORMAT_x_COMMA(B);
+    (decodingClass == 37 ?  WRITE_FORMAT_x_RB(C):
+                            WRITE_FORMAT_x(C));
+    WRITE_NOP_COMMENT();
+    my_sprintf(state,state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+
+
+    break;
+  case 38:
+    /* fieldA is a vr register
+       fieldB is a ARC700 basecase register.
+       %*,[%b]
+    */
+    CHECK_FIELD_A();
+    CHECK_FIELD_B();
+
+    write_instr_name();
+    WRITE_FORMAT_x_COMMA_LB(A);
+    WRITE_FORMAT_x_RB(B);
+    WRITE_NOP_COMMENT();
+    my_sprintf(state,state->operandBuffer, formatString, fieldA, fieldB);
+
+    break;
+  case 40:
+    /* fieldB & fieldC are vr registers
+       %(,%)
+       or
+       %B,%C
+       or
+       %(,%C
+    */
+    CHECK_FIELD_B();
+    CHECK_FIELD_C();
+
+    write_instr_name();
+    WRITE_FORMAT_x(B);
+    WRITE_FORMAT_COMMA_x(C);
+    my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
+    break;
+
+  case 42:
+    /* fieldA, fieldB, fieldC are all vr registers
+       %*, %(, %) */
+    CHECK_FIELD_A();
+    CHECK_FIELD_B();
+    FIELD_C();
+
+    write_instr_name();
+    WRITE_FORMAT_x(A);
+    WRITE_FORMAT_COMMA_x(B);
+    WRITE_FORMAT_COMMA_x(C);
+    my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
+    break;
+
+  case 43:
+    /* Only fieldC is a register
+     %C*/
+    CHECK_FIELD_C();
+
+    if (BITS(state->words[0], 17, 23) == 55)
+      fieldCisReg = 0;
+
+    write_instr_name();
+    WRITE_FORMAT_x(C);
+    my_sprintf(state, state->operandBuffer, formatString, fieldC);
+    break;
+
+    /***************SIMD decoding ends*********************/
+  default:
+    mwerror(state, "Bad decoding class in ARC disassembler");
+    break;
+  }
+
+  state->_cond = cond;
+  return state->instructionLen = offset;
+}
+
+
+/*
+ * _coreRegName - Returns the name the user specified core extension
+ *                register.
+ */
+static const char *
+_coreRegName
+(
+ void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */
+ int v                         /* Register value */
+ )
+{
+  return arcExtMap_coreRegName(v);
+}
+
+/*
+ * _auxRegName - Returns the name the user specified AUX extension
+ *               register.
+ */
+static const char *
+_auxRegName
+( void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */
+  int v                         /* Register value */
+  )
+{
+  return arcExtMap_auxRegName(v);
+}
+
+
+/*
+ * _condCodeName - Returns the name the user specified condition code
+ *                 name.
+ */
+static const char *
+_condCodeName
+(
+ void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */
+ int v                         /* Register value */
+ )
+{
+  return arcExtMap_condCodeName(v);
+}
+
+
+/*
+ * _instName - Returns the name the user specified extension instruction.
+ */
+static const char *
+_instName
+(
+ void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */
+ int op1,                      /* major opcode value */
+ int op2,                      /* minor opcode value */
+ int *flags                    /* instruction flags */
+ )
+{
+  return arcExtMap_instName(op1, op2, flags);
+}
+
+static void
+parse_disassembler_options (char *options)
+{
+  if (!strncasecmp (options, "simd",4))
+    {
+      enable_simd = 1;
+    }
+}
+
+/*
+ * This function is the same as decodeInstr except that this function
+ * returns a struct arcDisState instead of the instruction length.
+ *
+ * This struct contains information useful to the debugger.
+ */
+struct arcDisState
+arcAnalyzeInstr
+(
+ bfd_vma address,		/* Address of this instruction */
+ disassemble_info* info
+ )
+{
+  int status;
+  bfd_byte buffer[4];
+  struct arcDisState s;	/* ARC Disassembler state */
+  int lowbyte, highbyte;
+
+  lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
+  highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
+
+  memset (&s, 0, sizeof (struct arcDisState));
+
+  /* read first instruction */
+  status = (*info->read_memory_func) (address, buffer, 2, info);
+
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, address, info);
+      s.instructionLen = -1;
+      return s;
+    }
+
+  if ((buffer[lowbyte] & 0xf8) > 0x38)
+    {
+      info->bytes_per_line = 2;
+      s.words[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
+      status = (*info->read_memory_func) (address + 2, buffer, 4, info);
+      if (info->endian == BFD_ENDIAN_LITTLE)
+	s.words[1] = bfd_getl32 (buffer);
+      else
+	s.words[1] = bfd_getb32 (buffer);
+    }
+  else
+    {
+      info->bytes_per_line = 4;
+      status = (*info->read_memory_func) (address + 2, &buffer[2], 2, info);
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, address + 2, info);
+	  s.instructionLen = -1;
+	  return s;
+	}
+      if (info->endian == BFD_ENDIAN_LITTLE)
+	s.words[0] = bfd_getl32(buffer);
+      else
+	s.words[0] = bfd_getb32(buffer);
+
+      /* Always read second word in case of limm.  */
+      /* We ignore the result since the last insn may not have a limm.  */
+      status = (*info->read_memory_func) (address + 4, buffer, 4, info);
+      if (info->endian == BFD_ENDIAN_LITTLE)
+	s.words[1] = bfd_getl32(buffer);
+      else
+	s.words[1] = bfd_getb32(buffer);
+    }
+
+  s._this = &s;
+  s.coreRegName = _coreRegName;
+  s.auxRegName = _auxRegName;
+  s.condCodeName = _condCodeName;
+  s.instName = _instName;
+
+  /* disassemble */
+  dsmOneArcInst (address, (void *)&s, info);
+
+  return s;
+}
+
+/* ARCompact_decodeInstr - Decode an ARCompact instruction returning the
+   size of the instruction in bytes or zero if unrecognized.  */
+int
+ARCompact_decodeInstr (address, info)
+     bfd_vma address; /* Address of this instruction.  */
+     disassemble_info* info;
+{
+  void *stream = info->stream; /* output stream */
+  fprintf_ftype func = info->fprintf_func;
+  char buf[256];
+
+  if (info->disassembler_options)
+    {
+      parse_disassembler_options (info->disassembler_options);
+
+      /* To avoid repeated parsing of these options, we remove them here.  */
+      info->disassembler_options = NULL;
+    }
+
+  s = arcAnalyzeInstr (address, info);
+
+  if (!s.this)
+    return -1;
+
+  /* display the disassembly instruction */
+
+  if (s.instructionLen == 2)
+    (*func) (stream, "        ");
+
+  (*func) (stream, "%08x ", s.words[0]);
+  (*func) (stream, "    ");
+
+  (*func) (stream, "%-10s ", s.instrBuffer);
+
+  if (__TRANSLATION_REQUIRED(s))
+    {
+      bfd_vma addr;
+      char *tmpBuffer;
+      int i = 1;
+      if (s.operandBuffer[0] != '@')
+	{
+	  /* Branch instruction with 3 operands, Translation is required
+	     only for the third operand. Print the first 2 operands */
+	  strcpy (buf, s.operandBuffer);
+	  tmpBuffer = strtok (buf,"@");
+	  (*func) (stream, "%s",tmpBuffer);
+	  i = strlen (tmpBuffer)+1;
+	}
+      addr = s.addresses[s.operandBuffer[i] - '0'];
+      (*info->print_address_func) ((bfd_vma) addr, info);
+      (*func) (stream, "\n");
+    }
+  else
+    (*func) (stream, "%s",s.operandBuffer);
+  return s.instructionLen;
+
+}
diff --git a/sim/common/ChangeLog.ARC b/sim/common/ChangeLog.ARC
new file mode 100644
index 0000000..2b73a9f
--- /dev/null
+++ b/sim/common/ChangeLog.ARC
@@ -0,0 +1,42 @@
+2007-09-17  J"orn Rennecke  <joern.rennecke@arc.com>
+
+	* gentvals.sh: Allow target-specific definitions to override
+	later generic ones.
+	* gennltvals.sh: Use ${srcroot}/newlib/libc/sys/arc/sys/fcntl.h
+	for open on arc.
+	* nltvals.def: Regenerate.
+
+2007-08-22  J"orn Rennecke  <joern.rennecke@arc.com>
+
+	* cgen-trace.c (sim_cgen_disassemble_insn):
+	Check for CGEN_INSN_DISASM_BITSIZE.
+
+2007-08-21  J"orn Rennecke  <joern.rennecke@arc.com>
+
+	* cgen-trace.c (sim_cgen_disassemble_insn): Disable bogus sanity check.
+
+2007-05-14  J"orn Rennecke  <joern.rennecke@arc.com>
+
+	* callback.c (fdmap, fdbad): No longer static.
+
+2007-05-02  J"orn Rennecke  <joern.rennecke@arc.com>
+
+	* syscall.c (get_path): No longer static.
+
+2007-04-30  J"orn Rennecke  <joern.rennecke@arc.com>
+
+	* gennltvals.sh: Add arc code.
+	* nltvals.def: Regenerate.
+
+	Speed up simulator startup:
+	* sim-utils.c (zalloc): Use xcalloc.
+
+	Debugging utility functions:
+	* sim-utils.c (dump_hex, dump_strn_1, dump_asc): New functions.
+	* (dump_str, dump_strn): Likewise.
+
+	Fix descriptor 0/1/2 handling in pesence of freopen:
+	* syscall.c (cb_syscall): Add comments about descriptors 0/1/2.
+	* callback.c (os_read_stdin): Use os_read.
+	(os_write): Use fwrite to stdout / stderr for descriptor 1 / 2.
+	(os_write_stdout, os_write_stderr): Use os_write.