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fuchsia / third_party / bcmdhd / b435c30d80f701bfad942b5ee8a311d6f3963dba / . / dhd_pcie.c
blob: 69c78b4f9e77f9210028f07512e2a5b3cb7a9673 [file] [log] [blame]
/*
* DHD Bus Module for PCIE
*
* Copyright 1999-2016, Broadcom Corporation
* All rights reserved,
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* This software is provided by the copyright holder "as is" and any express or
* implied warranties, including, but not limited to, the implied warranties of
* merchantability and fitness for a particular purpose are disclaimed. In no event
* shall copyright holder be liable for any direct, indirect, incidental, special,
* exemplary, or consequential damages (including, but not limited to, procurement
* of substitute goods or services; loss of use, data, or profits; or business
* interruption) however caused and on any theory of liability, whether in
* contract, strict liability, or tort (including negligence or otherwise) arising
* in any way out of the use of this software, even if advised of the possibility
* of such damage
*
*
* <<Broadcom-WL-IPTag/Open:>>
*
* $Id: dhd_pcie.c 609007 2015-12-30 07:44:52Z $
*/
/* include files */
#include <typedefs.h>
#include <bcmutils.h>
#include <bcmdevs.h>
#include <siutils.h>
#include <hndsoc.h>
#include <hndpmu.h>
#include <sbchipc.h>
#include <hnd_armtrap.h>
#if defined(DHD_DEBUG)
#include <hnd_cons.h>
#endif /* defined(DHD_DEBUG) */
#include <dngl_stats.h>
#include <pcie_core.h>
#include <dhd.h>
#include <dhd_bus.h>
#include <dhd_flowring.h>
#include <dhd_proto.h>
#include <dhd_dbg.h>
#include <dhdioctl.h>
#include <sdiovar.h>
#include <bcmmsgbuf.h>
#include <pcicfg.h>
#include <dhd_pcie.h>
#include <bcmpcie.h>
#include <bcmendian.h>
#ifdef DHDTCPACK_SUPPRESS
#include <dhd_ip.h>
#endif /* DHDTCPACK_SUPPRESS */
#include <dhd_config.h>
#ifdef BCMEMBEDIMAGE
#include BCMEMBEDIMAGE
#endif /* BCMEMBEDIMAGE */
#ifdef PCIE_OOB
#include "ftdi_sio_external.h"
#endif /* PCIE_OOB */
#define MEMBLOCK 2048 /* Block size used for downloading of dongle image */
#define MAX_WKLK_IDLE_CHECK 3 /* times wake_lock checked before deciding not to suspend */
#define ARMCR4REG_BANKIDX (0x40/sizeof(uint32))
#define ARMCR4REG_BANKPDA (0x4C/sizeof(uint32))
/* Temporary war to fix precommit till sync issue between trunk & precommit branch is resolved */
#if defined(SUPPORT_MULTIPLE_BOARD_REV)
extern unsigned int system_rev;
#endif /* SUPPORT_MULTIPLE_BOARD_REV */
int dhd_dongle_memsize;
int dhd_dongle_ramsize;
static int dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size);
#ifdef DHD_DEBUG
static int dhdpcie_bus_readconsole(dhd_bus_t *bus);
#endif /* DHD_DEBUG */
#if defined(DHD_FW_COREDUMP)
static int dhdpcie_mem_dump(dhd_bus_t *bus);
#endif /* DHD_FW_COREDUMP */
static int dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size);
static int dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
const char *name, void *params,
int plen, void *arg, int len, int val_size);
static int dhdpcie_bus_lpback_req(struct dhd_bus *bus, uint32 intval);
static int dhdpcie_bus_dmaxfer_req(struct dhd_bus *bus,
uint32 len, uint32 srcdelay, uint32 destdelay);
static int dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter);
static int _dhdpcie_download_firmware(struct dhd_bus *bus);
static int dhdpcie_download_firmware(dhd_bus_t *bus, osl_t *osh);
static int dhdpcie_bus_write_vars(dhd_bus_t *bus);
static bool dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus);
static bool dhdpci_bus_read_frames(dhd_bus_t *bus);
static int dhdpcie_readshared(dhd_bus_t *bus);
static void dhdpcie_init_shared_addr(dhd_bus_t *bus);
static bool dhdpcie_dongle_attach(dhd_bus_t *bus);
static void dhdpcie_bus_dongle_setmemsize(dhd_bus_t *bus, int mem_size);
static void dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh,
bool dongle_isolation, bool reset_flag);
static void dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh);
static int dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len);
static uint8 dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset);
static void dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data);
static void dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data);
static uint16 dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset);
static void dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data);
static uint32 dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset);
static void dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data);
static uint64 dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset);
static void dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data);
#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
static void dhdpcie_bus_cfg_set_bar1_win(dhd_bus_t *bus, uint32 data);
static ulong dhd_bus_cmn_check_offset(dhd_bus_t *bus, ulong offset);
#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */
static void dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size);
static int dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b);
static void dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data);
static void dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info);
extern void dhd_dpc_kill(dhd_pub_t *dhdp);
#ifdef BCMEMBEDIMAGE
static int dhdpcie_download_code_array(dhd_bus_t *bus);
#endif /* BCMEMBEDIMAGE */
#ifdef EXYNOS_PCIE_DEBUG
extern void exynos_pcie_register_dump(int ch_num);
#endif /* EXYNOS_PCIE_DEBUG */
#define PCI_VENDOR_ID_BROADCOM 0x14e4
static void dhd_bus_set_device_wake(struct dhd_bus *bus, bool val);
extern void wl_nddbg_wpp_log(const char *format, ...);
#ifdef PCIE_OOB
static void dhd_bus_doorbell_timeout_reset(struct dhd_bus *bus);
#define DHD_DEFAULT_DOORBELL_TIMEOUT 200 /* ms */
static uint dhd_doorbell_timeout = DHD_DEFAULT_DOORBELL_TIMEOUT;
#define HOST_WAKE 4 /* GPIO_0 (HOST_WAKE) - Output from WLAN */
#define DEVICE_WAKE 5 /* GPIO_1 (DEVICE_WAKE) - Input to WLAN */
#define BIT_WL_REG_ON 6
#define BIT_BT_REG_ON 7
int gpio_handle_val = 0;
unsigned char gpio_port = 0;
unsigned char gpio_direction = 0;
#define OOB_PORT "ttyUSB0"
#endif /* PCIE_OOB */
static bool dhdpcie_check_firmware_compatible(uint32 f_api_version, uint32 h_api_version);
/* IOVar table */
enum {
IOV_INTR = 1,
IOV_MEMBYTES,
IOV_MEMSIZE,
IOV_SET_DOWNLOAD_STATE,
IOV_DEVRESET,
IOV_VARS,
IOV_MSI_SIM,
IOV_PCIE_LPBK,
IOV_CC_NVMSHADOW,
IOV_RAMSIZE,
IOV_RAMSTART,
IOV_SLEEP_ALLOWED,
IOV_PCIE_DMAXFER,
IOV_PCIE_SUSPEND,
IOV_PCIEREG,
IOV_PCIECFGREG,
IOV_PCIECOREREG,
IOV_PCIESERDESREG,
IOV_BAR0_SECWIN_REG,
IOV_SBREG,
IOV_DONGLEISOLATION,
IOV_LTRSLEEPON_UNLOOAD,
IOV_METADATA_DBG,
IOV_RX_METADATALEN,
IOV_TX_METADATALEN,
IOV_TXP_THRESHOLD,
IOV_BUZZZ_DUMP,
IOV_DUMP_RINGUPD_BLOCK,
IOV_DMA_RINGINDICES,
IOV_DB1_FOR_MB,
IOV_FLOW_PRIO_MAP,
#ifdef DHD_PCIE_RUNTIMEPM
IOV_IDLETIME,
#endif /* DHD_PCIE_RUNTIMEPM */
IOV_RXBOUND,
IOV_TXBOUND,
IOV_HANGREPORT,
#ifdef PCIE_OOB
IOV_OOB_BT_REG_ON,
IOV_OOB_ENABLE
#endif /* PCIE_OOB */
};
const bcm_iovar_t dhdpcie_iovars[] = {
{"intr", IOV_INTR, 0, IOVT_BOOL, 0 },
{"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int) },
{"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0 },
{"dwnldstate", IOV_SET_DOWNLOAD_STATE, 0, IOVT_BOOL, 0 },
{"vars", IOV_VARS, 0, IOVT_BUFFER, 0 },
{"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0 },
{"pcie_lpbk", IOV_PCIE_LPBK, 0, IOVT_UINT32, 0 },
{"cc_nvmshadow", IOV_CC_NVMSHADOW, 0, IOVT_BUFFER, 0 },
{"ramsize", IOV_RAMSIZE, 0, IOVT_UINT32, 0 },
{"ramstart", IOV_RAMSTART, 0, IOVT_UINT32, 0 },
{"pciereg", IOV_PCIEREG, 0, IOVT_BUFFER, 2 * sizeof(int32) },
{"pciecfgreg", IOV_PCIECFGREG, 0, IOVT_BUFFER, 2 * sizeof(int32) },
{"pciecorereg", IOV_PCIECOREREG, 0, IOVT_BUFFER, 2 * sizeof(int32) },
{"pcieserdesreg", IOV_PCIESERDESREG, 0, IOVT_BUFFER, 3 * sizeof(int32) },
{"bar0secwinreg", IOV_BAR0_SECWIN_REG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
{"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
{"pcie_dmaxfer", IOV_PCIE_DMAXFER, 0, IOVT_BUFFER, 3 * sizeof(int32) },
{"pcie_suspend", IOV_PCIE_SUSPEND, 0, IOVT_UINT32, 0 },
#ifdef PCIE_OOB
{"oob_bt_reg_on", IOV_OOB_BT_REG_ON, 0, IOVT_UINT32, 0 },
{"oob_enable", IOV_OOB_ENABLE, 0, IOVT_UINT32, 0 },
#endif /* PCIE_OOB */
{"sleep_allowed", IOV_SLEEP_ALLOWED, 0, IOVT_BOOL, 0 },
{"dngl_isolation", IOV_DONGLEISOLATION, 0, IOVT_UINT32, 0 },
{"ltrsleep_on_unload", IOV_LTRSLEEPON_UNLOOAD, 0, IOVT_UINT32, 0 },
{"dump_ringupdblk", IOV_DUMP_RINGUPD_BLOCK, 0, IOVT_BUFFER, 0 },
{"dma_ring_indices", IOV_DMA_RINGINDICES, 0, IOVT_UINT32, 0},
{"metadata_dbg", IOV_METADATA_DBG, 0, IOVT_BOOL, 0 },
{"rx_metadata_len", IOV_RX_METADATALEN, 0, IOVT_UINT32, 0 },
{"tx_metadata_len", IOV_TX_METADATALEN, 0, IOVT_UINT32, 0 },
{"db1_for_mb", IOV_DB1_FOR_MB, 0, IOVT_UINT32, 0 },
{"txp_thresh", IOV_TXP_THRESHOLD, 0, IOVT_UINT32, 0 },
{"buzzz_dump", IOV_BUZZZ_DUMP, 0, IOVT_UINT32, 0 },
{"flow_prio_map", IOV_FLOW_PRIO_MAP, 0, IOVT_UINT32, 0 },
#ifdef DHD_PCIE_RUNTIMEPM
{"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0 },
#endif /* DHD_PCIE_RUNTIMEPM */
{"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0 },
{"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0 },
{"fw_hang_report", IOV_HANGREPORT, 0, IOVT_BOOL, 0 },
{NULL, 0, 0, 0, 0 }
};
#define MAX_READ_TIMEOUT 5 * 1000 * 1000
#ifndef DHD_RXBOUND
#define DHD_RXBOUND 64
#endif
#ifndef DHD_TXBOUND
#define DHD_TXBOUND 64
#endif
uint dhd_rxbound = DHD_RXBOUND;
uint dhd_txbound = DHD_TXBOUND;
/* Register/Unregister functions are called by the main DHD entry
* point (e.g. module insertion) to link with the bus driver, in
* order to look for or await the device.
*/
int
dhd_bus_register(void)
{
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
return dhdpcie_bus_register();
}
void
dhd_bus_unregister(void)
{
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
dhdpcie_bus_unregister();
return;
}
/** returns a host virtual address */
uint32 *
dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size)
{
return (uint32 *)REG_MAP(addr, size);
}
void
dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size)
{
REG_UNMAP((void*)(uintptr)addr);
return;
}
/**
* 'regs' is the host virtual address that maps to the start of the PCIe BAR0 window. The first 4096
* bytes in this window are mapped to the backplane address in the PCIEBAR0Window register. The
* precondition is that the PCIEBAR0Window register 'points' at the PCIe core.
*
* 'tcm' is the *host* virtual address at which tcm is mapped.
*/
#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
dhd_bus_t* dhdpcie_bus_attach(osl_t *osh,
volatile char *regs, volatile char *tcm, uint32 tcm_size, void *pci_dev)
#else
dhd_bus_t* dhdpcie_bus_attach(osl_t *osh,
volatile char *regs, volatile char *tcm, void *pci_dev)
#endif /* DHD_PCIE_BAR1_WIN_BASE_FIX */
{
dhd_bus_t *bus;
DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
do {
if (!(bus = MALLOCZ(osh, sizeof(dhd_bus_t)))) {
DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__));
break;
}
bus->regs = regs;
bus->tcm = tcm;
#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
bus->tcm_size = tcm_size;
#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */
bus->osh = osh;
/* Save pci_dev into dhd_bus, as it may be needed in dhd_attach */
bus->dev = (struct pci_dev *)pci_dev;
dll_init(&bus->const_flowring);
/* Attach pcie shared structure */
if (!(bus->pcie_sh = MALLOCZ(osh, sizeof(pciedev_shared_t)))) {
DHD_ERROR(("%s: MALLOC of bus->pcie_sh failed\n", __FUNCTION__));
break;
}
/* dhd_common_init(osh); */
if (dhdpcie_dongle_attach(bus)) {
DHD_ERROR(("%s: dhdpcie_probe_attach failed\n", __FUNCTION__));
break;
}
/* software resources */
if (!(bus->dhd = dhd_attach(osh, bus, PCMSGBUF_HDRLEN))) {
DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__));
break;
}
bus->dhd->busstate = DHD_BUS_DOWN;
bus->db1_for_mb = TRUE;
bus->dhd->hang_report = TRUE;
bus->irq_registered = FALSE;
bus->d3_ack_war_cnt = 0;
DHD_TRACE(("%s: EXIT SUCCESS\n",
__FUNCTION__));
return bus;
} while (0);
DHD_TRACE(("%s: EXIT FAILURE\n", __FUNCTION__));
if (bus && bus->pcie_sh) {
MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t));
}
if (bus) {
MFREE(osh, bus, sizeof(dhd_bus_t));
}
return NULL;
}
uint
dhd_bus_chip(struct dhd_bus *bus)
{
ASSERT(bus->sih != NULL);
return bus->sih->chip;
}
uint
dhd_bus_chiprev(struct dhd_bus *bus)
{
ASSERT(bus);
ASSERT(bus->sih != NULL);
return bus->sih->chiprev;
}
void *
dhd_bus_pub(struct dhd_bus *bus)
{
return bus->dhd;
}
void *
dhd_bus_sih(struct dhd_bus *bus)
{
return (void *)bus->sih;
}
void *
dhd_bus_txq(struct dhd_bus *bus)
{
return &bus->txq;
}
/** Get Chip ID version */
uint dhd_bus_chip_id(dhd_pub_t *dhdp)
{
dhd_bus_t *bus = dhdp->bus;
return bus->sih->chip;
}
/** Get Chip Rev ID version */
uint dhd_bus_chiprev_id(dhd_pub_t *dhdp)
{
dhd_bus_t *bus = dhdp->bus;
return bus->sih->chiprev;
}
/** Get Chip Pkg ID version */
uint dhd_bus_chippkg_id(dhd_pub_t *dhdp)
{
dhd_bus_t *bus = dhdp->bus;
return bus->sih->chippkg;
}
/** Read and clear intstatus. This should be called with interupts disabled or inside isr */
uint32
dhdpcie_bus_intstatus(dhd_bus_t *bus)
{
uint32 intstatus = 0;
uint32 intmask = 0;
if ((bus->sih->buscorerev == 6) || (bus->sih->buscorerev == 4) ||
(bus->sih->buscorerev == 2)) {
intstatus = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4);
dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, intstatus);
intstatus &= I_MB;
} else {
/* this is a PCIE core register..not a config register... */
intstatus = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, 0, 0);
/* this is a PCIE core register..not a config register... */
intmask = si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask, 0, 0);
/*
* The fourth argument to si_corereg is the "mask" fields of the register to update
* and the fifth field is the "value" to update. Now if we are interested in only
* few fields of the "mask" bit map, we should not be writing back what we read
* By doing so, we might clear/ack interrupts that are not handled yet.
*/
si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxInt, bus->def_intmask,
intstatus);
intstatus &= intmask;
/* Is device removed. intstatus & intmask read 0xffffffff */
if (intstatus == (uint32)-1) {
DHD_ERROR(("%s: !!!!!!Device Removed or dead chip.\n", __FUNCTION__));
intstatus = 0;
#ifdef CUSTOMER_HW4_DEBUG
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
bus->dhd->hang_reason = HANG_REASON_PCIE_LINK_DOWN;
dhd_os_send_hang_message(bus->dhd);
#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27) && OEM_ANDROID */
#endif /* CUSTOMER_HW4_DEBUG */
}
intstatus &= bus->def_intmask;
}
return intstatus;
}
/**
* Name: dhdpcie_bus_isr
* Parameters:
* 1: IN int irq -- interrupt vector
* 2: IN void *arg -- handle to private data structure
* Return value:
* Status (TRUE or FALSE)
*
* Description:
* Interrupt Service routine checks for the status register,
* disable interrupt and queue DPC if mail box interrupts are raised.
*/
int32
dhdpcie_bus_isr(dhd_bus_t *bus)
{
uint32 intstatus = 0;
do {
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
/* verify argument */
if (!bus) {
DHD_ERROR(("%s : bus is null pointer, exit \n", __FUNCTION__));
break;
}
if (bus->dhd->dongle_reset) {
break;
}
if (bus->dhd->busstate == DHD_BUS_DOWN) {
DHD_ERROR(("%s: BUS is down, not processing the interrupt \r\n",
__FUNCTION__));
break;
}
intstatus = dhdpcie_bus_intstatus(bus);
/* Check if the interrupt is ours or not */
if (intstatus == 0) {
break;
}
/* save the intstatus */
bus->intstatus = intstatus;
/* Overall operation:
* - Mask further interrupts
* - Read/ack intstatus
* - Take action based on bits and state
* - Reenable interrupts (as per state)
*/
/* Count the interrupt call */
bus->intrcount++;
/* read interrupt status register!! Status bits will be cleared in DPC !! */
bus->ipend = TRUE;
dhdpcie_bus_intr_disable(bus); /* Disable interrupt!! */
bus->intdis = TRUE;
#if defined(PCIE_ISR_THREAD)
DHD_TRACE(("Calling dhd_bus_dpc() from %s\n", __FUNCTION__));
DHD_OS_WAKE_LOCK(bus->dhd);
while (dhd_bus_dpc(bus));
DHD_OS_WAKE_UNLOCK(bus->dhd);
#else
bus->dpc_sched = TRUE;
dhd_sched_dpc(bus->dhd); /* queue DPC now!! */
#endif /* defined(SDIO_ISR_THREAD) */
DHD_TRACE(("%s: Exit Success DPC Queued\n", __FUNCTION__));
return TRUE;
} while (0);
DHD_TRACE(("%s: Exit Failure\n", __FUNCTION__));
return FALSE;
}
#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
dhd_pub_t *link_recovery = NULL;
#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
static bool
dhdpcie_dongle_attach(dhd_bus_t *bus)
{
osl_t *osh = bus->osh;
void *regsva = (void*)bus->regs;
uint16 devid = bus->cl_devid;
uint32 val;
sbpcieregs_t *sbpcieregs;
DHD_TRACE(("%s: ENTER\n", __FUNCTION__));
#ifdef EXYNOS_PCIE_LINKDOWN_RECOVERY
link_recovery = bus->dhd;
#endif /* EXYNOS_PCIE_LINKDOWN_RECOVERY */
bus->alp_only = TRUE;
bus->sih = NULL;
/* Set bar0 window to si_enum_base */
dhdpcie_bus_cfg_set_bar0_win(bus, SI_ENUM_BASE);
#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
/* Read bar1 window */
bus->bar1_win_base = OSL_PCI_READ_CONFIG(bus->osh, PCI_BAR1_WIN, 4);
DHD_ERROR(("%s: PCI_BAR1_WIN = %x\n", __FUNCTION__, bus->bar1_win_base));
#else
/* Checking PCIe bus status with reading configuration space */
val = OSL_PCI_READ_CONFIG(osh, PCI_CFG_VID, sizeof(uint32));
if ((val & 0xFFFF) != VENDOR_BROADCOM) {
DHD_ERROR(("%s : failed to read PCI configuration space!\n", __FUNCTION__));
goto fail;
}
#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */
/* si_attach() will provide an SI handle and scan the backplane */
if (!(bus->sih = si_attach((uint)devid, osh, regsva, PCI_BUS, bus,
&bus->vars, &bus->varsz))) {
DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__));
goto fail;
}
si_setcore(bus->sih, PCIE2_CORE_ID, 0);
sbpcieregs = (sbpcieregs_t*)(bus->regs);
/* WAR where the BAR1 window may not be sized properly */
W_REG(osh, &sbpcieregs->configaddr, 0x4e0);
val = R_REG(osh, &sbpcieregs->configdata);
#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
/* Fix to 2M */
val = 22; /* 1M: 21, 2M: 22, 4M: 23 */
bus->bar1_win_mask = 0xffffffff - (bus->tcm_size - 1);
DHD_ERROR(("%s: BAR1 window val=%d, base=%d mask=%x, tcm=%x(%x)\n", __FUNCTION__, val,
bus->bar1_win_base, bus->bar1_win_mask,
bus->tcm_size, DHD_PCIE_BAR1_WIN_BASE_FIX));
#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */
W_REG(osh, &sbpcieregs->configdata, val);
/* Get info on the ARM and SOCRAM cores... */
/* Should really be qualified by device id */
if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
(si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) ||
(si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) ||
(si_setcore(bus->sih, ARMCA7_CORE_ID, 0))) {
bus->armrev = si_corerev(bus->sih);
} else {
DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__));
goto fail;
}
if (si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) {
if (!(bus->orig_ramsize = si_sysmem_size(bus->sih))) {
DHD_ERROR(("%s: failed to find SYSMEM memory!\n", __FUNCTION__));
goto fail;
}
/* also populate base address */
bus->dongle_ram_base = CA7_4365_RAM_BASE;
} else if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) {
if (!(bus->orig_ramsize = si_socram_size(bus->sih))) {
DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__));
goto fail;
}
} else {
/* cr4 has a different way to find the RAM size from TCM's */
if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) {
DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__));
goto fail;
}
/* also populate base address */
switch ((uint16)bus->sih->chip) {
case BCM4339_CHIP_ID:
case BCM4335_CHIP_ID:
bus->dongle_ram_base = CR4_4335_RAM_BASE;
break;
case BCM4358_CHIP_ID:
case BCM4356_CHIP_ID:
case BCM4354_CHIP_ID:
case BCM43567_CHIP_ID:
case BCM43569_CHIP_ID:
case BCM4350_CHIP_ID:
case BCM43570_CHIP_ID:
bus->dongle_ram_base = CR4_4350_RAM_BASE;
break;
case BCM4360_CHIP_ID:
bus->dongle_ram_base = CR4_4360_RAM_BASE;
break;
CASE_BCM4345_CHIP:
bus->dongle_ram_base = (bus->sih->chiprev < 6) /* changed at 4345C0 */
? CR4_4345_LT_C0_RAM_BASE : CR4_4345_GE_C0_RAM_BASE;
break;
CASE_BCM43602_CHIP:
bus->dongle_ram_base = CR4_43602_RAM_BASE;
break;
case BCM4349_CHIP_GRPID:
/* RAM base changed from 4349c0(revid=9) onwards */
bus->dongle_ram_base = ((bus->sih->chiprev < 9) ?
CR4_4349_RAM_BASE : CR4_4349_RAM_BASE_FROM_REV_9);
break;
default:
bus->dongle_ram_base = 0;
DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n",
__FUNCTION__, bus->dongle_ram_base));
}
}
bus->ramsize = bus->orig_ramsize;
if (dhd_dongle_memsize)
dhdpcie_bus_dongle_setmemsize(bus, dhd_dongle_memsize);
DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n",
bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base));
bus->srmemsize = si_socram_srmem_size(bus->sih);
bus->def_intmask = PCIE_MB_D2H_MB_MASK | PCIE_MB_TOPCIE_FN0_0 | PCIE_MB_TOPCIE_FN0_1;
/* Set the poll and/or interrupt flags */
bus->intr = (bool)dhd_intr;
bus->wait_for_d3_ack = 1;
bus->suspended = FALSE;
#ifdef PCIE_OOB
gpio_handle_val = get_handle(OOB_PORT);
if (gpio_handle_val < 0)
{
DHD_ERROR(("%s: Could not get GPIO handle.\n", __FUNCTION__));
ASSERT(FALSE);
}
gpio_direction = 0;
ftdi_set_bitmode(gpio_handle_val, 0, BITMODE_BITBANG);
/* Note BT core is also enabled here */
gpio_port = 1 << BIT_WL_REG_ON | 1 << BIT_BT_REG_ON | 1 << DEVICE_WAKE;
gpio_write_port(gpio_handle_val, gpio_port);
gpio_direction = 1 << BIT_WL_REG_ON | 1 << BIT_BT_REG_ON | 1 << DEVICE_WAKE;
ftdi_set_bitmode(gpio_handle_val, gpio_direction, BITMODE_BITBANG);
bus->oob_enabled = TRUE;
/* drive the Device_Wake GPIO low on startup */
bus->device_wake_state = TRUE;
dhd_bus_set_device_wake(bus, FALSE);
dhd_bus_doorbell_timeout_reset(bus);
#endif /* PCIE_OOB */
DHD_TRACE(("%s: EXIT: SUCCESS\n", __FUNCTION__));
return 0;
fail:
if (bus->sih != NULL) {
si_detach(bus->sih);
bus->sih = NULL;
}
DHD_TRACE(("%s: EXIT: FAILURE\n", __FUNCTION__));
return -1;
}
int
dhpcie_bus_unmask_interrupt(dhd_bus_t *bus)
{
dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, I_MB);
return 0;
}
int
dhpcie_bus_mask_interrupt(dhd_bus_t *bus)
{
dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, 0x0);
return 0;
}
void
dhdpcie_bus_intr_enable(dhd_bus_t *bus)
{
DHD_TRACE(("%s: enable interrupts\n", __FUNCTION__));
if (bus && bus->sih && !bus->is_linkdown) {
if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
(bus->sih->buscorerev == 4)) {
dhpcie_bus_unmask_interrupt(bus);
} else {
si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask,
bus->def_intmask, bus->def_intmask);
}
} else {
DHD_ERROR(("****** %s: failed ******\n", __FUNCTION__));
DHD_ERROR(("bus: %p sih: %p bus->is_linkdown %d\n",
bus, bus ? bus->sih : NULL, bus ? bus->is_linkdown: -1));
}
}
void
dhdpcie_bus_intr_disable(dhd_bus_t *bus)
{
DHD_TRACE(("%s Enter\n", __FUNCTION__));
if (bus && bus->sih && !bus->is_linkdown) {
if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) ||
(bus->sih->buscorerev == 4)) {
dhpcie_bus_mask_interrupt(bus);
} else {
si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask,
bus->def_intmask, 0);
}
} else {
DHD_ERROR(("****** %s: failed ******\n", __FUNCTION__));
DHD_ERROR(("bus: %p sih: %p bus->is_linkdown %d\n",
bus, bus ? bus->sih : NULL, bus ? bus->is_linkdown: -1));
}
DHD_TRACE(("%s Exit\n", __FUNCTION__));
}
/*
* dhdpcie_advertise_bus_cleanup advertises that clean up is under progress
* to other bus user contexts like Tx, Rx, IOVAR, WD etc and it waits for other contexts
* to gracefully exit. All the bus usage contexts before marking busstate as busy, will check for
* whether the busstate is DHD_BUS_DOWN or DHD_BUS_DOWN_IN_PROGRESS, if so
* they will exit from there itself without marking dhd_bus_busy_state as BUSY.
*/
static void
dhdpcie_advertise_bus_cleanup(dhd_pub_t *dhdp)
{
unsigned long flags;
int timeleft;
DHD_GENERAL_LOCK(dhdp, flags);
dhdp->busstate = DHD_BUS_DOWN_IN_PROGRESS;
DHD_GENERAL_UNLOCK(dhdp, flags);
timeleft = dhd_os_busbusy_wait_negation(dhdp, &dhdp->dhd_bus_busy_state);
if (timeleft == 0) {
DHD_ERROR(("%s : Timeout due to dhd_bus_busy_state=0x%x\n",
__FUNCTION__, dhdp->dhd_bus_busy_state));
BUG_ON(1);
}
return;
}
static void
dhdpcie_bus_remove_prep(dhd_bus_t *bus)
{
unsigned long flags;
DHD_TRACE(("%s Enter\n", __FUNCTION__));
DHD_GENERAL_LOCK(bus->dhd, flags);
bus->dhd->busstate = DHD_BUS_DOWN;
DHD_GENERAL_UNLOCK(bus->dhd, flags);
dhd_os_sdlock(bus->dhd);
dhdpcie_bus_intr_disable(bus);
// terence 20150406: fix for null pointer handle when doing remove driver
if (!bus->dhd->dongle_isolation && bus->sih) {
pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs));
}
dhd_os_sdunlock(bus->dhd);
DHD_TRACE(("%s Exit\n", __FUNCTION__));
}
/** Detach and free everything */
void
dhdpcie_bus_release(dhd_bus_t *bus)
{
bool dongle_isolation = FALSE;
osl_t *osh = NULL;
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
if (bus) {
osh = bus->osh;
ASSERT(osh);
if (bus->dhd) {
dhdpcie_advertise_bus_cleanup(bus->dhd);
dongle_isolation = bus->dhd->dongle_isolation;
dhdpcie_bus_remove_prep(bus);
if (bus->intr) {
dhdpcie_bus_intr_disable(bus);
dhdpcie_free_irq(bus);
}
dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE);
dhd_detach(bus->dhd);
dhd_free(bus->dhd);
bus->dhd = NULL;
}
/* unmap the regs and tcm here!! */
if (bus->regs) {
dhdpcie_bus_reg_unmap(osh, (ulong)bus->regs, DONGLE_REG_MAP_SIZE);
bus->regs = NULL;
}
if (bus->tcm) {
dhdpcie_bus_reg_unmap(osh, (ulong)bus->tcm, DONGLE_TCM_MAP_SIZE);
bus->tcm = NULL;
}
dhdpcie_bus_release_malloc(bus, osh);
/* Detach pcie shared structure */
if (bus->pcie_sh) {
MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t));
bus->pcie_sh = NULL;
}
#ifdef DHD_DEBUG
if (bus->console.buf != NULL)
MFREE(osh, bus->console.buf, bus->console.bufsize);
#endif
/* Finally free bus info */
MFREE(osh, bus, sizeof(dhd_bus_t));
}
DHD_TRACE(("%s: Exit\n", __FUNCTION__));
} /* dhdpcie_bus_release */
void
dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag)
{
DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__,
bus->dhd, bus->dhd->dongle_reset));
if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag) {
DHD_TRACE(("%s Exit\n", __FUNCTION__));
return;
}
if (bus->sih) {
if (!dongle_isolation)
pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs));
if (bus->ltrsleep_on_unload) {
si_corereg(bus->sih, bus->sih->buscoreidx,
OFFSETOF(sbpcieregs_t, u.pcie2.ltr_state), ~0, 0);
}
if (bus->sih->buscorerev == 13)
pcie_serdes_iddqdisable(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs));
if (bus->sih != NULL) {
si_detach(bus->sih);
bus->sih = NULL;
}
if (bus->vars && bus->varsz)
MFREE(osh, bus->vars, bus->varsz);
bus->vars = NULL;
}
DHD_TRACE(("%s Exit\n", __FUNCTION__));
}
uint32
dhdpcie_bus_cfg_read_dword(dhd_bus_t *bus, uint32 addr, uint32 size)
{
uint32 data = OSL_PCI_READ_CONFIG(bus->osh, addr, size);
return data;
}
/** 32 bit config write */
void
dhdpcie_bus_cfg_write_dword(dhd_bus_t *bus, uint32 addr, uint32 size, uint32 data)
{
OSL_PCI_WRITE_CONFIG(bus->osh, addr, size, data);
}
void
dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data)
{
OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR0_WIN, 4, data);
}
#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
static void
dhdpcie_bus_cfg_set_bar1_win(dhd_bus_t *bus, uint32 data)
{
OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR1_WIN, 4, data);
}
#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */
void
dhdpcie_bus_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
{
int32 min_size = DONGLE_MIN_MEMSIZE;
/* Restrict the memsize to user specified limit */
DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n",
dhd_dongle_memsize, min_size));
if ((dhd_dongle_memsize > min_size) &&
(dhd_dongle_memsize < (int32)bus->orig_ramsize))
bus->ramsize = dhd_dongle_memsize;
}
void
dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh)
{
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
if (bus->dhd && bus->dhd->dongle_reset)
return;
if (bus->vars && bus->varsz) {
MFREE(osh, bus->vars, bus->varsz);
bus->vars = NULL;
}
DHD_TRACE(("%s: Exit\n", __FUNCTION__));
return;
}
/** Stop bus module: clear pending frames, disable data flow */
void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
{
uint32 status;
unsigned long flags;
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
if (!bus->dhd)
return;
if (bus->dhd->busstate == DHD_BUS_DOWN) {
DHD_ERROR(("%s: already down by net_dev_reset\n", __FUNCTION__));
goto done;
}
DHD_DISABLE_RUNTIME_PM(bus->dhd);
DHD_GENERAL_LOCK(bus->dhd, flags);
bus->dhd->busstate = DHD_BUS_DOWN;
DHD_GENERAL_UNLOCK(bus->dhd, flags);
dhdpcie_bus_intr_disable(bus);
status = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4);
dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, status);
if (!dhd_download_fw_on_driverload) {
dhd_dpc_kill(bus->dhd);
}
/* Clear rx control and wake any waiters */
dhd_os_set_ioctl_resp_timeout(IOCTL_DISABLE_TIMEOUT);
dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_BUS_STOP);
done:
return;
}
/** Watchdog timer function */
bool dhd_bus_watchdog(dhd_pub_t *dhd)
{
unsigned long flags;
#ifdef DHD_DEBUG
dhd_bus_t *bus;
bus = dhd->bus;
DHD_GENERAL_LOCK(dhd, flags);
if (dhd->busstate == DHD_BUS_DOWN ||
dhd->busstate == DHD_BUS_DOWN_IN_PROGRESS) {
DHD_GENERAL_UNLOCK(dhd, flags);
return FALSE;
}
dhd->dhd_bus_busy_state |= DHD_BUS_BUSY_IN_WD;
DHD_GENERAL_UNLOCK(dhd, flags);
#ifdef DHD_PCIE_RUNTIMEPM
dhdpcie_runtime_bus_wake(dhd, TRUE, __builtin_return_address(0));
#endif /* DHD_PCIE_RUNTIMEPM */
/* Poll for console output periodically */
if (dhd->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
bus->console.count += dhd_watchdog_ms;
if (bus->console.count >= dhd_console_ms) {
bus->console.count -= dhd_console_ms;
/* Make sure backplane clock is on */
if (dhdpcie_bus_readconsole(bus) < 0)
dhd_console_ms = 0; /* On error, stop trying */
}
}
#endif /* DHD_DEBUG */
#ifdef PCIE_OOB
/* If haven't communicated with device for a while, deassert the Device_Wake GPIO */
if (dhd_doorbell_timeout != 0 && !(bus->dhd->busstate == DHD_BUS_SUSPEND) &&
dhd_timeout_expired(&bus->doorbell_timer)) {
dhd_bus_set_device_wake(bus, FALSE);
}
#endif /* PCIE_OOB */
DHD_GENERAL_LOCK(dhd, flags);
dhd->dhd_bus_busy_state &= ~DHD_BUS_BUSY_IN_WD;
DHD_GENERAL_UNLOCK(dhd, flags);
return TRUE;
} /* dhd_bus_watchdog */
#define DEADBEEF_PATTERN 0xADDEADDE // "DeadDead"
#define MEMCHECKINFO "/data/.memcheck.info"
static int
dhd_get_memcheck_info(void)
{
struct file *fp = NULL;
uint32 mem_val = 0;
int ret = 0;
char *filepath = MEMCHECKINFO;
fp = filp_open(filepath, O_RDONLY, 0);
if (IS_ERR(fp)) {
DHD_ERROR(("[WIFI_SEC] %s: File [%s] doesn't exist\n", __FUNCTION__, filepath));
goto done;
} else {
ret = kernel_read(fp, 0, (char *)&mem_val, 4);
if (ret < 0) {
DHD_ERROR(("[WIFI_SEC] %s: File read error, ret=%d\n", __FUNCTION__, ret));
filp_close(fp, NULL);
goto done;
}
mem_val = bcm_atoi((char *)&mem_val);
DHD_ERROR(("[WIFI_SEC]%s: MEMCHECK ENABLED = %d\n", __FUNCTION__, mem_val));
filp_close(fp, NULL);
}
done:
return mem_val;
}
static int
dhdpcie_mem_check(struct dhd_bus *bus)
{
int bcmerror = BCME_OK;
int offset = 0;
int len = 0;
uint8 *memblock = NULL, *memptr;
int size = bus->ramsize;
int i;
uint32 memcheck_enabled;
/* Read memcheck info from the file */
/* 0 : Disable */
/* 1 : "Dead Beef" pattern write */
/* 2 : "Dead Beef" pattern write and checking the pattern value */
memcheck_enabled = dhd_get_memcheck_info();
DHD_ERROR(("%s: memcheck_enabled: %d \n", __FUNCTION__, memcheck_enabled));
if (memcheck_enabled == 0) {
return bcmerror;
}
memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
if (memblock == NULL) {
DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
goto err;
}
if ((ulong)memblock % DHD_SDALIGN) {
memptr += (DHD_SDALIGN - ((ulong)memblock % DHD_SDALIGN));
}
for (i = 0; i < MEMBLOCK; i = i + 4) {
*(ulong*)(memptr + i) = DEADBEEF_PATTERN;
}
if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) ||
si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) {
if (offset == 0) {
/* Add start of RAM address to the address given by user */
offset += bus->dongle_ram_base;
}
}
/* Write "DeadBeef" pattern with MEMBLOCK size */
while (size) {
len = MIN(MEMBLOCK, size);
bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len);
if (bcmerror) {
DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
__FUNCTION__, bcmerror, MEMBLOCK, offset));
goto err;
}
if (memcheck_enabled == 2) {
bcmerror = dhdpcie_bus_membytes(bus, FALSE, offset, (uint8 *)memptr, len);
if (bcmerror) {
DHD_ERROR(("%s: error %d on read %d membytes at 0x%08x\n",
__FUNCTION__, bcmerror, MEMBLOCK, offset));
goto err;
} else {
for (i = 0; i < len; i = i+4) {
if ((*(uint32*)(memptr + i)) != DEADBEEF_PATTERN) {
DHD_ERROR(("%s: error on reading pattern at "
"0x%08x\n", __FUNCTION__, (offset + i)));
bcmerror = BCME_ERROR;
goto err;
}
}
}
}
offset += MEMBLOCK;
size -= MEMBLOCK;
}
DHD_ERROR(("%s: Writing the Dead Beef pattern is Done \n", __FUNCTION__));
err:
if (memblock) {
MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
}
return bcmerror;
}
/* Download firmware image and nvram image */
int
dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
char *pfw_path, char *pnv_path,
char *pclm_path, char *pconf_path)
{
int ret;
bus->fw_path = pfw_path;
bus->nv_path = pnv_path;
bus->dhd->clm_path = pclm_path;
bus->dhd->conf_path = pconf_path;
DHD_ERROR(("%s: firmware path=%s, nvram path=%s\n",
__FUNCTION__, bus->fw_path, bus->nv_path));
dhdpcie_mem_check(bus);
ret = dhdpcie_download_firmware(bus, osh);
return ret;
}
void
dhd_set_path_params(struct dhd_bus *bus)
{
/* External conf takes precedence if specified */
dhd_conf_preinit(bus->dhd);
if (bus->dhd->clm_path[0] == '\0') {
dhd_conf_set_path(bus->dhd, "clm.blob", bus->dhd->clm_path, bus->fw_path);
}
dhd_conf_set_clm_name_by_chip(bus->dhd, bus->dhd->clm_path);
if (bus->dhd->conf_path[0] == '\0') {
dhd_conf_set_path(bus->dhd, "config.txt", bus->dhd->conf_path, bus->nv_path);
}
#ifdef CONFIG_PATH_AUTO_SELECT
dhd_conf_set_conf_name_by_chip(bus->dhd, bus->dhd->conf_path);
#endif
dhd_conf_read_config(bus->dhd, bus->dhd->conf_path);
dhd_conf_set_fw_name_by_chip(bus->dhd, bus->fw_path);
dhd_conf_set_nv_name_by_chip(bus->dhd, bus->nv_path);
dhd_conf_set_clm_name_by_chip(bus->dhd, bus->dhd->clm_path);
printf("Final fw_path=%s\n", bus->fw_path);
printf("Final nv_path=%s\n", bus->nv_path);
printf("Final clm_path=%s\n", bus->dhd->clm_path);
printf("Final conf_path=%s\n", bus->dhd->conf_path);
}
static int
dhdpcie_download_firmware(struct dhd_bus *bus, osl_t *osh)
{
int ret = 0;
#if defined(BCM_REQUEST_FW)
uint chipid = bus->sih->chip;
uint revid = bus->sih->chiprev;
char fw_path[64] = "/lib/firmware/brcm/bcm"; /* path to firmware image */
char nv_path[64]; /* path to nvram vars file */
bus->fw_path = fw_path;
bus->nv_path = nv_path;
switch (chipid) {
case BCM43570_CHIP_ID:
bcmstrncat(fw_path, "43570", 5);
switch (revid) {
case 0:
bcmstrncat(fw_path, "a0", 2);
break;
case 2:
bcmstrncat(fw_path, "a2", 2);
break;
default:
DHD_ERROR(("%s: revid is not found %x\n", __FUNCTION__,
revid));
break;
}
break;
default:
DHD_ERROR(("%s: unsupported device %x\n", __FUNCTION__,
chipid));
return 0;
}
/* load board specific nvram file */
snprintf(bus->nv_path, sizeof(nv_path), "%s.nvm", fw_path);
/* load firmware */
snprintf(bus->fw_path, sizeof(fw_path), "%s-firmware.bin", fw_path);
#endif /* BCM_REQUEST_FW */
DHD_OS_WAKE_LOCK(bus->dhd);
dhd_set_path_params(bus);
ret = _dhdpcie_download_firmware(bus);
DHD_OS_WAKE_UNLOCK(bus->dhd);
return ret;
}
static int
dhdpcie_download_code_file(struct dhd_bus *bus, char *pfw_path)
{
int bcmerror = BCME_ERROR;
int offset = 0;
int len = 0;
char *imgbuf = NULL;
uint8 *memblock = NULL, *memptr;
uint8 *memptr_tmp = NULL; // terence: check downloaded firmware is correct
int offset_end = bus->ramsize;
DHD_ERROR(("%s: download firmware %s\n", __FUNCTION__, pfw_path));
/* Should succeed in opening image if it is actually given through registry
* entry or in module param.
*/
imgbuf = dhd_os_open_image(pfw_path);
if (imgbuf == NULL) {
printf("%s: Open firmware file failed %s\n", __FUNCTION__, pfw_path);
goto err;
}
memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
if (memblock == NULL) {
DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
goto err;
}
if (dhd_msg_level & DHD_TRACE_VAL) {
memptr_tmp = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
if (memptr_tmp == NULL) {
DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
goto err;
}
}
if ((uint32)(uintptr)memblock % DHD_SDALIGN)
memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
DHD_INFO_HW4(("%s: dongle_ram_base: 0x%x ramsize: 0x%x tcm: %p\n",
__FUNCTION__, bus->dongle_ram_base, bus->ramsize, bus->tcm));
/* Download image with MEMBLOCK size */
while ((len = dhd_os_get_image_block((char*)memptr, MEMBLOCK, imgbuf))) {
if (len < 0) {
DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len));
bcmerror = BCME_ERROR;
goto err;
}
/* check if CR4/CA7 */
if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) ||
si_setcore(bus->sih, ARMCA7_CORE_ID, 0)) {
/* if address is 0, store the reset instruction to be written in 0 */
if (offset == 0) {
bus->resetinstr = *(((uint32*)memptr));
/* Add start of RAM address to the address given by user */
offset += bus->dongle_ram_base;
offset_end += offset;
}
}
bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len);
if (bcmerror) {
DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
__FUNCTION__, bcmerror, MEMBLOCK, offset));
goto err;
}
if (dhd_msg_level & DHD_TRACE_VAL) {
bcmerror = dhdpcie_bus_membytes(bus, FALSE, offset, memptr_tmp, len);
if (bcmerror) {
DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
__FUNCTION__, bcmerror, MEMBLOCK, offset));
goto err;
}
if (memcmp(memptr_tmp, memptr, len)) {
DHD_ERROR(("%s: Downloaded image is corrupted.\n", __FUNCTION__));
goto err;
} else
DHD_INFO(("%s: Download, Upload and compare succeeded.\n", __FUNCTION__));
}
offset += MEMBLOCK;
if (offset >= offset_end) {
DHD_ERROR(("%s: invalid address access to %x (offset end: %x)\n",
__FUNCTION__, offset, offset_end));
bcmerror = BCME_ERROR;
goto err;
}
}
err:
if (memblock)
MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
if (dhd_msg_level & DHD_TRACE_VAL) {
if (memptr_tmp)
MFREE(bus->dhd->osh, memptr_tmp, MEMBLOCK + DHD_SDALIGN);
}
if (imgbuf)
dhd_os_close_image(imgbuf);
return bcmerror;
} /* dhdpcie_download_code_file */
#ifdef CUSTOMER_HW4_DEBUG
#define MIN_NVRAMVARS_SIZE 128
#endif /* CUSTOMER_HW4_DEBUG */
static int
dhdpcie_download_nvram(struct dhd_bus *bus)
{
int bcmerror = BCME_ERROR;
uint len;
char * memblock = NULL;
char *bufp;
char *pnv_path;
bool nvram_file_exists;
bool nvram_uefi_exists = FALSE;
bool local_alloc = FALSE;
pnv_path = bus->nv_path;
nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0'));
/* First try UEFI */
len = MAX_NVRAMBUF_SIZE;
dhd_get_download_buffer(bus->dhd, NULL, NVRAM, &memblock, &len);
/* If UEFI empty, then read from file system */
if ((len == 0) || (memblock[0] == '\0')) {
if (nvram_file_exists) {
len = MAX_NVRAMBUF_SIZE;
dhd_get_download_buffer(bus->dhd, pnv_path, NVRAM, &memblock, &len);
if ((len <= 0 || len > MAX_NVRAMBUF_SIZE)) {
goto err;
}
}
else {
/* For SROM OTP no external file or UEFI required */
bcmerror = BCME_OK;
}
} else {
nvram_uefi_exists = TRUE;
}
DHD_ERROR(("%s: dhd_get_download_buffer len %d\n", __FUNCTION__, len));
if (len > 0 && len <= MAX_NVRAMBUF_SIZE) {
bufp = (char *) memblock;
#ifdef CACHE_FW_IMAGES
if (bus->processed_nvram_params_len) {
len = bus->processed_nvram_params_len;
}
if (!bus->processed_nvram_params_len) {
bufp[len] = 0;
if (nvram_uefi_exists || nvram_file_exists) {
len = process_nvram_vars(bufp, len);
bus->processed_nvram_params_len = len;
}
} else
#else
{
bufp[len] = 0;
if (nvram_uefi_exists || nvram_file_exists) {
len = process_nvram_vars(bufp, len);
}
}
#endif /* CACHE_FW_IMAGES */
DHD_ERROR(("%s: process_nvram_vars len %d\n", __FUNCTION__, len));
#ifdef CUSTOMER_HW4_DEBUG
if (len < MIN_NVRAMVARS_SIZE) {
DHD_ERROR(("%s: invalid nvram size in process_nvram_vars \n",
__FUNCTION__));
bcmerror = BCME_ERROR;
goto err;
}
#endif /* CUSTOMER_HW4_DEBUG */
if (len % 4) {
len += 4 - (len % 4);
}
bufp += len;
*bufp++ = 0;
if (len)
bcmerror = dhdpcie_downloadvars(bus, memblock, len + 1);
if (bcmerror) {
DHD_ERROR(("%s: error downloading vars: %d\n",
__FUNCTION__, bcmerror));
}
}
err:
if (memblock) {
if (local_alloc) {
MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE);
} else {
dhd_free_download_buffer(bus->dhd, memblock, MAX_NVRAMBUF_SIZE);
}
}
return bcmerror;
}
#ifdef BCMEMBEDIMAGE
int
dhdpcie_download_code_array(struct dhd_bus *bus)
{
int bcmerror = -1;
int offset = 0;
unsigned char *p_dlarray = NULL;
unsigned int dlarray_size = 0;
unsigned int downloded_len, remaining_len, len;
char *p_dlimagename, *p_dlimagever, *p_dlimagedate;
uint8 *memblock = NULL, *memptr;
downloded_len = 0;
remaining_len = 0;
len = 0;
p_dlarray = dlarray;
dlarray_size = sizeof(dlarray);
p_dlimagename = dlimagename;
p_dlimagever = dlimagever;
p_dlimagedate = dlimagedate;
if ((p_dlarray == 0) || (dlarray_size == 0) ||(dlarray_size > bus->ramsize) ||
(p_dlimagename == 0) || (p_dlimagever == 0) || (p_dlimagedate == 0))
goto err;
memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
if (memblock == NULL) {
DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK));
goto err;
}
if ((uint32)(uintptr)memblock % DHD_SDALIGN)
memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN));
while (downloded_len < dlarray_size) {
remaining_len = dlarray_size - downloded_len;
if (remaining_len >= MEMBLOCK)
len = MEMBLOCK;
else
len = remaining_len;
memcpy(memptr, (p_dlarray + downloded_len), len);
/* check if CR4/CA7 */
if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0) ||
si_setcore(bus->sih, SYSMEM_CORE_ID, 0)) {
/* if address is 0, store the reset instruction to be written in 0 */
if (offset == 0) {
bus->resetinstr = *(((uint32*)memptr));
/* Add start of RAM address to the address given by user */
offset += bus->dongle_ram_base;
}
}
bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len);
downloded_len += len;
if (bcmerror) {
DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n",
__FUNCTION__, bcmerror, MEMBLOCK, offset));
goto err;
}
offset += MEMBLOCK;
}
#ifdef DHD_DEBUG
/* Upload and compare the downloaded code */
{
unsigned char *ularray = NULL;
unsigned int uploded_len;
uploded_len = 0;
bcmerror = -1;
ularray = MALLOC(bus->dhd->osh, dlarray_size);
if (ularray == NULL)
goto upload_err;
/* Upload image to verify downloaded contents. */
offset = bus->dongle_ram_base;
memset(ularray, 0xaa, dlarray_size);
while (uploded_len < dlarray_size) {
remaining_len = dlarray_size - uploded_len;
if (remaining_len >= MEMBLOCK)
len = MEMBLOCK;
else
len = remaining_len;
bcmerror = dhdpcie_bus_membytes(bus, FALSE, offset,
(uint8 *)(ularray + uploded_len), len);
if (bcmerror) {
DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
__FUNCTION__, bcmerror, MEMBLOCK, offset));
goto upload_err;
}
uploded_len += len;
offset += MEMBLOCK;
}
if (memcmp(p_dlarray, ularray, dlarray_size)) {
DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n",
__FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate));
goto upload_err;
} else
DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n",
__FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate));
upload_err:
if (ularray)
MFREE(bus->dhd->osh, ularray, dlarray_size);
}
#endif /* DHD_DEBUG */
err:
if (memblock)
MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
return bcmerror;
} /* dhdpcie_download_code_array */
#endif /* BCMEMBEDIMAGE */
static int
_dhdpcie_download_firmware(struct dhd_bus *bus)
{
int bcmerror = -1;
bool embed = FALSE; /* download embedded firmware */
bool dlok = FALSE; /* download firmware succeeded */
/* Out immediately if no image to download */
if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
#ifdef BCMEMBEDIMAGE
embed = TRUE;
#else
DHD_ERROR(("%s: no fimrware file\n", __FUNCTION__));
return 0;
#endif
}
/* Keep arm in reset */
if (dhdpcie_bus_download_state(bus, TRUE)) {
DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__));
goto err;
}
/* External image takes precedence if specified */
if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
if (dhdpcie_download_code_file(bus, bus->fw_path)) {
DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__));
#ifdef BCMEMBEDIMAGE
embed = TRUE;
#else
goto err;
#endif
} else {
embed = FALSE;
dlok = TRUE;
}
}
#ifdef BCMEMBEDIMAGE
if (embed) {
if (dhdpcie_download_code_array(bus)) {
DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__));
goto err;
} else {
dlok = TRUE;
}
}
#else
BCM_REFERENCE(embed);
#endif
if (!dlok) {
DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__));
goto err;
}
/* EXAMPLE: nvram_array */
/* If a valid nvram_arry is specified as above, it can be passed down to dongle */
/* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
/* External nvram takes precedence if specified */
if (dhdpcie_download_nvram(bus)) {
DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__));
goto err;
}
/* Take arm out of reset */
if (dhdpcie_bus_download_state(bus, FALSE)) {
DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__));
goto err;
}
bcmerror = 0;
err:
return bcmerror;
} /* _dhdpcie_download_firmware */
#define CONSOLE_LINE_MAX 192
#ifdef DHD_DEBUG
static int
dhdpcie_bus_readconsole(dhd_bus_t *bus)
{
dhd_console_t *c = &bus->console;
uint8 line[CONSOLE_LINE_MAX], ch;
uint32 n, idx, addr;
int rv;
/* Don't do anything until FWREADY updates console address */
if (bus->console_addr == 0)
return -1;
/* Read console log struct */
addr = bus->console_addr + OFFSETOF(hnd_cons_t, log);
if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0)
return rv;
/* Allocate console buffer (one time only) */
if (c->buf == NULL) {
c->bufsize = ltoh32(c->log.buf_size);
if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL)
return BCME_NOMEM;
}
idx = ltoh32(c->log.idx);
/* Protect against corrupt value */
if (idx > c->bufsize)
return BCME_ERROR;
/* Skip reading the console buffer if the index pointer has not moved */
if (idx == c->last)
return BCME_OK;
/* Read the console buffer */
addr = ltoh32(c->log.buf);
if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0)
return rv;
while (c->last != idx) {
for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
if (c->last == idx) {
/* This would output a partial line. Instead, back up
* the buffer pointer and output this line next time around.
*/
if (c->last >= n)
c->last -= n;
else
c->last = c->bufsize - n;
goto break2;
}
ch = c->buf[c->last];
c->last = (c->last + 1) % c->bufsize;
if (ch == '\n')
break;
line[n] = ch;
}
if (n > 0) {
if (line[n - 1] == '\r')
n--;
line[n] = 0;
printf("CONSOLE: %s\n", line);
}
}
break2:
return BCME_OK;
} /* dhdpcie_bus_readconsole */
#endif /* DHD_DEBUG */
static int
dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size)
{
int bcmerror = 0;
uint msize = 512;
char *mbuffer = NULL;
char *console_buffer = NULL;
uint maxstrlen = 256;
char *str = NULL;
trap_t tr;
pciedev_shared_t *pciedev_shared = bus->pcie_sh;
struct bcmstrbuf strbuf;
uint32 console_ptr, console_size, console_index;
uint8 line[CONSOLE_LINE_MAX], ch;
uint32 n, i, addr;
int rv;
DHD_TRACE(("%s: Enter\n", __FUNCTION__));
if (DHD_NOCHECKDIED_ON()) {
return 0;
}
if (data == NULL) {
/*
* Called after a rx ctrl timeout. "data" is NULL.
* allocate memory to trace the trap or assert.
*/
size = msize;
mbuffer = data = MALLOC(bus->dhd->osh, msize);
if (mbuffer == NULL) {
DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize));
bcmerror = BCME_NOMEM;
goto done;
}
}
if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) {
DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen));
bcmerror = BCME_NOMEM;
goto done;
}
if ((bcmerror = dhdpcie_readshared(bus)) < 0) {
goto done;
}
bcm_binit(&strbuf, data, size);
bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
pciedev_shared->msgtrace_addr, pciedev_shared->console_addr);
if ((pciedev_shared->flags & PCIE_SHARED_ASSERT_BUILT) == 0) {
/* NOTE: Misspelled assert is intentional - DO NOT FIX.
* (Avoids conflict with real asserts for programmatic parsing of output.)
*/
bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
}
if ((bus->pcie_sh->flags & (PCIE_SHARED_ASSERT|PCIE_SHARED_TRAP)) == 0) {
/* NOTE: Misspelled assert is intentional - DO NOT FIX.
* (Avoids conflict with real asserts for programmatic parsing of output.)
*/
bcm_bprintf(&strbuf, "No trap%s in dongle",
(bus->pcie_sh->flags & PCIE_SHARED_ASSERT_BUILT)
?"/assrt" :"");
} else {
if (bus->pcie_sh->flags & PCIE_SHARED_ASSERT) {
/* Download assert */
bcm_bprintf(&strbuf, "Dongle assert");
if (bus->pcie_sh->assert_exp_addr != 0) {
str[0] = '\0';
if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE,
bus->pcie_sh->assert_exp_addr,
(uint8 *)str, maxstrlen)) < 0) {
goto done;
}
str[maxstrlen - 1] = '\0';
bcm_bprintf(&strbuf, " expr \"%s\"", str);
}
if (bus->pcie_sh->assert_file_addr != 0) {
str[0] = '\0';
if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE,
bus->pcie_sh->assert_file_addr,
(uint8 *)str, maxstrlen)) < 0) {
goto done;
}
str[maxstrlen - 1] = '\0';
bcm_bprintf(&strbuf, " file \"%s\"", str);
}
bcm_bprintf(&strbuf, " line %d ", bus->pcie_sh->assert_line);
}
if (bus->pcie_sh->flags & PCIE_SHARED_TRAP) {
bus->dhd->dongle_trap_occured = TRUE;
if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE,
bus->pcie_sh->trap_addr, (uint8*)&tr, sizeof(trap_t))) < 0) {
goto done;
}
bcm_bprintf(&strbuf,
"\nTRAP type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
" lp 0x%x, rpc 0x%x"
"\nTrap offset 0x%x, r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, "
"r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n",
ltoh32(tr.type), ltoh32(tr.epc), ltoh32(tr.cpsr), ltoh32(tr.spsr),
ltoh32(tr.r13), ltoh32(tr.r14), ltoh32(tr.pc),
ltoh32(bus->pcie_sh->trap_addr),
ltoh32(tr.r0), ltoh32(tr.r1), ltoh32(tr.r2), ltoh32(tr.r3),
ltoh32(tr.r4), ltoh32(tr.r5), ltoh32(tr.r6), ltoh32(tr.r7));
addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log);
if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr,
(uint8 *)&console_ptr, sizeof(console_ptr))) < 0) {
goto printbuf;
}
addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.buf_size);
if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr,
(uint8 *)&console_size, sizeof(console_size))) < 0) {
goto printbuf;
}
addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.idx);
if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr,
(uint8 *)&console_index, sizeof(console_index))) < 0) {
goto printbuf;
}
console_ptr = ltoh32(console_ptr);
console_size = ltoh32(console_size);
console_index = ltoh32(console_index);
if (console_size > CONSOLE_BUFFER_MAX ||
!(console_buffer = MALLOC(bus->dhd->osh, console_size))) {
goto printbuf;
}
if ((rv = dhdpcie_bus_membytes(bus, FALSE, console_ptr,
(uint8 *)console_buffer, console_size)) < 0) {
goto printbuf;
}
for (i = 0, n = 0; i < console_size; i += n + 1) {
for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
ch = console_buffer[(console_index + i + n) % console_size];
if (ch == '\n')
break;
line[n] = ch;
}
if (n > 0) {
if (line[n - 1] == '\r')
n--;
line[n] = 0;
/* Don't use DHD_ERROR macro since we print
* a lot of information quickly. The macro
* will truncate a lot of the printfs
*/
printf("CONSOLE: %s\n", line);
}
}
}
}
printbuf:
if (bus->pcie_sh->flags & (PCIE_SHARED_ASSERT | PCIE_SHARED_TRAP)) {
printf("%s: %s\n", __FUNCTION__, strbuf.origbuf);
/* wake up IOCTL wait event */
dhd_wakeup_ioctl_event(bus->dhd, IOCTL_RETURN_ON_TRAP);
#if defined(DHD_FW_COREDUMP)
/* save core dump or write to a file */
if (bus->dhd->memdump_enabled) {
bus->dhd->memdump_type = DUMP_TYPE_DONGLE_TRAP;
dhdpcie_mem_dump(bus);
}
#endif /* DHD_FW_COREDUMP */
}
done:
if (mbuffer)
MFREE(bus->dhd->osh, mbuffer, msize);
if (str)
MFREE(bus->dhd->osh, str, maxstrlen);
if (console_buffer)
MFREE(bus->dhd->osh, console_buffer, console_size);
return bcmerror;
} /* dhdpcie_checkdied */
/* Custom copy of dhdpcie_mem_dump() that can be called at interrupt level */
void dhdpcie_mem_dump_bugcheck(dhd_bus_t *bus, uint8 *buf)
{
int ret = 0;
int size; /* Full mem size */
int start; /* Start address */
int read_size = 0; /* Read size of each iteration */
uint8 *databuf = buf;
if (bus == NULL) {
return;
}
start = bus->dongle_ram_base;
/* Get full mem size */
size = bus->ramsize;
/* Read mem content */
while (size)
{
read_size = MIN(MEMBLOCK, size);
if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size))) {
return;
}
/* Decrement size and increment start address */
size -= read_size;
start += read_size;
databuf += read_size;
}
bus->dhd->soc_ram = buf;
bus->dhd->soc_ram_length = bus->ramsize;
return;
}
#if defined(DHD_FW_COREDUMP)
static int
dhdpcie_mem_dump(dhd_bus_t *bus)
{
int ret = 0;
int size; /* Full mem size */
int start = bus->dongle_ram_base; /* Start address */
int read_size = 0; /* Read size of each iteration */
uint8 *buf = NULL, *databuf = NULL;
#ifdef EXYNOS_PCIE_DEBUG
exynos_pcie_register_dump(1);
#endif /* EXYNOS_PCIE_DEBUG */
#ifdef SUPPORT_LINKDOWN_RECOVERY
if (bus->is_linkdown) {
DHD_ERROR(("%s: PCIe link was down so skip\n", __FUNCTION__));
return BCME_ERROR;
}
#endif /* SUPPORT_LINKDOWN_RECOVERY */
/* Get full mem size */
size = bus->ramsize;
#if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_MEMDUMP)
buf = DHD_OS_PREALLOC(bus->dhd, DHD_PREALLOC_MEMDUMP_BUF, size);
bzero(buf, size);
#else
buf = MALLOC(bus->dhd->osh, size);
#endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_MEMDUMP */
if (!buf) {
DHD_ERROR(("%s: Out of memory (%d bytes)\n", __FUNCTION__, size));
return BCME_ERROR;
}
/* Read mem content */
DHD_TRACE_HW4(("Dump dongle memory"));
databuf = buf;
while (size)
{
read_size = MIN(MEMBLOCK, size);
if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size)))
{
DHD_ERROR(("%s: Error membytes %d\n", __FUNCTION__, ret));
if (buf) {
MFREE(bus->dhd->osh, buf, size);
}
return BCME_ERROR;
}
DHD_TRACE(("."));
/* Decrement size and increment start address */
size -= read_size;
start += read_size;
databuf += read_size;
}
DHD_TRACE_HW4(("%s FUNC: Copy fw image to the embedded buffer \n", __FUNCTION__));
dhd_save_fwdump(bus->dhd, buf, bus->ramsize);
dhd_schedule_memdump(bus->dhd, buf, bus->ramsize);
return ret;
}
int
dhd_bus_mem_dump(dhd_pub_t *dhdp)
{
dhd_bus_t *bus = dhdp->bus;
if (bus->suspended) {
DHD_ERROR(("%s: Bus is suspend so skip\n", __FUNCTION__));
return 0;
}
return dhdpcie_mem_dump(bus);
}
#endif /* DHD_FW_COREDUMP */
int
dhd_socram_dump(dhd_bus_t *bus)
{
#if defined(DHD_FW_COREDUMP)
return (dhdpcie_mem_dump(bus));
#else
return -1;
#endif
}
/**
* Transfers bytes from host to dongle using pio mode.
* Parameter 'address' is a backplane address.
*/
static int
dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size)
{
uint dsize;
int detect_endian_flag = 0x01;
bool little_endian;
#if defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
bool is_64bit_unaligned;
#endif /* defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */
if (write && bus->is_linkdown) {
DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__));
return BCME_ERROR;
}
/* Detect endianness. */
little_endian = *(char *)&detect_endian_flag;
#if defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
/* Check 64bit aligned or not. */
is_64bit_unaligned = (address & 0x7);
#endif /* defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */
/* In remap mode, adjust address beyond socram and redirect
* to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize
* is not backplane accessible
*/
/* Determine initial transfer parameters */
dsize = sizeof(uint64);
/* Do the transfer(s) */
if (write) {
while (size) {
if (size >= sizeof(uint64) && little_endian) {
#if defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
if (is_64bit_unaligned) {
DHD_INFO(("%s: write unaligned %lx\n",
__FUNCTION__, address));
dhdpcie_bus_wtcm32(bus, address, *((uint32 *)data));
data += 4;
size -= 4;
address += 4;
is_64bit_unaligned = (address & 0x7);
continue;
}
else
#endif
dhdpcie_bus_wtcm64(bus, address, *((uint64 *)data));
} else {
dsize = sizeof(uint8);
dhdpcie_bus_wtcm8(bus, address, *data);
}
/* Adjust for next transfer (if any) */
if ((size -= dsize)) {
data += dsize;
address += dsize;
}
}
} else {
while (size) {
if (size >= sizeof(uint64) && little_endian) {
#if defined(CONFIG_64BIT) || defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
if (is_64bit_unaligned) {
DHD_INFO(("%s: read unaligned %lx\n",
__FUNCTION__, address));
*(uint32 *)data = dhdpcie_bus_rtcm32(bus, address);
data += 4;
size -= 4;
address += 4;
is_64bit_unaligned = (address & 0x7);
continue;
}
else
#endif
*(uint64 *)data = dhdpcie_bus_rtcm64(bus, address);
} else {
dsize = sizeof(uint8);
*data = dhdpcie_bus_rtcm8(bus, address);
}
/* Adjust for next transfer (if any) */
if ((size -= dsize) > 0) {
data += dsize;
address += dsize;
}
}
}
return BCME_OK;
} /* dhdpcie_bus_membytes */
/**
* Transfers one transmit (ethernet) packet that was queued in the (flow controlled) flow ring queue
* to the (non flow controlled) flow ring.
*/
int BCMFASTPATH
dhd_bus_schedule_queue(struct dhd_bus *bus, uint16 flow_id, bool txs)
{
flow_ring_node_t *flow_ring_node;
int ret = BCME_OK;
#ifdef DHD_LOSSLESS_ROAMING
dhd_pub_t *dhdp = bus->dhd;
#endif
DHD_INFO(("%s: flow_id is %d\n", __FUNCTION__, flow_id));
/* ASSERT on flow_id */
if (flow_id >= bus->max_sub_queues) {
DHD_ERROR(("%s: flow_id is invalid %d, max %d\n", __FUNCTION__,
flow_id, bus->max_sub_queues));
return 0;
}
flow_ring_node = DHD_FLOW_RING(bus->dhd, flow_id);
#ifdef DHD_LOSSLESS_ROAMING
if ((dhdp->dequeue_prec_map & (1 << flow_ring_node->flow_info.tid)) == 0) {
DHD_INFO(("%s: tid %d is not in precedence map. block scheduling\n",
__FUNCTION__, flow_ring_node->flow_info.tid));
return BCME_OK;
}
#endif /* DHD_LOSSLESS_ROAMING */
{
unsigned long flags;
void *txp = NULL;
flow_queue_t *queue;
#ifdef DHD_LOSSLESS_ROAMING
struct ether_header *eh;
uint8 *pktdata;
#endif /* DHD_LOSSLESS_ROAMING */
queue = &flow_ring_node->queue; /* queue associated with flow ring */
DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
if (flow_ring_node->status != FLOW_RING_STATUS_OPEN) {
DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
return BCME_NOTREADY;
}
while ((txp = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) {
PKTORPHAN(txp, bus->dhd->conf->tsq);
/*
* Modifying the packet length caused P2P cert failures.
* Specifically on test cases where a packet of size 52 bytes
* was injected, the sniffer capture showed 62 bytes because of
* which the cert tests failed. So making the below change
* only Router specific.
*/
#ifdef DHDTCPACK_SUPPRESS
if (bus->dhd->tcpack_sup_mode != TCPACK_SUP_HOLD) {
ret = dhd_tcpack_check_xmit(bus->dhd, txp);
if (ret != BCME_OK) {
DHD_ERROR(("%s: dhd_tcpack_check_xmit() error.\n",
__FUNCTION__));
}
}
#endif /* DHDTCPACK_SUPPRESS */
#ifdef DHD_LOSSLESS_ROAMING
pktdata = (uint8 *)PKTDATA(OSH_NULL, txp);
eh = (struct ether_header *) pktdata;
if (eh->ether_type == hton16(ETHER_TYPE_802_1X)) {
uint8 prio = (uint8)PKTPRIO(txp);
/* Restore to original priority for 802.1X packet */
if (prio == PRIO_8021D_NC) {
PKTSETPRIO(txp, PRIO_8021D_BE);
}
}
#endif /* DHD_LOSSLESS_ROAMING */
/* Attempt to transfer packet over flow ring */
ret = dhd_prot_txdata(bus->dhd, txp, flow_ring_node->flow_info.ifindex);
if (ret != BCME_OK) { /* may not have resources in flow ring */
DHD_INFO(("%s: Reinserrt %d\n", __FUNCTION__, ret));
dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE);
/* reinsert at head */
dhd_flow_queue_reinsert(bus->dhd, queue, txp);
DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
/* If we are able to requeue back, return success */
return BCME_OK;
}
}
dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE);
DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
}
return ret;
} /* dhd_bus_schedule_queue */
/** Sends an (ethernet) data frame (in 'txp') to the dongle. Callee disposes of txp. */
int BCMFASTPATH
dhd_bus_txdata(struct dhd_bus *bus, void *txp, uint8 ifidx)
{
uint16 flowid;
flow_queue_t *queue;
flow_ring_node_t *flow_ring_node;
unsigned long flags;
int ret = BCME_OK;
void *txp_pend = NULL;
if (!bus->dhd->flowid_allocator) {
DHD_ERROR(("%s: Flow ring not intited yet \n", __FUNCTION__));
goto toss;
}
flowid = DHD_PKT_GET_FLOWID(txp);
flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid);
DHD_TRACE(("%s: pkt flowid %d, status %d active %d\n",
__FUNCTION__, flowid, flow_ring_node->status,
flow_ring_node->active));
DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
if ((flowid >= bus->dhd->num_flow_rings) ||
(!flow_ring_node->active) ||
(flow_ring_node->status == FLOW_RING_STATUS_DELETE_PENDING) ||
(flow_ring_node->status == FLOW_RING_STATUS_STA_FREEING)) {
DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
DHD_INFO(("%s: Dropping pkt flowid %d, status %d active %d\n",
__FUNCTION__, flowid, flow_ring_node->status,
flow_ring_node->active));
ret = BCME_ERROR;
goto toss;
}
queue = &flow_ring_node->queue; /* queue associated with flow ring */
if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp)) != BCME_OK) {
txp_pend = txp;
}
DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
if (flow_ring_node->status) {
DHD_INFO(("%s: Enq pkt flowid %d, status %d active %d\n",
__FUNCTION__, flowid, flow_ring_node->status,
flow_ring_node->active));
if (txp_pend) {
txp = txp_pend;
goto toss;
}
return BCME_OK;
}
ret = dhd_bus_schedule_queue(bus, flowid, FALSE); /* from queue to flowring */
/* If we have anything pending, try to push into q */
if (txp_pend) {
DHD_FLOWRING_LOCK(flow_ring_node->lock, flags);
if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp_pend)) != BCME_OK) {
DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
txp = txp_pend;
goto toss;
}
DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags);
}
return ret;
toss:
DHD_INFO(("%s: Toss %d\n", __FUNCTION__, ret));
PKTCFREE(bus->dhd->osh, txp, TRUE);
return ret;
} /* dhd_bus_txdata */
void
dhd_bus_stop_queue(struct dhd_bus *bus)
{
dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON);
bus->bus_flowctrl = TRUE;
}
void
dhd_bus_start_queue(struct dhd_bus *bus)
{
dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF);
bus->bus_flowctrl = TRUE;
}
#if defined(DHD_DEBUG)
/* Device console input function */
int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen)
{
dhd_bus_t *bus = dhd->bus;
uint32 addr, val;
int rv;
/* Address could be zero if CONSOLE := 0 in dongle Makefile */
if (bus->console_addr == 0)
return BCME_UNSUPPORTED;
/* Don't allow input if dongle is in reset */
if (bus->dhd->dongle_reset) {
dhd_os_sdunlock(bus->dhd);
return BCME_NOTREADY;
}
/* Zero cbuf_index */
addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx);
val = htol32(0);
if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
goto done;
/* Write message into cbuf */
addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf);
if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0)
goto done;
/* Write length into vcons_in */
addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in);
val = htol32(msglen);
if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0)
goto done;
/* generate an interrupt to dongle to indicate that it needs to process cons command */
dhdpcie_send_mb_data(bus, H2D_HOST_CONS_INT);
done:
return rv;
} /* dhd_bus_console_in */
#endif /* defined(DHD_DEBUG) */
/**
* Called on frame reception, the frame was received from the dongle on interface 'ifidx' and is
* contained in 'pkt'. Processes rx frame, forwards up the layer to netif.
*/
void BCMFASTPATH
dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count)
{
dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, 0);
}
#if defined(DHD_PCIE_BAR1_WIN_BASE_FIX)
static ulong dhd_bus_cmn_check_offset(dhd_bus_t *bus, ulong offset)
{
uint new_bar1_wbase = 0;
ulong address = 0;
new_bar1_wbase = (uint)offset & bus->bar1_win_mask;
if (bus->bar1_win_base != new_bar1_wbase) {
bus->bar1_win_base = new_bar1_wbase;
dhdpcie_bus_cfg_set_bar1_win(bus, bus->bar1_win_base);
DHD_ERROR(("%s: offset=%lx, switch bar1_win_base to %x\n",
__FUNCTION__, offset, bus->bar1_win_base));
}
address = offset - bus->bar1_win_base;
return address;
}
#else
#define dhd_bus_cmn_check_offset(x, y) y
#endif /* defined(DHD_PCIE_BAR1_WIN_BASE_FIX) */
/** 'offset' is a backplane address */
void
dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data)
{
*(volatile uint8 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint8)data;
}
uint8
dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset)
{
volatile uint8 data;
data = *(volatile uint8 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset));
return data;
}
void
dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data)
{
*(volatile uint32 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint32)data;
}
void
dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data)
{
*(volatile uint16 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint16)data;
}
void
dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data)
{
*(volatile uint64 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint64)data;
}
uint16
dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset)
{
volatile uint16 data;
data = *(volatile uint16 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset));
return data;
}
uint32
dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset)
{
volatile uint32 data;
data = *(volatile uint32 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset));
return data;
}
uint64
dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset)
{
volatile uint64 data;
data = *(volatile uint64 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset));
return data;
}
/** A snippet of dongle memory is shared between host and dongle */
void
dhd_bus_cmn_writeshared(dhd_bus_t *bus, void *data, uint32 len, uint8 type, uint16 ringid)
{
uint64 long_data;
ulong tcm_offset;
DHD_INFO(("%s: writing to dongle type %d len %d\n", __FUNCTION__, type, len));
if (bus->is_linkdown) {
DHD_ERROR(("%s: PCIe link was down\n", __FUNCTION__));
return;
}
switch (type) {
case D2H_DMA_SCRATCH_BUF:
{
pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
long_data = HTOL64(*(uint64 *)data);
tcm_offset = (ulong)&(sh->host_dma_scratch_buffer);
dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
prhex(__FUNCTION__, data, len);
break;
}
case D2H_DMA_SCRATCH_BUF_LEN:
{
pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
tcm_offset = (ulong)&(sh->host_dma_scratch_buffer_len);
dhdpcie_bus_wtcm32(bus, tcm_offset, (uint32) HTOL32(*(uint32 *)data));
prhex(__FUNCTION__, data, len);
break;
}
case H2D_DMA_INDX_WR_BUF:
{
pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
long_data = HTOL64(*(uint64 *)data);
tcm_offset = (ulong)shmem->rings_info_ptr;
tcm_offset += OFFSETOF(ring_info_t, h2d_w_idx_hostaddr);
dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
prhex(__FUNCTION__, data, len);
break;
}
case H2D_DMA_INDX_RD_BUF:
{
pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
long_data = HTOL64(*(uint64 *)data);
tcm_offset = (ulong)shmem->rings_info_ptr;
tcm_offset += OFFSETOF(ring_info_t, h2d_r_idx_hostaddr);
dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
prhex(__FUNCTION__, data, len);
break;
}
case D2H_DMA_INDX_WR_BUF:
{
pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
long_data = HTOL64(*(uint64 *)data);
tcm_offset = (ulong)shmem->rings_info_ptr;
tcm_offset += OFFSETOF(ring_info_t, d2h_w_idx_hostaddr);
dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
prhex(__FUNCTION__, data, len);
break;
}
case D2H_DMA_INDX_RD_BUF:
{
pciedev_shared_t *shmem = (pciedev_shared_t *)bus->pcie_sh;
long_data = HTOL64(*(uint64 *)data);
tcm_offset = (ulong)shmem->rings_info_ptr;
tcm_offset += OFFSETOF(ring_info_t, d2h_r_idx_hostaddr);
dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len);
prhex(__FUNCTION__, data, len);
break;
}
case RING_ITEM_LEN:
tcm_offset = bus->ring_sh[ringid].ring_mem_addr;
tcm_offset += OFFSETOF(ring_mem_t, len_items);
dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data));
break;
case RING_MAX_ITEMS:
tcm_offset = bus->ring_sh[ringid].ring_mem_addr;
tcm_offset += OFFSETOF(ring_mem_t, max_item);
dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data));
break;
case RING_BUF_ADDR:
long_data = HTOL64(*(uint64 *)data);
tcm_offset = bus->ring_sh[ringid].ring_mem_addr;
tcm_offset += OFFSETOF(ring_mem_t, base_addr);
dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8 *) &long_data, len);
prhex(__FUNCTION__, data, len);
break;
case RING_WR_UPD:
tcm_offset = bus->ring_sh[ringid].ring_state_w;
dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data));
break;
case RING_RD_UPD:
tcm_offset = bus->ring_sh[ringid].ring_state_r;
dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data));
break;
case D2H_MB_DATA:
dhdpcie_bus_wtcm32(bus, bus->d2h_mb_data_ptr_addr,
(uint32) HTOL32(*(uint32 *)data));
break;
case H2D_MB_DATA:
dhdpcie_bus_wtcm32(bus, bus->h2d_mb_data_ptr_addr,
(uint32) HTOL32(*(uint32 *)data));
break;
default:
break;
}
} /* dhd_bus_cmn_writeshared */
/** A snippet of dongle memory is shared between host and dongle */
void
dhd_bus_cmn_readshared(dhd_bus_t *bus, void* data, uint8 type, uint16 ringid)
{
ulong tcm_offset;
switch (type) {
case RING_WR_UPD:
tcm_offset = bus->ring_sh[ringid].ring_state_w;
*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset));
break;
case RING_RD_UPD:
tcm_offset = bus->ring_sh[ringid].ring_state_r;
*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset));
break;
case TOTAL_LFRAG_PACKET_CNT:
{
pciedev_shared_t *sh = (pciedev_shared_t*)bus->shared_addr;
*(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus,
(ulong) &sh->total_lfrag_pkt_cnt));
break;
}
case H2D_MB_DATA:
*(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->h2d_mb_data_ptr_addr));
break;
case D2H_MB_DATA:
*(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->d2h_mb_data_ptr_addr));
break;