| /** @file pcie_core.c |
| * |
| * Contains PCIe related functions that are shared between different driver models (e.g. firmware |
| * builds, DHD builds, BMAC builds), in order to avoid code duplication. |
| * |
| * Copyright 1999-2016, Broadcom Corporation |
| * All rights reserved, |
| * |
| * Redistribution and use in source and binary forms, with or without modification, |
| * are permitted provided that the following conditions are met: |
| * 1. Redistributions of source code must retain the above copyright notice, |
| * this list of conditions and the following disclaimer. |
| * 2. Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * This software is provided by the copyright holder "as is" and any express or |
| * implied warranties, including, but not limited to, the implied warranties of |
| * merchantability and fitness for a particular purpose are disclaimed. In no event |
| * shall copyright holder be liable for any direct, indirect, incidental, special, |
| * exemplary, or consequential damages (including, but not limited to, procurement |
| * of substitute goods or services; loss of use, data, or profits; or business |
| * interruption) however caused and on any theory of liability, whether in |
| * contract, strict liability, or tort (including negligence or otherwise) arising |
| * in any way out of the use of this software, even if advised of the possibility |
| * of such damage |
| * |
| * |
| * <<Broadcom-WL-IPTag/Open:>> |
| * |
| * $Id: pcie_core.c 591285 2015-10-07 11:56:29Z $ |
| */ |
| |
| #include <bcm_cfg.h> |
| #include <typedefs.h> |
| #include <bcmutils.h> |
| #include <bcmdefs.h> |
| #include <osl.h> |
| #include <siutils.h> |
| #include <hndsoc.h> |
| #include <sbchipc.h> |
| |
| #include "pcie_core.h" |
| |
| /* local prototypes */ |
| |
| /* local variables */ |
| |
| /* function definitions */ |
| |
| #ifdef BCMDRIVER |
| |
| void pcie_watchdog_reset(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs) |
| { |
| uint32 val, i, lsc; |
| uint16 cfg_offset[] = {PCIECFGREG_STATUS_CMD, PCIECFGREG_PM_CSR, |
| PCIECFGREG_MSI_CAP, PCIECFGREG_MSI_ADDR_L, |
| PCIECFGREG_MSI_ADDR_H, PCIECFGREG_MSI_DATA, |
| PCIECFGREG_LINK_STATUS_CTRL2, PCIECFGREG_RBAR_CTRL, |
| PCIECFGREG_PML1_SUB_CTRL1, PCIECFGREG_REG_BAR2_CONFIG, |
| PCIECFGREG_REG_BAR3_CONFIG}; |
| sbpcieregs_t *pcie = NULL; |
| uint32 origidx = si_coreidx(sih); |
| |
| /* Switch to PCIE2 core */ |
| pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0); |
| BCM_REFERENCE(pcie); |
| ASSERT(pcie != NULL); |
| |
| /* Disable/restore ASPM Control to protect the watchdog reset */ |
| W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL); |
| lsc = R_REG(osh, &sbpcieregs->configdata); |
| val = lsc & (~PCIE_ASPM_ENAB); |
| W_REG(osh, &sbpcieregs->configdata, val); |
| |
| si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 4); |
| OSL_DELAY(100000); |
| |
| W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL); |
| W_REG(osh, &sbpcieregs->configdata, lsc); |
| |
| if (sih->buscorerev <= 13) { |
| /* Write configuration registers back to the shadow registers |
| * cause shadow registers are cleared out after watchdog reset. |
| */ |
| for (i = 0; i < ARRAYSIZE(cfg_offset); i++) { |
| W_REG(osh, &sbpcieregs->configaddr, cfg_offset[i]); |
| val = R_REG(osh, &sbpcieregs->configdata); |
| W_REG(osh, &sbpcieregs->configdata, val); |
| } |
| } |
| si_setcoreidx(sih, origidx); |
| } |
| |
| |
| /* CRWLPCIEGEN2-117 pcie_pipe_Iddq should be controlled |
| * by the L12 state from MAC to save power by putting the |
| * SerDes analog in IDDQ mode |
| */ |
| void pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs) |
| { |
| sbpcieregs_t *pcie = NULL; |
| uint crwlpciegen2_117_disable = 0; |
| uint32 origidx = si_coreidx(sih); |
| |
| crwlpciegen2_117_disable = PCIE_PipeIddqDisable0 | PCIE_PipeIddqDisable1; |
| /* Switch to PCIE2 core */ |
| pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0); |
| BCM_REFERENCE(pcie); |
| ASSERT(pcie != NULL); |
| |
| OR_REG(osh, &sbpcieregs->control, |
| crwlpciegen2_117_disable); |
| |
| si_setcoreidx(sih, origidx); |
| } |
| #endif /* BCMDRIVER */ |