| commit | c27a444e54d531f8a0cd33e67dc46ff7c763cc4b | [log] [tgz] |
|---|---|---|
| author | Henrik Smiding <henrik.smiding@intel.com> | Wed Jan 15 16:12:02 2014 +0100 |
| committer | Wang LiangX <liangx.wang@intel.com> | Fri Apr 18 11:31:54 2014 +0800 |
| tree | f93e108d398788c0b25572c673d14e0f230b4f52 | |
| parent | a740b3bb409c9acdf4cf6a829b982e57a89d08de [diff] |
Add Silvermont architecture cache sizes Adds Silvermont specific cache sizes for memset16/32 SSE optimization. Change-Id: Ib5ea086d57544e74ac384ee1ef516b8511392f70 Signed-off-by: Henrik Smiding <henrik.smiding@intel.com>