commit 537ecaaa2a6d26d9c0752555eb9e781e59747a07
author Chris Masone <cmasone@google.com> Thu Feb 29 22:53:29 2024 +0000
committer Copybara-Service <copybara-worker@google.com> Thu Feb 29 14:54:23 2024 -0800
tree dbb89e04c2493b442bb90d1bf94b290b10202138
parent b18ccf435ede06d6923374700b4cea4937a20417

Merge "Implement Sequence Lock for RISC-V" into main

GitOrigin-RevId: f1242f942e7b79ca0445bc1172f1788cd968dc64
Change-Id: I9218087e4ecaa909fb42b626001e4d945ca384fa

base/include/aemu/base/synchronization/Lock.h

diff --git a/base/include/aemu/base/synchronization/Lock.h b/base/include/aemu/base/synchronization/Lock.h
index 2b88f05..281a970 100644
--- a/base/include/aemu/base/synchronization/Lock.h
+++ b/base/include/aemu/base/synchronization/Lock.h
@@ -237,6 +237,8 @@
         asm volatile("dmb ishst" ::: "memory");
 #elif defined(__x86_64__)
         std::atomic_thread_fence(std::memory_order_release);
+#elif defined(__riscv) && (__riscv_xlen == 64)
+        std::atomic_thread_fence(std::memory_order_release);
 #else
 #error "Unimplemented SmpWmb for current CPU architecture"
 #endif
@@ -247,6 +249,8 @@
         asm volatile("dmb ishld" ::: "memory");
 #elif defined(__x86_64__)
         std::atomic_thread_fence(std::memory_order_acquire);
+#elif defined(__riscv) && (__riscv_xlen == 64)
+        std::atomic_thread_fence(std::memory_order_acquire);
 #else
 #error "Unimplemented SmpRmb for current CPU architecture"
 #endif