fuchsia.hardware.pci
PROTOCOLS
Bus
Defined in fuchsia.hardware.pci/pci.fidl
GetDevices
Request {#Bus.GetDevices_Request}
<EMPTY>
Response {#Bus.GetDevices_Response}
GetHostBridgeInfo
Request {#Bus.GetHostBridgeInfo_Request}
<EMPTY>
Response {#Bus.GetHostBridgeInfo_Response}
Pci
Defined in fuchsia.hardware.pci/pci.fidl
AckInterrupt
Request {#Pci.AckInterrupt_Request}
<EMPTY>
Response {#Pci.AckInterrupt_Response}
ConfigRead16
Request {#Pci.ConfigRead16_Request}
Response {#Pci.ConfigRead16_Response}
ConfigRead32
Request {#Pci.ConfigRead32_Request}
Response {#Pci.ConfigRead32_Response}
ConfigRead8
Request {#Pci.ConfigRead8_Request}
Response {#Pci.ConfigRead8_Response}
ConfigWrite16
Request {#Pci.ConfigWrite16_Request}
Response {#Pci.ConfigWrite16_Response}
ConfigWrite32
Request {#Pci.ConfigWrite32_Request}
Response {#Pci.ConfigWrite32_Response}
ConfigWrite8
Request {#Pci.ConfigWrite8_Request}
Response {#Pci.ConfigWrite8_Response}
ConfigureIrqMode
Request {#Pci.ConfigureIrqMode_Request}
Response {#Pci.ConfigureIrqMode_Response}
EnableBusMaster
Request {#Pci.EnableBusMaster_Request}
Response {#Pci.EnableBusMaster_Response}
GetBar
Request {#Pci.GetBar_Request}
Response {#Pci.GetBar_Response}
GetBti
Request {#Pci.GetBti_Request}
Response {#Pci.GetBti_Response}
GetDeviceInfo
Request {#Pci.GetDeviceInfo_Request}
<EMPTY>
Response {#Pci.GetDeviceInfo_Response}
GetFirstCapability
Request {#Pci.GetFirstCapability_Request}
Response {#Pci.GetFirstCapability_Response}
GetFirstExtendedCapability
Request {#Pci.GetFirstExtendedCapability_Request}
Response {#Pci.GetFirstExtendedCapability_Response}
GetNextCapability
Request {#Pci.GetNextCapability_Request}
Response {#Pci.GetNextCapability_Response}
GetNextExtendedCapability
Request {#Pci.GetNextExtendedCapability_Request}
Response {#Pci.GetNextExtendedCapability_Response}
MapInterrupt
Request {#Pci.MapInterrupt_Request}
Response {#Pci.MapInterrupt_Response}
QueryIrqMode
Request {#Pci.QueryIrqMode_Request}
Response {#Pci.QueryIrqMode_Response}
ResetDevice
Request {#Pci.ResetDevice_Request}
<EMPTY>
Response {#Pci.ResetDevice_Response}
SetIrqMode
Request {#Pci.SetIrqMode_Request}
Response {#Pci.SetIrqMode_Response}
STRUCTS
BaseAddress {#BaseAddress data-text=“BaseAddress”}
Defined in fuchsia.hardware.pci/pci.fidl
Capability {#Capability data-text=“Capability”}
Defined in fuchsia.hardware.pci/pci.fidl
Device {#Device data-text=“Device”}
Defined in fuchsia.hardware.pci/pci.fidl
ExtendedCapability {#ExtendedCapability data-text=“ExtendedCapability”}
Defined in fuchsia.hardware.pci/pci.fidl
HostBridgeInfo {#HostBridgeInfo data-text=“HostBridgeInfo”}
Defined in fuchsia.hardware.pci/pci.fidl
ENUMS
PciCapId strict{:.fidl-attribute}
Type: uint8
Defined in fuchsia.hardware.pci/pci.fidl
PciCfg strict{:.fidl-attribute}
Type: uint16
Defined in fuchsia.hardware.pci/pci.fidl
PciExtCapId strict{:.fidl-attribute}
Type: uint16
Defined in fuchsia.hardware.pci/pci.fidl
PciIrqMode strict{:.fidl-attribute}
Type: uint8
Defined in fuchsia.hardware.pci/pci.fidl
CONSTANTS
