fuchsia.hardware.cpu.insntrace

PROTOCOLS

Controller

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

AllocateBuffer

Request {#Controller.AllocateBuffer_Request}

Response {#Controller.AllocateBuffer_Response}

AssignThreadBuffer

Request {#Controller.AssignThreadBuffer_Request}

Response {#Controller.AssignThreadBuffer_Response}

FreeBuffer

Request {#Controller.FreeBuffer_Request}

Response {#Controller.FreeBuffer_Response}

<EMPTY>

GetAllocation

Request {#Controller.GetAllocation_Request}

<EMPTY>

Response {#Controller.GetAllocation_Response}

GetBufferConfig

Request {#Controller.GetBufferConfig_Request}

Response {#Controller.GetBufferConfig_Response}

GetBufferState

Request {#Controller.GetBufferState_Request}

Response {#Controller.GetBufferState_Response}

GetChunkHandle

Request {#Controller.GetChunkHandle_Request}

Response {#Controller.GetChunkHandle_Response}

Initialize

Request {#Controller.Initialize_Request}

Response {#Controller.Initialize_Response}

ReleaseThreadBuffer

Request {#Controller.ReleaseThreadBuffer_Request}

Response {#Controller.ReleaseThreadBuffer_Response}

Start

Request {#Controller.Start_Request}

<EMPTY>

Response {#Controller.Start_Response}

<EMPTY>

Stop

Request {#Controller.Stop_Request}

<EMPTY>

Response {#Controller.Stop_Response}

<EMPTY>

Terminate

Request {#Controller.Terminate_Request}

<EMPTY>

Response {#Controller.Terminate_Response}

STRUCTS

AddressRange {#AddressRange data-text=“AddressRange”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

Allocation {#Allocation data-text=“Allocation”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

BufferConfig {#BufferConfig data-text=“BufferConfig”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

BufferState {#BufferState data-text=“BufferState”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

Controller_AllocateBuffer_Response {#Controller_AllocateBuffer_Response data-text=“Controller_AllocateBuffer_Response”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

Controller_AssignThreadBuffer_Response {#Controller_AssignThreadBuffer_Response data-text=“Controller_AssignThreadBuffer_Response”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

<EMPTY>

Controller_Initialize_Response {#Controller_Initialize_Response data-text=“Controller_Initialize_Response”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

<EMPTY>

Controller_ReleaseThreadBuffer_Response {#Controller_ReleaseThreadBuffer_Response data-text=“Controller_ReleaseThreadBuffer_Response”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

<EMPTY>

Controller_Terminate_Response {#Controller_Terminate_Response data-text=“Controller_Terminate_Response”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

<EMPTY>

ENUMS

Mode strict{:.fidl-attribute}

Type: uint8

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

UNIONS

Controller_AllocateBuffer_Result strict{:.fidl-attribute} {#Controller_AllocateBuffer_Result data-text=“Controller_AllocateBuffer_Result”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

Controller_AssignThreadBuffer_Result strict{:.fidl-attribute} {#Controller_AssignThreadBuffer_Result data-text=“Controller_AssignThreadBuffer_Result”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

Controller_Initialize_Result strict{:.fidl-attribute} {#Controller_Initialize_Result data-text=“Controller_Initialize_Result”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

Controller_ReleaseThreadBuffer_Result strict{:.fidl-attribute} {#Controller_ReleaseThreadBuffer_Result data-text=“Controller_ReleaseThreadBuffer_Result”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

Controller_Terminate_Result strict{:.fidl-attribute} {#Controller_Terminate_Result data-text=“Controller_Terminate_Result”}

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

CONSTANTS

TYPE ALIASES