fuchsia.hardware.cpu.insntrace

PROTOCOLS

Controller

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

Initialize

Request

Response

Terminate

Request

Response

GetAllocation

Request

Response

AllocateBuffer

Request

Response

AssignThreadBuffer

Request

Response

ReleaseThreadBuffer

Request

Response

GetBufferConfig

Request

Response

GetBufferState

Request

Response

GetChunkHandle

Request

Response

FreeBuffer

Request

Response

Start

Request

Response

Stop

Request

Response

STRUCTS

Controller_Initialize_Response {#Controller_Initialize_Response}

generated

Controller_Terminate_Response {#Controller_Terminate_Response}

generated

Controller_AllocateBuffer_Response {#Controller_AllocateBuffer_Response}

generated

Controller_AssignThreadBuffer_Response {#Controller_AssignThreadBuffer_Response}

generated

Controller_ReleaseThreadBuffer_Response {#Controller_ReleaseThreadBuffer_Response}

generated

Allocation

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

AddressRange

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

BufferConfig

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

BufferState

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

ENUMS

Mode

Type: uint8

Defined in fuchsia.hardware.cpu.insntrace/insntrace.fidl

UNIONS

Controller_Initialize_Result {#Controller_Initialize_Result}

generated

Controller_Terminate_Result {#Controller_Terminate_Result}

generated

Controller_AllocateBuffer_Result {#Controller_AllocateBuffer_Result}

generated

Controller_AssignThreadBuffer_Result {#Controller_AssignThreadBuffer_Result}

generated

Controller_ReleaseThreadBuffer_Result {#Controller_ReleaseThreadBuffer_Result}

generated

CONSTANTS