tree febcb96c7f191ff7e8a443731f23ed90289f8a2c
parent 9eda0ca5e25a5d85e006bea8b25d6f7cb8a2f71b
author Joshua Seaton <joshuaseaton@fuchsia.infra.roller.google.com> 1694217065 +0000
committer Copybara-Service <copybara-worker@google.com> 1694217133 -0700

[roll] Roll fuchsia [kernel][phys] Introduce AddressSpace

This change introduces `AddressSpace`, a phys abstraction for a virtual
address space. It acts as a wrapper around the libarch PagingTrait APIs
and replaces libpage-table phys uses in this CL.

The only behaviour change is that arm paging goes from 3-level, using a
constrained virtual address space with 39 addressable bits to the
'normal' 48-bit one (which is what the kernel uses).

Original-Bug: 129344
Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/876197
Original-Revision: c4adda40a6c9cea5fcec89547daa91db0adfbd27
GitOrigin-RevId: 5686b0ef554eb16d268c8a16791ddf353f43d2dc
Change-Id: If90bdccee3313723794b65e6aa78c2815f817cd4