[roll] Roll fuchsia [libc] Preserve vector registers in RISC-V TLSDESC

Now that Fuchsia has enable support for the V extension for riscv64
targets, the TLSDESC implementation needs to ensure that none of those
registers can be clobbered as a side effect when calling __tls_get_new.

Original-Bug: 323265072
Original-Bug: 325518247
Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/1004581
Original-Revision: 1dca5e8c362104a7299c1ad589ddc3a306efd78c
GitOrigin-RevId: 0aa34632d05507e9d144053abe58e6073e272748
Change-Id: I3c2b86994bb4c99eadef93e5076232f54740e621
1 file changed
tree: e1c60972d69cf3ffa5e0636ca6463b5131c6548c
  1. ctf/
  2. git-hooks/
  3. infra/
  4. third_party/
  5. cts
  6. firmware
  7. flower
  8. jiri.lock
  9. MILESTONE
  10. minimal
  11. prebuilts
  12. README.md
  13. stem
  14. test_durations
  15. toolchain
README.md

Integration

This repository contains Fuchsia's Global Integration manifest files.

Making changes

All changes should be made to the internal version of this repository. Our infrastructure automatically updates this version when the internal one changes.

Currently all changes must be made by a Google employee. Non-Google employees wishing to make a change can ask for assistance via the IRC channel #fuchsia on Freenode.

Obtaining the source

First install Jiri.

Next run:

$ jiri init
$ jiri import minimal https://fuchsia.googlesource.com/integration
$ jiri update

Third party

Third party projects should have their own subdirectory in ./third_party.