| commit | ed727caf9cc33d12763e23e581d892798f1b5a35 | [log] [tgz] |
|---|---|---|
| author | Joshua Seaton <joshuaseaton@fuchsia.infra.roller.google.com> | Fri Jul 09 03:15:07 2021 +0000 |
| committer | Copybara-Service <copybara-worker@google.com> | Thu Jul 08 20:16:22 2021 -0700 |
| tree | 91b4f8e9cf45529281e9daa00ddee3a5b7daee6a | |
| parent | b18ae302ca4f97aa0e23f39ba46bb58cf359be3a [diff] |
[roll] Roll fuchsia [vmm][arm64] Always report that the UART TX FIFO is empty PL011 gives separate TX FIFO "full" and "empty" bits; currently the hypervisor always reports that both are false - so, in particular, that the FIFO is never empty. It is a reasonable expectation for any driver that this FIFO should eventually be empty - and we have a platform driver that does expect this. Accordingly - and since incoming data in the emulated UART is immediately processed - this change updates the hypervisor to always report that the TX FIFO is empty. Original-Bug: 80376 Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/553322 Original-Revision: 69698d9be99e141037c9947115211b64bad419c4 GitOrigin-RevId: 54b75960b484c430618876cc4a3c910e99546886 Change-Id: I2b6763e5375d906bed47e47856b7eada68e0dcd0
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