[roll] Roll fuchsia [kernel][x86] Enumerate SPEC_CTRL before writing to SPEC_CTRL MSR Fixes Fuchsia boot on processors with ARCH_CAPABILITIES, Enhanced IBRS (IBRS_ALL) enumerated, but without the SPEC_CTRL MSR. It is possible that such CPUID combinations only exist within hypervisor guests. 1) ARCH_CAPABILITIES.IBRS_ALL implies that a processor supports 'enhanced IBRS'; When enhanced IBRS is reported, the IBRS mode (which splits predictor state based on 'mode', such as kernel/ user or vm guest/host) can always be enabled and STIBP is not required cross hyper-thread. 2) IBRS (both enhanced and regular) are enabled by writing to bit 0 of MSR 0x48, SPEC_CTRL. 3) However, SPEC_CTRL is only defined to exist if any CPUID bit for: IBPB, STIBP, or SSBD are present. It is _not_ defined to exist if only IBRS_ALL (in ARCH_CAPABILITIES) is set. Only enable enhanced IBRS if SPEC_CTRL is enumerated; otherwise, we are in a situation where we "have to" turn it on, but don't have a way to do so. Original-Bug: 33667 Spectre mitigations? Original-Bug: 12540 Speculative Execution Mitigations. Original-Bug: 67147 QEMU host tests fail to boot on N2 (Cascade Lack) GCE VMs Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/467615 Original-Revision: 2fd0875bc6321f8f87d0a0d531bb098cff79e3ce GitOrigin-RevId: 0b08a9435c997ee91a539b99098773eef9a2fa50 Change-Id: Iea30d011327f174c4ded9726a2984c3d0cfdf944
This repository contains Fuchsia's Global Integration manifest files.
All changes should be made to the internal version of this repository. Our infrastructure automatically updates this version when the internal one changes.
Currently all changes must be made by a Google employee. Non-Google employees wishing to make a change can ask for assistance via the IRC channel #fuchsia on Freenode.
First install Jiri.
Next run:
$ jiri init $ jiri import minimal https://fuchsia.googlesource.com/integration $ jiri update
Third party projects should have their own subdirectory in ./third_party.