[roll] Roll fuchsia [vmm] VirtioQueueFake: ensure descriptor data is properly aligned

Currently, VirtioQueueFake ensures the first descriptor's data is
aligned but does not make similar guarantees for subsequent descriptors.
For example, the following code has undefined behavior on some
architectures because resp->status is not 8-byte aligned.

  struct Req {
    uint8_t code;
  }
  struct Resp {
    uint64_t status;
  }
  Req req;
  Resp* resp;
  DescriptorChainBuilder(q)
      .AppendReadableDescriptor(&req, sizeof(req))
      .AppendWritableDescriptor(&resp, sizeof(*resp))
      .Build();
  // ... wait for response
  EXPECT_EQ(resp->status, 1);  // UB: unaligned access

To fix this, VirtioQueueFake::WriteDesc now ensures data_begin_ is
aligned after writing each descriptor.

Tested in the follow-up CL: tests in that CL pass with this change, but
have UBSan failures without this change.

Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/612412
Original-Revision: 8f44b6fcc0bba1a948ef619d7b023013360d8f58
GitOrigin-RevId: 259217289da27f3a7bb1071f1d9a1896c5df203b
Change-Id: Ie18c851a2a73773c060916a0d114791850666ca7