[roll] Roll fuchsia [intel-i915] Expanded PCH panel control logic.

This CL implements the following functionality.

* Expanded definitions for the registers related to PCH (South display
  engine) panel power and brightness.
* A new PchEngine class that is responsible for interpreting the values
  of the PCH registers and coordinating changes to these registers.
* Re-configuring PCH registers (clocking, panel power sequence, panel
  brightness PWM) if the configuration left by the boot firmware is
  obviously incorrect.
* Driving the PCH through the panel power sequence.

The implementation is based on the Intel PRMs for Kaby Lake, Sky Lake
(similar to Kaby Lake), Tiger Lake, and DG1. We also refer to DG1
because the Tiger Lake PRM only got definitions for the PCH registers
very recently, and our implementation was mainly developed against the
DG1 documentation. Our experiments showed that the registers described
in the DG1 manual exist on Tiger Lake, which was confirmed by the
updated Tiger Lake PRMs.

The new PchEngine class is integrated with i915::Controller and
DpDisplay. All direct accesses to PCH-related MMIO registers are
replaced with PchEngine functionality, so PchEngine becomes the only
class that accesses these registers.

Original-Bug: 83825
Tested: fx test //src/graphics/display/drivers/intel-i915
Tested: fx shell display-tool squares
Tested: Atlas with Secure Boot enabled boots into core.x64
Tested: Atlas in Dev Mode still boots into core.x64
Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/707284
Original-Revision: bbbc139ceef03d035e1056363cafce7984b5763d
GitOrigin-RevId: a1d145ec44c237f50e6df687f90952bc00146559
Change-Id: I0d60085b9755ee0c9a69692b8c0189855179a00f