[roll] Roll fuchsia [libc] Link libc.so with -z rela on riscv64 when instrumented The runtime instrumentation in libc.so causes many more relocs than usual. In ld.so, there's a limit to the number of relocs it can have itself when those are DT_REL relocs with addends. On RISC-V, there is no separate GOT reloc type that doesn't use addends, so most of the additional relocs require them. This pushes it over the limit of the addend-saving hack used for ld.so's double-relocation. Since DT_RELA relocs don't require this hack, link libc with `-z rela` to counteract the compiler driver's default `-z rel` so it has DT_RELA instead of DT_REL. Original-Fixed: 126753 Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/853538 Original-Revision: 4cc6a1be6a6f5841604769e5bdde30790b2fa8da GitOrigin-RevId: 7926ae948f7f1dd29717fe34bcdd0de428a47ad9 Change-Id: Id85d58f70a22460139eeaaa730cad1a4c4951a28
This repository contains Fuchsia's Global Integration manifest files.
All changes should be made to the internal version of this repository. Our infrastructure automatically updates this version when the internal one changes.
Currently all changes must be made by a Google employee. Non-Google employees wishing to make a change can ask for assistance via the IRC channel #fuchsia on Freenode.
First install Jiri.
Next run:
$ jiri init $ jiri import minimal https://fuchsia.googlesource.com/integration $ jiri update
Third party projects should have their own subdirectory in ./third_party.