[roll] Roll fuchsia [intel-i915] Refactor CDCLK frequency setup code. This change moves CDCLK (Core display clock) setup code to a separate file (clock/cdclk.h, cdclk.cc) and added a common interface for CDCLK for all platforms. This allows us to add CDCLK frequency setup logic for other platforms (e.g. Tiger lake) and use it in intel-i915 controller. Original-Bug: 95863 Test: Refactor only. no-op. Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/680309 Original-Revision: d4577d62b96d250f6308f1b8555b6f81bfca1fc9 GitOrigin-RevId: b8243afce65f7db118c892106ef45f4cab99ad7f Change-Id: I19d2f1943106980b99fab49979b25e147cccb193
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Next run:
$ jiri init $ jiri import minimal https://fuchsia.googlesource.com/integration $ jiri update
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