[roll] Roll fuchsia [amlogic-display][hdmi] Allow lower HDMI PLL DCO frequency if the pixel
clock is very low.
When the pixel clock is very low (e.g. on Surenoo SUR480480Y021A
the pixel clock can be as low as 16.96 MHz), the frequency of the
HDMI PLL DCO has to be lowered to 2.7 GHz in order to keep the
correct aspect ratio.
This change adds a new method
GetHdmiPllValidDcoFrequencyRange(pixel_clock_khz), so that the driver
can check and set the DCO frequency based on the desired pixel clock.
Test: "display-tool squares 1" on VIM3 with Surenoo SUR480480Y021A (low
pixel clock), the aspect ratio is 1:1.
Test: "display-tool squares 1" on VIM3 with MIMO (high pixel clock)
Original-Bug: b/301330744
Original-Bug: b/306236155
Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/934312
Original-Revision: 4a27de6e205c11932365b362b82ae6184baa48d7
GitOrigin-RevId: 926c7a3c8f21eb4b134187f8e3a5adde20dffa5e
Change-Id: If12bac06b94f99ac650b40b7ce4becaf7bb2d952
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