[roll] Roll fuchsia [arch][arm] tweak global cache coherency context manager to add additional barriers In the case of the cpu signalling that it doesn't need the data cache to be written out before flushing the i cache, make sure a data barrier is always present before potentially flushing the i cache to make sure it at least gets the freshest of data. In the case where the cpu signals that it does not need an icache invalidation to synchronize the caches, make sure an ISB is issued. Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/1447110 Original-Revision: 8de67bd4366e686c43047157fd61c01420af0daf GitOrigin-RevId: a455bf1b69c807bbcdf429b190251a9d5c98d3be Change-Id: Ice0d568a5cc8d7aaba0706156a6796541b2dd017
This repository contains Fuchsia's Global Integration manifest files.
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First install Jiri.
Next run:
$ jiri init $ jiri import minimal https://fuchsia.googlesource.com/integration $ jiri update
Third party projects should have their own subdirectory in ./third_party.