[roll] Roll fuchsia [kernel][riscv64] Clean D-cache in arch_sync_cache_range On RISC-V 64, synchronizing the instruction cache requires cleaning the data cache first if Zicbom is present. Otherwise, fence.i might synchronize with stale data in main memory. Add arch_clean_cache_range call to arch_sync_cache_range for kernel addresses. Update Riscv64VmICacheConsistencyManager to clean the D-cache in SyncAddr and broadcast fence.i directly in Finish to avoid redundant cleaning. Original-Original-Bug: 517178004 Original-Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/1661280 Original-Original-Revision: 168c88a423948404dbdc791442a7e6c217c4f856 GitOrigin-RevId: aacbb9786a3e9cd84dbda799d1896d9de28c64e6 Change-Id: I3aa0c992545234c4d949f1124c2a65b19a4219a3 Reviewed-on: https://fuchsia-review.googlesource.com/c/integration/+/1673055 Cr-Commit-Position: refs/heads/main@{#195298}
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