[roll] Roll fuchsia [kernel][x86][mmu] Make sure we put the CR4.PGE bit back after clearing it in a global tlb invalidate As a result the first time we do a global invalidate on any given cpu, the PGE bit was cleared and then never set again. As a result all global pages were turned off for the rest of the system. Substantial performance is being dropped on the floor as a result of this, since the cpu now loses all kernel pages when it context switches between processes. Was wiped out in a previous refactoring of the code in February 2021. Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/753522 Original-Revision: 6180236bf6ea0bc9682bd4517715693d7678d102 GitOrigin-RevId: 2d984a7586830b7f9b233a00e8ff5332a1878c3b Change-Id: I77cdd8249fbdca7b63dab6de71cc1e97a1f98cf7
This repository contains Fuchsia's Global Integration manifest files.
All changes should be made to the internal version of this repository. Our infrastructure automatically updates this version when the internal one changes.
Currently all changes must be made by a Google employee. Non-Google employees wishing to make a change can ask for assistance via the IRC channel #fuchsia on Freenode.
First install Jiri.
Next run:
$ jiri init $ jiri import minimal https://fuchsia.googlesource.com/integration $ jiri update
Third party projects should have their own subdirectory in ./third_party.