[roll] Roll fuchsia [display][i915] Strong typing for DPLL_CTRL1 link rate values

The DPLL_CTRL1 register allows the DisplayPort-mode link rate for DPLLs
to be programmed by writing one of 6 discrete values that represent DP
link rates. These values do not equal the numeric values they represent;
instead they are index numbers that are defined to correspond to
specific values (e.g 0 => 5.4 GHz, 1 => 2.7 GHz, etc).

To better represent this distinction and to prevent implicit conversion
to/from a numeric type representing an actual link rate, an enum-class
type has been introduced in place of the existing integer type
constants.

In addition:
- Introduced helpers to convert between the DPLL_CTRL1 register link
rate values and actual numeric values.
- DpDisplay::ComputeDpllState will now result in an error if the
selected display port link clock is not one of the frequences that Intel
DPLLs are capable of (i.e. 1620, 2160, 2700, 3240, 4320, 5400). This
also means that more frequencies are now supported compared to before.
- Fixed camel-case naming convention for some snake-case helpers.
- Ran clang-format.

Original-Bug: 78470
Test: intel-i915-test
Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/589002
Original-Revision: 39ea1b3d7d8acb581d1964425f6804467a1d8ed4
GitOrigin-RevId: 99f1cacb3eba343bf4d021c1c0edf059fd77423e
Change-Id: I133555dcd4a5c15824d20c140d6a54906727e580