commit 22a156c83247ee9a8bd4dc2548c0147751687b42
author Victor Costan <costan@fuchsia.infra.roller.google.com> Wed Nov 09 06:05:05 2022 +0000
committer Copybara-Service <copybara-worker@google.com> Tue Nov 08 22:06:23 2022 -0800
tree c8a335815c9d1d4645bb3541ad8cb43b4fa52692
parent 4eb9f22e1ae5f3229b8168c5db7a577669dca35e

[roll] Roll fuchsia [intel-i915-tgl] Tiger Lake combo DDI PHY register definitions.

Intel's documentation is fairly minimal around these registers. For this
reason, we combined information from all the PRMs (DG1, Ice Lake) that
seem to cover the same combo PHY registers.

Original-Bug: 112730
Test: fx test intel-i915-tgl-test.cm
Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/745444
Original-Revision: d8d3ae8a0d4fb3dd84a021fe91617dbfe9822a89
GitOrigin-RevId: 5c34d115f7c0331c05224a2ec3e963808a999dba
Change-Id: Iad962a7ab2f4618dd4793585e75e0130e539d90e

stem

diff --git a/stem b/stem
index ddc2a9c..8486a3a 100644
--- a/stem
+++ b/stem
@@ -11,7 +11,7 @@
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              remote="https://fuchsia.googlesource.com/fuchsia"
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-             revision="fdee5acedade45a38476c8d25ceeb6073f1c4fb4"/>
+             revision="d8d3ae8a0d4fb3dd84a021fe91617dbfe9822a89"/>
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