| commit | 22a156c83247ee9a8bd4dc2548c0147751687b42 | [log] [tgz] |
|---|---|---|
| author | Victor Costan <costan@fuchsia.infra.roller.google.com> | Wed Nov 09 06:05:05 2022 +0000 |
| committer | Copybara-Service <copybara-worker@google.com> | Tue Nov 08 22:06:23 2022 -0800 |
| tree | c8a335815c9d1d4645bb3541ad8cb43b4fa52692 | |
| parent | 4eb9f22e1ae5f3229b8168c5db7a577669dca35e [diff] |
[roll] Roll fuchsia [intel-i915-tgl] Tiger Lake combo DDI PHY register definitions. Intel's documentation is fairly minimal around these registers. For this reason, we combined information from all the PRMs (DG1, Ice Lake) that seem to cover the same combo PHY registers. Original-Bug: 112730 Test: fx test intel-i915-tgl-test.cm Original-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/745444 Original-Revision: d8d3ae8a0d4fb3dd84a021fe91617dbfe9822a89 GitOrigin-RevId: 5c34d115f7c0331c05224a2ec3e963808a999dba Change-Id: Iad962a7ab2f4618dd4793585e75e0130e539d90e
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