)]}'
{
  "commit": "03b92fd2b9c3de34867eacfa4f0ae2e1f125f534",
  "tree": "3c0552be1a71cb1a32257d667faf6f26bf1f403e",
  "parents": [
    "8415bae5b0613ca3d2c77d7e9a0fedcc3ea8bf63"
  ],
  "author": {
    "name": "Travis Geiselbrecht",
    "email": "travisg@fuchsia.infra.roller.google.com",
    "time": "Fri Jan 23 16:24:03 2026 -0800"
  },
  "committer": {
    "name": "Copybara-Service",
    "email": "copybara-worker@google.com",
    "time": "Fri Jan 23 16:24:43 2026 -0800"
  },
  "message": "[roll] Roll fuchsia [kernel][arm64] explicitly insert an ISB when using the AT instruction\n\nAs documented in the ARM ARM under the section \"Address translation\ninstructions\", explicit synchronization must be done after using the AT\ninstruction and before reading the PAR_EL1 register that the instruction\nmodifies. This is consistent with the general requirement that you must\nsynchronize after modifying any control register that affects the output\nof another, or to definitively see the result of the modification at\nall.\n\nOriginal-Bug: 477979595\nOriginal-Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/1483761\nOriginal-Revision: b2fd0a80fba9c6c9f680b950544d0b249c3f034f\nGitOrigin-RevId: 59e8b91b1425e0168bcd487950f45bed8e0f560b\nChange-Id: I11591ae0271de0859ba2adef1ccc51bb5b5bddef\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a85082d908face4730c3516b77a8f08f796e1ed2",
      "old_mode": 33188,
      "old_path": "stem",
      "new_id": "f59e4ca7169fb6324903f894d963be7802705130",
      "new_mode": 33188,
      "new_path": "stem"
    }
  ]
}