sdk/fidl/fuchsia.hardware.dsi/dsi.fidl

// Copyright 2020 The Fuchsia Authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
library fuchsia.hardware.dsi;
using zx;

const MAX_PAYLOAD_SIZE uint32 = 64;

// This enum is used to configure DSI interface in either Video or Command mode
type DsiMode = strict enum : uint8 {
    VIDEO = 1;
    COMMAND = 2;
};

// This enum is used to configure the type of video mode
type VideoMode = strict enum : uint8 {
    NON_BURST_PULSE = 1;
    NON_BURST_EVENT = 2;
    BURST = 3;
};

/// Supported color codes for the DSI interface
type ColorCode = strict enum : uint8 {
    PACKED_16BIT_565 = 1;
    PACKED_18BIT_666 = 2;
    LOOSE_24BIT_666 = 3;
    PACKED_24BIT_888 = 4;
};

// This is the top level table used to populated all DSI configuration registers
/// Vendor-provided configurations based on hardware/lcd type.
type DisplaySetting = table {
    1: lane_num uint32;
    2: bit_rate_max uint32;
    3: clock_factor uint32;
    4: lcd_clock uint32;
    5: h_active uint32;
    6: v_active uint32;
    7: h_period uint32;
    8: v_period uint32;
    9: hsync_width uint32;
   10: hsync_bp uint32;
   11: hsync_pol uint32;
   12: vsync_width uint32;
   13: vsync_bp uint32;
   14: vsync_pol uint32;
};

/// Vendor specific data
type VendorConfig = table {
    1: lp_escape_time uint32;
    2: lp_cmd_pkt_size uint32;
    3: phy_timer_clkhs_to_lp uint32;
    4: phy_timer_clklp_to_hs uint32;
    5: phy_timer_hs_to_lp uint32;
    6: phy_timer_lp_to_hs uint32;
    7: auto_clklane uint8;
};

/// Complete MIPI-DSI and MIPI D-PHY configuration information
type DsiConfig = table {
    1: display_setting DisplaySetting;
    2: video_mode_type VideoMode;
    3: color_coding ColorCode;
    4: vendor_config VendorConfig;
};

/// Generic MIPI-DSI command structure
type MipiDsiCmd = table {
    1: virtual_channel_id uint8;
    2: dsi_data_type uint8; // DSI data type as defined by mipi-dsi library
    3: write_length uint32; // Write length in bytes
    4: expected_read_length uint32; // Expected read length in bytes
    5: flags uint32; // optional flags as defined by mipi-dsi library
};

@discoverable
protocol DsiBase {
    /// This function is used to send a MIPI-DSI command.
    SendCmd(struct {
        cmd MipiDsiCmd;
        txdata vector<uint8>:MAX_PAYLOAD_SIZE;
    }) -> (struct {
        rxdata vector<uint8>:MAX_PAYLOAD_SIZE;
    }) error zx.status;
};

@discoverable
protocol DsiExtended {
    compose DsiBase;
    /// This function is used to configure all the DSI parameters needed to operated in both
    /// Command and Video Mode.
    Config(struct {
        dsi_config DsiConfig;
    }) -> (struct {}) error zx.status;
    /// This function is called to power up the DSI interface.
    PowerUp() -> ();
    /// This function is called to power down the DSI interface.
    PowerDown() -> ();
    /// This function is used to change modes between Video and Command.
    SetMode(struct {
        mode DsiMode;
    }) -> ();
    /// This function returns true if the DSI IP block is powered on and not in reset.
    IsPoweredUp() -> (struct {
        on bool;
    });
    /// This function resets the DSI IP block.
    Reset() -> ();
    /// This function configures the MIPI D-PHY block if it exists within the DSI IP block.
    PhyConfig(struct {
        dsi_config DsiConfig;
    }) -> (struct {}) error zx.status;
    /// This function is used to power up the MIPI D-PHY block.
    PhyPowerUp() -> ();
    /// This function is used to power down the MIPI D-PHY block.
    PhyPowerDown() -> ();
    /// This function is used to communicate with the MIPI D-PHY block.
    PhySendCode(struct {
        code uint32;
        parameter uint32;
    }) -> ();
    /// This function returns ZX_OK once MIPI D-PHY block is ready. MIPI D-PHY block is
    /// considered ready once the LOCK Bit and StopStateClk bit are set.
    PhyWaitForReady() -> (struct {}) error zx.status;
    /// This function allows writing to any register within the DSI IP block. This could be used
    /// for debug purposes during development stages.
    WriteReg(struct {
        reg uint32;
        val uint32;
    }) -> (struct {}) error zx.status;
    /// This function returns the value of any register within the DSI IP block.
    ReadReg(struct {
        reg uint32;
    }) -> (struct {
        val uint32;
    }) error zx.status;
    /// This function enables Built-In Self-Test (BIST) pattern generation.
    EnableBist(struct {
        pattern uint32;
    }) -> (struct {}) error zx.status;
    /// This function prints the value of all DSI IP block registers.
    PrintDsiRegisters() -> ();
};