[amlogic-display][dsi][clock] Do not use the hardcoded PLL / DSI clock
ratio for LCD panels.
Some LCD panel vendors provided hardcoded PLL / DSI clock ratios
for their LCD panels, while some used automatically calculated
clock ratios.
Since the calculated clock ratios always match the hardcoded values,
this change removes all the hardcoded values and make all displays
to use the automatically calculated values.
This change also adds a test to verify that the calculated clock
ratio matches the original hardcoded values for the affected display
panels.
Test: added PllTimingHdmiPllClockRatioCalculatedCorrectly to clock-test
Test: core.astro, core.nelson and core.sherlock booted (using the
affected panels)
Change-Id: Ie2c4721b14a92977ef31dd2951dc4cac207cb60e
Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/970959
Reviewed-by: Victor Costan <costan@google.com>
Commit-Queue: Yilong Li <liyl@google.com>
diff --git a/display/drivers/amlogic-display/clock-test.cc b/display/drivers/amlogic-display/clock-test.cc
index 9fdf44a..94cc5de 100644
--- a/display/drivers/amlogic-display/clock-test.cc
+++ b/display/drivers/amlogic-display/clock-test.cc
@@ -15,7 +15,7 @@
namespace {
-const display_setting_t kDisplaySettingsWithoutClockFactor = {
+const display_setting_t kDisplaySettingsWithoutHdmiPllClockRatio = {
.lane_num = 4,
.bit_rate_max = 400,
.clock_factor = 0, // auto
@@ -33,9 +33,13 @@
};
static display_setting_t display_types[] = {
- kDisplaySettingTV070WSM_FT, kDisplaySettingP070ACB_FT, kDisplaySettingG101B158_FT,
- kDisplaySettingTV101WXM_FT, kDisplaySettingKD070D82_FT, kDisplaySettingTV070WSM_ST7703I,
- kDisplaySettingsWithoutClockFactor,
+ kDisplaySettingTV070WSM_FT,
+ kDisplaySettingP070ACB_FT,
+ kDisplaySettingG101B158_FT,
+ kDisplaySettingTV101WXM_FT,
+ kDisplaySettingKD070D82_FT,
+ kDisplaySettingTV070WSM_ST7703I,
+ kDisplaySettingsWithoutHdmiPllClockRatio,
};
// For now, simply test that timing calculations don't segfault.
@@ -52,6 +56,34 @@
}
}
+TEST(AmlogicDisplayClock, PllTimingHdmiPllClockRatioCalculatedCorrectly) {
+ // The LCD vendor-provided display settings hardcode the HDMI PLL / DSI
+ // clock ratio while the settings below requires the clock ratios to be
+ // calculated automatically.
+ //
+ // This test ensures that the calculated clock ratios match the hardcoded
+ // values removed in Ie2c4721b14a92977ef31dd2951dc4cac207cb60e.
+ zx::result<PllConfig> pll_tv070wsm_ft = Clock::GenerateHPLL(kDisplaySettingTV070WSM_FT);
+ static constexpr int kExpectedHdmiPllClockRatioTv070wsmFt = 8;
+ EXPECT_OK(pll_tv070wsm_ft.status_value());
+ EXPECT_EQ(kExpectedHdmiPllClockRatioTv070wsmFt, static_cast<int>(pll_tv070wsm_ft->clock_factor));
+
+ zx::result<PllConfig> pll_p070acb_ft = Clock::GenerateHPLL(kDisplaySettingP070ACB_FT);
+ static constexpr int kExpectedHdmiPllClockRatioP070acbFt = 8;
+ EXPECT_OK(pll_p070acb_ft.status_value());
+ EXPECT_EQ(kExpectedHdmiPllClockRatioP070acbFt, static_cast<int>(pll_p070acb_ft->clock_factor));
+
+ zx::result<PllConfig> pll_g101b158_ft = Clock::GenerateHPLL(kDisplaySettingG101B158_FT);
+ static constexpr int kExpectedHdmiPllClockRatioG101b158 = 8;
+ EXPECT_OK(pll_g101b158_ft.status_value());
+ EXPECT_EQ(kExpectedHdmiPllClockRatioG101b158, static_cast<int>(pll_g101b158_ft->clock_factor));
+
+ zx::result<PllConfig> pll_tv101wxm_ft = Clock::GenerateHPLL(kDisplaySettingTV101WXM_FT);
+ static constexpr int kExpectedHdmiPllClockRatioTv101wxmFt = 8;
+ EXPECT_OK(pll_tv101wxm_ft.status_value());
+ EXPECT_EQ(kExpectedHdmiPllClockRatioTv101wxmFt, static_cast<int>(pll_tv101wxm_ft->clock_factor));
+}
+
} // namespace
} // namespace amlogic_display
diff --git a/display/lib/device-protocol-display/include/lib/device-protocol/display-panel.h b/display/lib/device-protocol-display/include/lib/device-protocol/display-panel.h
index 588935e..5adda83 100644
--- a/display/lib/device-protocol-display/include/lib/device-protocol/display-panel.h
+++ b/display/lib/device-protocol-display/include/lib/device-protocol/display-panel.h
@@ -31,7 +31,9 @@
const display_setting_t kDisplaySettingTV070WSM_FT = {
.lane_num = 4,
.bit_rate_max = 360,
- .clock_factor = 8,
+ // The vendor-provided configuration hard-coded this to 8. This is not
+ // necessary, because our clocking code produces the same value.
+ .clock_factor = 0,
.lcd_clock = 44250000,
.h_active = 600,
.v_active = 1024,
@@ -47,7 +49,9 @@
const display_setting_t kDisplaySettingP070ACB_FT = {
.lane_num = 4,
.bit_rate_max = 400,
- .clock_factor = 8,
+ // The vendor-provided configuration hard-coded this to 8. This is not
+ // necessary, because our clocking code produces the same value.
+ .clock_factor = 0,
.lcd_clock = 49434000,
.h_active = 600,
.v_active = 1024,
@@ -63,7 +67,9 @@
const display_setting_t kDisplaySettingG101B158_FT = {
.lane_num = 4,
.bit_rate_max = 566,
- .clock_factor = 8,
+ // The vendor-provided configuration hard-coded this to 8. This is not
+ // necessary, because our clocking code produces the same value.
+ .clock_factor = 0,
.lcd_clock = 70701600,
.h_active = 800,
.v_active = 1280,
@@ -79,7 +85,9 @@
const display_setting_t kDisplaySettingTV101WXM_FT = {
.lane_num = 4,
.bit_rate_max = 566,
- .clock_factor = 8,
+ // The vendor-provided configuration hard-coded this to 8. This is not
+ // necessary, because our clocking code produces the same value.
+ .clock_factor = 0,
.lcd_clock = 70701600,
.h_active = 800,
.v_active = 1280,
