tree 5845361c6f7cc66a843368d2ed1165d5ecf7c2e3
parent b4b301cfdd6233d597df3f84798632361b3ed87a
author John Grossman <johngro@google.com> 1488315333 -0800
committer John Grossman <johngro@google.com> 1488317893 -0800

[intel-hda] Update SRST bit behavior in the stream control register.

According to the documentation, the SRST bit in the {IOB}SDnCTL
register is sticky bit.  Software is supposed to write a 1 to this bit
in order to begin the process or resetting the stream hardware.
Hardware is supposed to report a 1 once it has run the complete reset
cycle.  At this point, software is supposed to write a 0 and (once
again) wait until the HW ack acknowledged a release from reset by
reporting a 0 in the readback of this bit.

Previously, QEMU's emulation of the hardware would reset the contents
of the Status and Control registers, but it would not report a 1 in
the reset bit.

Now, the emulated hardware will immediately acknowledge the reset by
reporting a 1 in the SRST bit and reset the values contained in all of
the stream descriptor registers.  Subsequent writes to the register
will be ignored until the SRST bit has been cleared.

See section 3.3.35 of the Intel High Definition Audio Specification
Rev 1.0a dated June 17, 2010

Change-Id: I4d4bfc6a7b75a014cc6145fc457a54f604d44a66